Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8372194 |
1 |
|
|
T26 |
48 |
|
T27 |
691 |
|
T28 |
405 |
| auto[1] |
6238827 |
1 |
|
|
T26 |
27 |
|
T27 |
520 |
|
T30 |
18536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12038468 |
1 |
|
|
T26 |
44 |
|
T27 |
1086 |
|
T28 |
405 |
| auto[1] |
2572553 |
1 |
|
|
T26 |
31 |
|
T27 |
125 |
|
T30 |
11166 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8361138 |
1 |
|
|
T26 |
43 |
|
T27 |
726 |
|
T28 |
405 |
| auto[1] |
6249883 |
1 |
|
|
T26 |
32 |
|
T27 |
485 |
|
T30 |
18023 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1855504 |
1 |
|
|
T26 |
1 |
|
T27 |
175 |
|
T30 |
3464 |
| auto[1] |
auto[0] |
auto[1] |
1293813 |
1 |
|
|
T26 |
13 |
|
T27 |
60 |
|
T30 |
5704 |
| auto[1] |
auto[1] |
auto[0] |
1821826 |
1 |
|
|
T27 |
185 |
|
T30 |
3393 |
|
T34 |
188 |
| auto[1] |
auto[1] |
auto[1] |
1278740 |
1 |
|
|
T26 |
18 |
|
T27 |
65 |
|
T30 |
5462 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |