Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8386041 |
1 |
|
|
T26 |
61 |
|
T27 |
681 |
|
T28 |
405 |
| auto[1] |
6224980 |
1 |
|
|
T26 |
14 |
|
T27 |
530 |
|
T30 |
19021 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12048886 |
1 |
|
|
T26 |
72 |
|
T27 |
1062 |
|
T28 |
405 |
| auto[1] |
2562135 |
1 |
|
|
T26 |
3 |
|
T27 |
149 |
|
T30 |
11409 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8366261 |
1 |
|
|
T26 |
61 |
|
T27 |
625 |
|
T28 |
405 |
| auto[1] |
6244760 |
1 |
|
|
T26 |
14 |
|
T27 |
586 |
|
T30 |
18569 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1855265 |
1 |
|
|
T27 |
196 |
|
T30 |
3290 |
|
T34 |
427 |
| auto[1] |
auto[0] |
auto[1] |
1292927 |
1 |
|
|
T26 |
2 |
|
T27 |
102 |
|
T30 |
5174 |
| auto[1] |
auto[1] |
auto[0] |
1827360 |
1 |
|
|
T26 |
11 |
|
T27 |
241 |
|
T30 |
3870 |
| auto[1] |
auto[1] |
auto[1] |
1269208 |
1 |
|
|
T26 |
1 |
|
T27 |
47 |
|
T30 |
6235 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |