Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338464 |
1 |
|
|
T26 |
38 |
|
T27 |
569 |
|
T28 |
405 |
| auto[1] |
6272557 |
1 |
|
|
T26 |
37 |
|
T27 |
642 |
|
T30 |
18605 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12040270 |
1 |
|
|
T26 |
73 |
|
T27 |
1084 |
|
T28 |
405 |
| auto[1] |
2570751 |
1 |
|
|
T26 |
2 |
|
T27 |
127 |
|
T30 |
11454 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8344477 |
1 |
|
|
T26 |
60 |
|
T27 |
697 |
|
T28 |
405 |
| auto[1] |
6266544 |
1 |
|
|
T26 |
15 |
|
T27 |
514 |
|
T30 |
17860 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1832137 |
1 |
|
|
T26 |
6 |
|
T27 |
178 |
|
T30 |
3117 |
| auto[1] |
auto[0] |
auto[1] |
1275442 |
1 |
|
|
T27 |
56 |
|
T30 |
5463 |
|
T34 |
316 |
| auto[1] |
auto[1] |
auto[0] |
1863656 |
1 |
|
|
T26 |
7 |
|
T27 |
209 |
|
T30 |
3289 |
| auto[1] |
auto[1] |
auto[1] |
1295309 |
1 |
|
|
T26 |
2 |
|
T27 |
71 |
|
T30 |
5991 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |