Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8355743 |
1 |
|
|
T26 |
43 |
|
T27 |
640 |
|
T28 |
405 |
| auto[1] |
6255278 |
1 |
|
|
T26 |
32 |
|
T27 |
571 |
|
T30 |
18825 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046642 |
1 |
|
|
T26 |
56 |
|
T27 |
1063 |
|
T28 |
405 |
| auto[1] |
2564379 |
1 |
|
|
T26 |
19 |
|
T27 |
148 |
|
T30 |
10811 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8364937 |
1 |
|
|
T26 |
55 |
|
T27 |
468 |
|
T28 |
405 |
| auto[1] |
6246084 |
1 |
|
|
T26 |
20 |
|
T27 |
743 |
|
T30 |
17052 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1834831 |
1 |
|
|
T26 |
1 |
|
T27 |
341 |
|
T30 |
3183 |
| auto[1] |
auto[0] |
auto[1] |
1276460 |
1 |
|
|
T26 |
10 |
|
T27 |
66 |
|
T30 |
5303 |
| auto[1] |
auto[1] |
auto[0] |
1846874 |
1 |
|
|
T27 |
254 |
|
T30 |
3058 |
|
T34 |
500 |
| auto[1] |
auto[1] |
auto[1] |
1287919 |
1 |
|
|
T26 |
9 |
|
T27 |
82 |
|
T30 |
5508 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |