Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403459 |
1 |
|
|
T26 |
42 |
|
T27 |
577 |
|
T28 |
405 |
| auto[1] |
6207562 |
1 |
|
|
T26 |
33 |
|
T27 |
634 |
|
T30 |
17707 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12054085 |
1 |
|
|
T26 |
54 |
|
T27 |
1098 |
|
T28 |
405 |
| auto[1] |
2556936 |
1 |
|
|
T26 |
21 |
|
T27 |
113 |
|
T30 |
10813 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8372054 |
1 |
|
|
T26 |
40 |
|
T27 |
807 |
|
T28 |
405 |
| auto[1] |
6238967 |
1 |
|
|
T26 |
35 |
|
T27 |
404 |
|
T30 |
16635 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1848841 |
1 |
|
|
T26 |
8 |
|
T27 |
116 |
|
T30 |
3009 |
| auto[1] |
auto[0] |
auto[1] |
1280788 |
1 |
|
|
T26 |
3 |
|
T27 |
22 |
|
T30 |
5286 |
| auto[1] |
auto[1] |
auto[0] |
1833190 |
1 |
|
|
T26 |
6 |
|
T27 |
175 |
|
T30 |
2813 |
| auto[1] |
auto[1] |
auto[1] |
1276148 |
1 |
|
|
T26 |
18 |
|
T27 |
91 |
|
T30 |
5527 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |