Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8379545 |
1 |
|
|
T26 |
45 |
|
T27 |
617 |
|
T28 |
405 |
| auto[1] |
6231476 |
1 |
|
|
T26 |
30 |
|
T27 |
594 |
|
T30 |
17231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12053403 |
1 |
|
|
T26 |
61 |
|
T27 |
1063 |
|
T28 |
405 |
| auto[1] |
2557618 |
1 |
|
|
T26 |
14 |
|
T27 |
148 |
|
T30 |
12002 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8381996 |
1 |
|
|
T26 |
60 |
|
T27 |
450 |
|
T28 |
405 |
| auto[1] |
6229025 |
1 |
|
|
T26 |
15 |
|
T27 |
761 |
|
T30 |
19143 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1829498 |
1 |
|
|
T27 |
249 |
|
T30 |
3735 |
|
T34 |
284 |
| auto[1] |
auto[0] |
auto[1] |
1277485 |
1 |
|
|
T26 |
3 |
|
T27 |
89 |
|
T30 |
6348 |
| auto[1] |
auto[1] |
auto[0] |
1841909 |
1 |
|
|
T26 |
1 |
|
T27 |
364 |
|
T30 |
3406 |
| auto[1] |
auto[1] |
auto[1] |
1280133 |
1 |
|
|
T26 |
11 |
|
T27 |
59 |
|
T30 |
5654 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |