Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338863 |
1 |
|
|
T26 |
59 |
|
T27 |
755 |
|
T28 |
405 |
| auto[1] |
6272158 |
1 |
|
|
T26 |
16 |
|
T27 |
456 |
|
T30 |
18223 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12055607 |
1 |
|
|
T26 |
72 |
|
T27 |
1049 |
|
T28 |
405 |
| auto[1] |
2555414 |
1 |
|
|
T26 |
3 |
|
T27 |
162 |
|
T30 |
11090 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8384067 |
1 |
|
|
T26 |
64 |
|
T27 |
575 |
|
T28 |
405 |
| auto[1] |
6226954 |
1 |
|
|
T26 |
11 |
|
T27 |
636 |
|
T30 |
17487 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1837583 |
1 |
|
|
T26 |
8 |
|
T27 |
259 |
|
T30 |
3128 |
| auto[1] |
auto[0] |
auto[1] |
1279527 |
1 |
|
|
T26 |
3 |
|
T27 |
114 |
|
T30 |
5688 |
| auto[1] |
auto[1] |
auto[0] |
1833957 |
1 |
|
|
T27 |
215 |
|
T30 |
3269 |
|
T34 |
298 |
| auto[1] |
auto[1] |
auto[1] |
1275887 |
1 |
|
|
T27 |
48 |
|
T30 |
5402 |
|
T34 |
301 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |