Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8372404 |
1 |
|
|
T26 |
43 |
|
T27 |
612 |
|
T28 |
405 |
| auto[1] |
6238617 |
1 |
|
|
T26 |
32 |
|
T27 |
599 |
|
T30 |
18211 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13817312 |
1 |
|
|
T26 |
75 |
|
T27 |
1198 |
|
T28 |
405 |
| auto[1] |
793709 |
1 |
|
|
T27 |
13 |
|
T30 |
2239 |
|
T34 |
259 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8372391 |
1 |
|
|
T26 |
60 |
|
T27 |
693 |
|
T28 |
405 |
| auto[1] |
6238630 |
1 |
|
|
T26 |
15 |
|
T27 |
518 |
|
T30 |
18517 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2726369 |
1 |
|
|
T26 |
5 |
|
T27 |
202 |
|
T30 |
7876 |
| auto[1] |
auto[0] |
auto[1] |
398261 |
1 |
|
|
T27 |
3 |
|
T30 |
1127 |
|
T34 |
184 |
| auto[1] |
auto[1] |
auto[0] |
2718552 |
1 |
|
|
T26 |
10 |
|
T27 |
303 |
|
T30 |
8402 |
| auto[1] |
auto[1] |
auto[1] |
395448 |
1 |
|
|
T27 |
10 |
|
T30 |
1112 |
|
T34 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |