Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8360350 |
1 |
|
|
T26 |
46 |
|
T27 |
633 |
|
T28 |
405 |
| auto[1] |
6250671 |
1 |
|
|
T26 |
29 |
|
T27 |
578 |
|
T30 |
17864 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13813442 |
1 |
|
|
T26 |
74 |
|
T27 |
1193 |
|
T28 |
405 |
| auto[1] |
797579 |
1 |
|
|
T26 |
1 |
|
T27 |
18 |
|
T30 |
2233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8347638 |
1 |
|
|
T26 |
54 |
|
T27 |
738 |
|
T28 |
405 |
| auto[1] |
6263383 |
1 |
|
|
T26 |
21 |
|
T27 |
473 |
|
T30 |
18658 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2730384 |
1 |
|
|
T26 |
10 |
|
T27 |
255 |
|
T30 |
8139 |
| auto[1] |
auto[0] |
auto[1] |
397686 |
1 |
|
|
T27 |
11 |
|
T30 |
1052 |
|
T34 |
93 |
| auto[1] |
auto[1] |
auto[0] |
2735420 |
1 |
|
|
T26 |
10 |
|
T27 |
200 |
|
T30 |
8286 |
| auto[1] |
auto[1] |
auto[1] |
399893 |
1 |
|
|
T26 |
1 |
|
T27 |
7 |
|
T30 |
1181 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |