Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8366512 |
1 |
|
|
T26 |
60 |
|
T27 |
504 |
|
T28 |
405 |
| auto[1] |
6244509 |
1 |
|
|
T26 |
15 |
|
T27 |
707 |
|
T30 |
17696 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13812238 |
1 |
|
|
T26 |
75 |
|
T27 |
1192 |
|
T28 |
405 |
| auto[1] |
798783 |
1 |
|
|
T27 |
19 |
|
T30 |
2196 |
|
T34 |
240 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8346611 |
1 |
|
|
T26 |
56 |
|
T27 |
598 |
|
T28 |
405 |
| auto[1] |
6264410 |
1 |
|
|
T26 |
19 |
|
T27 |
613 |
|
T30 |
18944 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2741555 |
1 |
|
|
T26 |
14 |
|
T27 |
258 |
|
T30 |
8398 |
| auto[1] |
auto[0] |
auto[1] |
401128 |
1 |
|
|
T27 |
7 |
|
T30 |
1112 |
|
T34 |
116 |
| auto[1] |
auto[1] |
auto[0] |
2724072 |
1 |
|
|
T26 |
5 |
|
T27 |
336 |
|
T30 |
8350 |
| auto[1] |
auto[1] |
auto[1] |
397655 |
1 |
|
|
T27 |
12 |
|
T30 |
1084 |
|
T34 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |