Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8336337 |
1 |
|
|
T26 |
47 |
|
T27 |
556 |
|
T28 |
405 |
| auto[1] |
6274684 |
1 |
|
|
T26 |
28 |
|
T27 |
655 |
|
T30 |
18688 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13818951 |
1 |
|
|
T26 |
75 |
|
T27 |
1192 |
|
T28 |
405 |
| auto[1] |
792070 |
1 |
|
|
T27 |
19 |
|
T30 |
2324 |
|
T34 |
235 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8385832 |
1 |
|
|
T26 |
66 |
|
T27 |
572 |
|
T28 |
405 |
| auto[1] |
6225189 |
1 |
|
|
T26 |
9 |
|
T27 |
639 |
|
T30 |
19158 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2713138 |
1 |
|
|
T26 |
4 |
|
T27 |
333 |
|
T30 |
8073 |
| auto[1] |
auto[0] |
auto[1] |
395072 |
1 |
|
|
T27 |
10 |
|
T30 |
1092 |
|
T34 |
148 |
| auto[1] |
auto[1] |
auto[0] |
2719981 |
1 |
|
|
T26 |
5 |
|
T27 |
287 |
|
T30 |
8761 |
| auto[1] |
auto[1] |
auto[1] |
396998 |
1 |
|
|
T27 |
9 |
|
T30 |
1232 |
|
T34 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |