Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 944
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T765 /workspace/coverage/cover_reg_top/3.gpio_intr_test.4008286037 Jul 15 06:42:32 PM PDT 24 Jul 15 06:42:33 PM PDT 24 23635995 ps
T766 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2673503968 Jul 15 06:43:51 PM PDT 24 Jul 15 06:43:53 PM PDT 24 15705440 ps
T767 /workspace/coverage/cover_reg_top/25.gpio_intr_test.4191513163 Jul 15 06:43:40 PM PDT 24 Jul 15 06:43:41 PM PDT 24 20268710 ps
T768 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.302361829 Jul 15 06:42:19 PM PDT 24 Jul 15 06:42:20 PM PDT 24 20978813 ps
T769 /workspace/coverage/cover_reg_top/40.gpio_intr_test.157866426 Jul 15 06:43:44 PM PDT 24 Jul 15 06:43:45 PM PDT 24 22292546 ps
T770 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.162752358 Jul 15 06:43:00 PM PDT 24 Jul 15 06:43:02 PM PDT 24 59712935 ps
T771 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2128706 Jul 15 06:42:25 PM PDT 24 Jul 15 06:42:27 PM PDT 24 178249746 ps
T772 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2044655005 Jul 15 06:42:04 PM PDT 24 Jul 15 06:42:07 PM PDT 24 278531495 ps
T773 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3996549264 Jul 15 06:43:59 PM PDT 24 Jul 15 06:44:00 PM PDT 24 19771983 ps
T774 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2834788069 Jul 15 06:43:52 PM PDT 24 Jul 15 06:43:54 PM PDT 24 48127869 ps
T775 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4172905597 Jul 15 06:42:41 PM PDT 24 Jul 15 06:42:42 PM PDT 24 80680435 ps
T776 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2485620098 Jul 15 06:43:10 PM PDT 24 Jul 15 06:43:11 PM PDT 24 24626573 ps
T56 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1601514319 Jul 15 06:41:49 PM PDT 24 Jul 15 06:41:50 PM PDT 24 46315920 ps
T777 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3041695102 Jul 15 06:43:04 PM PDT 24 Jul 15 06:43:05 PM PDT 24 31675463 ps
T778 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1686622201 Jul 15 06:43:05 PM PDT 24 Jul 15 06:43:06 PM PDT 24 33076059 ps
T779 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.145912478 Jul 15 06:43:21 PM PDT 24 Jul 15 06:43:22 PM PDT 24 42460800 ps
T780 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3351792943 Jul 15 06:43:10 PM PDT 24 Jul 15 06:43:11 PM PDT 24 28084461 ps
T781 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1313258611 Jul 15 06:42:42 PM PDT 24 Jul 15 06:42:43 PM PDT 24 75364758 ps
T782 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2687874638 Jul 15 06:43:24 PM PDT 24 Jul 15 06:43:25 PM PDT 24 16022245 ps
T49 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1289420341 Jul 15 06:43:12 PM PDT 24 Jul 15 06:43:13 PM PDT 24 109604007 ps
T783 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1570545547 Jul 15 06:42:32 PM PDT 24 Jul 15 06:42:33 PM PDT 24 73004833 ps
T784 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1698640739 Jul 15 06:43:51 PM PDT 24 Jul 15 06:43:52 PM PDT 24 33693562 ps
T785 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.769778038 Jul 15 06:42:31 PM PDT 24 Jul 15 06:42:32 PM PDT 24 262792266 ps
T99 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1798602984 Jul 15 06:42:49 PM PDT 24 Jul 15 06:42:50 PM PDT 24 120232510 ps
T786 /workspace/coverage/cover_reg_top/30.gpio_intr_test.4107715487 Jul 15 06:43:43 PM PDT 24 Jul 15 06:43:44 PM PDT 24 13302940 ps
T787 /workspace/coverage/cover_reg_top/16.gpio_intr_test.109791520 Jul 15 06:43:33 PM PDT 24 Jul 15 06:43:34 PM PDT 24 14102644 ps
T788 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2584443646 Jul 15 06:43:51 PM PDT 24 Jul 15 06:43:52 PM PDT 24 42608645 ps
T115 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.594521942 Jul 15 06:43:04 PM PDT 24 Jul 15 06:43:05 PM PDT 24 224636163 ps
T789 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3042994532 Jul 15 06:42:53 PM PDT 24 Jul 15 06:42:54 PM PDT 24 51039204 ps
T790 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1853603237 Jul 15 06:43:04 PM PDT 24 Jul 15 06:43:05 PM PDT 24 16469057 ps
T791 /workspace/coverage/cover_reg_top/36.gpio_intr_test.40790301 Jul 15 06:43:53 PM PDT 24 Jul 15 06:43:54 PM PDT 24 24128537 ps
T57 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.156751109 Jul 15 06:42:09 PM PDT 24 Jul 15 06:42:10 PM PDT 24 70265390 ps
T792 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2327086761 Jul 15 06:43:47 PM PDT 24 Jul 15 06:43:48 PM PDT 24 11009209 ps
T793 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.645169759 Jul 15 06:42:49 PM PDT 24 Jul 15 06:42:51 PM PDT 24 43668020 ps
T794 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1507609789 Jul 15 06:42:25 PM PDT 24 Jul 15 06:42:26 PM PDT 24 89766143 ps
T795 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1981478891 Jul 15 06:43:21 PM PDT 24 Jul 15 06:43:24 PM PDT 24 457425778 ps
T100 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.90312365 Jul 15 06:43:31 PM PDT 24 Jul 15 06:43:32 PM PDT 24 18042546 ps
T796 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2211238558 Jul 15 06:43:07 PM PDT 24 Jul 15 06:43:08 PM PDT 24 101068378 ps
T797 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1753894799 Jul 15 06:43:09 PM PDT 24 Jul 15 06:43:13 PM PDT 24 59370580 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.230404741 Jul 15 06:42:38 PM PDT 24 Jul 15 06:42:41 PM PDT 24 555248950 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2586921544 Jul 15 06:43:26 PM PDT 24 Jul 15 06:43:27 PM PDT 24 16958631 ps
T800 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2090988125 Jul 15 06:42:03 PM PDT 24 Jul 15 06:42:04 PM PDT 24 64292875 ps
T101 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2376592768 Jul 15 06:42:34 PM PDT 24 Jul 15 06:42:35 PM PDT 24 14333087 ps
T801 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2999146189 Jul 15 06:43:32 PM PDT 24 Jul 15 06:43:33 PM PDT 24 37745725 ps
T802 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2922353819 Jul 15 06:43:38 PM PDT 24 Jul 15 06:43:39 PM PDT 24 11639567 ps
T803 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1627175979 Jul 15 06:43:40 PM PDT 24 Jul 15 06:43:41 PM PDT 24 25740992 ps
T804 /workspace/coverage/cover_reg_top/17.gpio_intr_test.461270326 Jul 15 06:43:32 PM PDT 24 Jul 15 06:43:32 PM PDT 24 17993630 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4026727916 Jul 15 06:43:22 PM PDT 24 Jul 15 06:43:23 PM PDT 24 52444024 ps
T806 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2866231297 Jul 15 06:43:09 PM PDT 24 Jul 15 06:43:11 PM PDT 24 18631402 ps
T807 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3783572517 Jul 15 06:43:52 PM PDT 24 Jul 15 06:43:54 PM PDT 24 11120623 ps
T808 /workspace/coverage/cover_reg_top/35.gpio_intr_test.700377510 Jul 15 06:43:43 PM PDT 24 Jul 15 06:43:44 PM PDT 24 18250299 ps
T809 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3418962778 Jul 15 06:43:45 PM PDT 24 Jul 15 06:43:46 PM PDT 24 14911006 ps
T810 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4261276954 Jul 15 06:43:00 PM PDT 24 Jul 15 06:43:01 PM PDT 24 46240427 ps
T811 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.104199548 Jul 15 06:41:48 PM PDT 24 Jul 15 06:41:49 PM PDT 24 25158663 ps
T812 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3075947742 Jul 15 06:43:04 PM PDT 24 Jul 15 06:43:06 PM PDT 24 47266823 ps
T813 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3268168705 Jul 15 06:43:15 PM PDT 24 Jul 15 06:43:17 PM PDT 24 276748778 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_intr_test.4139265950 Jul 15 06:42:15 PM PDT 24 Jul 15 06:42:16 PM PDT 24 40495205 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.962138420 Jul 15 06:43:35 PM PDT 24 Jul 15 06:43:35 PM PDT 24 44157842 ps
T50 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2427019962 Jul 15 06:43:19 PM PDT 24 Jul 15 06:43:21 PM PDT 24 141513223 ps
T816 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1276321939 Jul 15 06:43:39 PM PDT 24 Jul 15 06:43:40 PM PDT 24 52984054 ps
T817 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1555123724 Jul 15 06:43:10 PM PDT 24 Jul 15 06:43:11 PM PDT 24 26228240 ps
T818 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1355984747 Jul 15 06:41:55 PM PDT 24 Jul 15 06:41:56 PM PDT 24 46006749 ps
T819 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3045184107 Jul 15 06:42:43 PM PDT 24 Jul 15 06:42:44 PM PDT 24 18538829 ps
T102 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1418817998 Jul 15 06:43:22 PM PDT 24 Jul 15 06:43:23 PM PDT 24 14352866 ps
T52 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3695979445 Jul 15 06:43:27 PM PDT 24 Jul 15 06:43:29 PM PDT 24 41612352 ps
T820 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.716027981 Jul 15 06:43:06 PM PDT 24 Jul 15 06:43:09 PM PDT 24 310035713 ps
T53 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.596539618 Jul 15 06:43:32 PM PDT 24 Jul 15 06:43:34 PM PDT 24 48457374 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1171434292 Jul 15 06:42:00 PM PDT 24 Jul 15 06:42:01 PM PDT 24 10759488 ps
T822 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1992628087 Jul 15 06:43:52 PM PDT 24 Jul 15 06:43:53 PM PDT 24 46275674 ps
T823 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1989985921 Jul 15 06:43:45 PM PDT 24 Jul 15 06:43:46 PM PDT 24 13246032 ps
T824 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2267159450 Jul 15 06:43:29 PM PDT 24 Jul 15 06:43:30 PM PDT 24 166975569 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.732111157 Jul 15 06:42:22 PM PDT 24 Jul 15 06:42:24 PM PDT 24 121719578 ps
T826 /workspace/coverage/cover_reg_top/33.gpio_intr_test.971639351 Jul 15 06:43:47 PM PDT 24 Jul 15 06:43:48 PM PDT 24 10202250 ps
T827 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1266949124 Jul 15 06:43:41 PM PDT 24 Jul 15 06:43:42 PM PDT 24 36756649 ps
T828 /workspace/coverage/cover_reg_top/29.gpio_intr_test.4236365411 Jul 15 06:43:59 PM PDT 24 Jul 15 06:44:00 PM PDT 24 12200105 ps
T829 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3684697870 Jul 15 06:42:37 PM PDT 24 Jul 15 06:42:38 PM PDT 24 66913806 ps
T830 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1643011695 Jul 15 06:43:11 PM PDT 24 Jul 15 06:43:13 PM PDT 24 886898373 ps
T116 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2530991361 Jul 15 06:43:29 PM PDT 24 Jul 15 06:43:31 PM PDT 24 221503806 ps
T831 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2145128288 Jul 15 06:43:00 PM PDT 24 Jul 15 06:43:02 PM PDT 24 87641455 ps
T103 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2877038905 Jul 15 06:41:51 PM PDT 24 Jul 15 06:41:52 PM PDT 24 34789510 ps
T832 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.123604785 Jul 15 06:42:25 PM PDT 24 Jul 15 06:42:26 PM PDT 24 277683661 ps
T833 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1532888513 Jul 15 06:43:45 PM PDT 24 Jul 15 06:43:46 PM PDT 24 15996075 ps
T834 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2646586645 Jul 15 06:43:40 PM PDT 24 Jul 15 06:43:41 PM PDT 24 20411570 ps
T835 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.517330505 Jul 15 06:43:04 PM PDT 24 Jul 15 06:43:07 PM PDT 24 83049617 ps
T836 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1266364228 Jul 15 06:42:02 PM PDT 24 Jul 15 06:42:03 PM PDT 24 37466414 ps
T837 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1988671550 Jul 15 06:43:52 PM PDT 24 Jul 15 06:43:56 PM PDT 24 634115949 ps
T838 /workspace/coverage/cover_reg_top/11.gpio_intr_test.651411974 Jul 15 06:43:10 PM PDT 24 Jul 15 06:43:11 PM PDT 24 16526735 ps
T55 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.788744857 Jul 15 06:43:06 PM PDT 24 Jul 15 06:43:08 PM PDT 24 106546487 ps
T839 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1491920846 Jul 15 06:43:11 PM PDT 24 Jul 15 06:43:13 PM PDT 24 2015916396 ps
T840 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.809973216 Jul 15 06:42:27 PM PDT 24 Jul 15 06:42:28 PM PDT 24 17071434 ps
T841 /workspace/coverage/cover_reg_top/6.gpio_intr_test.4258900723 Jul 15 06:42:52 PM PDT 24 Jul 15 06:42:53 PM PDT 24 48751815 ps
T842 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2652538521 Jul 15 06:43:30 PM PDT 24 Jul 15 06:43:32 PM PDT 24 31052180 ps
T843 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3966084127 Jul 15 06:42:32 PM PDT 24 Jul 15 06:42:34 PM PDT 24 120986502 ps
T844 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2882277904 Jul 15 06:42:52 PM PDT 24 Jul 15 06:42:56 PM PDT 24 298677632 ps
T845 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3747473303 Jul 15 06:43:56 PM PDT 24 Jul 15 06:43:58 PM PDT 24 32859622 ps
T846 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.92622261 Jul 15 06:44:20 PM PDT 24 Jul 15 06:44:21 PM PDT 24 147804085 ps
T847 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3758996506 Jul 15 06:44:09 PM PDT 24 Jul 15 06:44:10 PM PDT 24 79227540 ps
T848 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1855103164 Jul 15 06:44:19 PM PDT 24 Jul 15 06:44:20 PM PDT 24 60195619 ps
T849 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1852285473 Jul 15 06:44:30 PM PDT 24 Jul 15 06:44:32 PM PDT 24 90737314 ps
T850 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3244465419 Jul 15 06:44:25 PM PDT 24 Jul 15 06:44:27 PM PDT 24 111556090 ps
T851 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.794928607 Jul 15 06:44:13 PM PDT 24 Jul 15 06:44:14 PM PDT 24 186572916 ps
T852 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23720357 Jul 15 06:44:26 PM PDT 24 Jul 15 06:44:27 PM PDT 24 347114357 ps
T853 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1229951824 Jul 15 06:43:59 PM PDT 24 Jul 15 06:44:00 PM PDT 24 54687303 ps
T854 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.368528918 Jul 15 06:44:07 PM PDT 24 Jul 15 06:44:09 PM PDT 24 41496622 ps
T855 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1022642937 Jul 15 06:43:57 PM PDT 24 Jul 15 06:43:58 PM PDT 24 51350751 ps
T856 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1237886720 Jul 15 06:44:23 PM PDT 24 Jul 15 06:44:24 PM PDT 24 70678911 ps
T857 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1681397360 Jul 15 06:44:21 PM PDT 24 Jul 15 06:44:22 PM PDT 24 84571645 ps
T858 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1540970037 Jul 15 06:44:15 PM PDT 24 Jul 15 06:44:17 PM PDT 24 58941028 ps
T859 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.118901174 Jul 15 06:44:20 PM PDT 24 Jul 15 06:44:21 PM PDT 24 27188659 ps
T860 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2459968295 Jul 15 06:44:03 PM PDT 24 Jul 15 06:44:05 PM PDT 24 145715326 ps
T861 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1653422491 Jul 15 06:44:26 PM PDT 24 Jul 15 06:44:27 PM PDT 24 106293583 ps
T862 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1073452983 Jul 15 06:44:03 PM PDT 24 Jul 15 06:44:04 PM PDT 24 68977697 ps
T863 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1150569365 Jul 15 06:44:29 PM PDT 24 Jul 15 06:44:31 PM PDT 24 78752512 ps
T864 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.451651106 Jul 15 06:44:30 PM PDT 24 Jul 15 06:44:32 PM PDT 24 849878343 ps
T865 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.256683249 Jul 15 06:44:07 PM PDT 24 Jul 15 06:44:09 PM PDT 24 97528364 ps
T866 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1977908067 Jul 15 06:44:15 PM PDT 24 Jul 15 06:44:17 PM PDT 24 39763355 ps
T867 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.176737756 Jul 15 06:44:27 PM PDT 24 Jul 15 06:44:28 PM PDT 24 137803940 ps
T868 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1031076493 Jul 15 06:44:03 PM PDT 24 Jul 15 06:44:04 PM PDT 24 67696223 ps
T869 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912741242 Jul 15 06:43:57 PM PDT 24 Jul 15 06:43:58 PM PDT 24 154416131 ps
T870 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3197537738 Jul 15 06:44:15 PM PDT 24 Jul 15 06:44:17 PM PDT 24 479821209 ps
T871 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2140420900 Jul 15 06:43:57 PM PDT 24 Jul 15 06:43:59 PM PDT 24 99663827 ps
T872 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2289834451 Jul 15 06:43:54 PM PDT 24 Jul 15 06:43:56 PM PDT 24 248765486 ps
T873 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2070993356 Jul 15 06:44:20 PM PDT 24 Jul 15 06:44:21 PM PDT 24 34607633 ps
T874 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2833348517 Jul 15 06:44:13 PM PDT 24 Jul 15 06:44:15 PM PDT 24 46370479 ps
T875 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.572376543 Jul 15 06:43:59 PM PDT 24 Jul 15 06:44:01 PM PDT 24 56935332 ps
T876 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2328573269 Jul 15 06:44:03 PM PDT 24 Jul 15 06:44:05 PM PDT 24 150120190 ps
T877 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4232934001 Jul 15 06:44:02 PM PDT 24 Jul 15 06:44:04 PM PDT 24 324396389 ps
T878 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3212086889 Jul 15 06:44:23 PM PDT 24 Jul 15 06:44:25 PM PDT 24 50981287 ps
T879 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3798072327 Jul 15 06:44:27 PM PDT 24 Jul 15 06:44:29 PM PDT 24 406989563 ps
T880 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.321947436 Jul 15 06:44:29 PM PDT 24 Jul 15 06:44:31 PM PDT 24 76389832 ps
T881 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.861243359 Jul 15 06:44:28 PM PDT 24 Jul 15 06:44:30 PM PDT 24 162647148 ps
T882 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3720962161 Jul 15 06:44:14 PM PDT 24 Jul 15 06:44:15 PM PDT 24 35183266 ps
T883 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3019028063 Jul 15 06:44:18 PM PDT 24 Jul 15 06:44:20 PM PDT 24 321940264 ps
T884 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956637079 Jul 15 06:43:57 PM PDT 24 Jul 15 06:43:59 PM PDT 24 47436278 ps
T885 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4169824957 Jul 15 06:44:29 PM PDT 24 Jul 15 06:44:30 PM PDT 24 150357556 ps
T886 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1103266339 Jul 15 06:43:57 PM PDT 24 Jul 15 06:43:59 PM PDT 24 82879278 ps
T887 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4069050123 Jul 15 06:44:17 PM PDT 24 Jul 15 06:44:19 PM PDT 24 147704691 ps
T888 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.586841299 Jul 15 06:44:26 PM PDT 24 Jul 15 06:44:27 PM PDT 24 52120506 ps
T889 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929084320 Jul 15 06:44:20 PM PDT 24 Jul 15 06:44:22 PM PDT 24 59916768 ps
T890 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2273597773 Jul 15 06:44:26 PM PDT 24 Jul 15 06:44:27 PM PDT 24 76235559 ps
T891 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1309738812 Jul 15 06:44:10 PM PDT 24 Jul 15 06:44:11 PM PDT 24 58493516 ps
T892 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1769630685 Jul 15 06:44:29 PM PDT 24 Jul 15 06:44:30 PM PDT 24 124006239 ps
T893 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1418546548 Jul 15 06:44:05 PM PDT 24 Jul 15 06:44:06 PM PDT 24 874716058 ps
T894 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1078777463 Jul 15 06:44:19 PM PDT 24 Jul 15 06:44:20 PM PDT 24 168523227 ps
T895 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9330251 Jul 15 06:44:34 PM PDT 24 Jul 15 06:44:36 PM PDT 24 407018192 ps
T896 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.261747723 Jul 15 06:43:55 PM PDT 24 Jul 15 06:43:56 PM PDT 24 233514020 ps
T897 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1473194320 Jul 15 06:44:24 PM PDT 24 Jul 15 06:44:26 PM PDT 24 43671653 ps
T898 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.843134079 Jul 15 06:44:00 PM PDT 24 Jul 15 06:44:02 PM PDT 24 53838608 ps
T899 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2262898083 Jul 15 06:44:28 PM PDT 24 Jul 15 06:44:29 PM PDT 24 55588903 ps
T900 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1962888593 Jul 15 06:43:59 PM PDT 24 Jul 15 06:44:01 PM PDT 24 28979900 ps
T901 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863612751 Jul 15 06:44:28 PM PDT 24 Jul 15 06:44:30 PM PDT 24 32481985 ps
T902 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.204655721 Jul 15 06:44:31 PM PDT 24 Jul 15 06:44:33 PM PDT 24 26188710 ps
T903 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1103008649 Jul 15 06:44:24 PM PDT 24 Jul 15 06:44:25 PM PDT 24 41154228 ps
T904 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3470304717 Jul 15 06:44:17 PM PDT 24 Jul 15 06:44:19 PM PDT 24 365742167 ps
T905 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1317690562 Jul 15 06:44:15 PM PDT 24 Jul 15 06:44:17 PM PDT 24 76962917 ps
T906 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3893958427 Jul 15 06:44:13 PM PDT 24 Jul 15 06:44:16 PM PDT 24 108973422 ps
T907 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348316047 Jul 15 06:44:02 PM PDT 24 Jul 15 06:44:04 PM PDT 24 187418660 ps
T908 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.986061801 Jul 15 06:43:53 PM PDT 24 Jul 15 06:43:56 PM PDT 24 357568467 ps
T909 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2636363261 Jul 15 06:43:56 PM PDT 24 Jul 15 06:43:58 PM PDT 24 95994087 ps
T910 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4192510740 Jul 15 06:44:14 PM PDT 24 Jul 15 06:44:16 PM PDT 24 54323438 ps
T911 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2746051104 Jul 15 06:44:28 PM PDT 24 Jul 15 06:44:29 PM PDT 24 40059980 ps
T912 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.204342654 Jul 15 06:43:56 PM PDT 24 Jul 15 06:43:58 PM PDT 24 103393834 ps
T913 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1352017334 Jul 15 06:44:05 PM PDT 24 Jul 15 06:44:07 PM PDT 24 62647618 ps
T914 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2939662106 Jul 15 06:44:14 PM PDT 24 Jul 15 06:44:16 PM PDT 24 272834956 ps
T915 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749443925 Jul 15 06:44:13 PM PDT 24 Jul 15 06:44:14 PM PDT 24 66385226 ps
T916 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2199771900 Jul 15 06:44:02 PM PDT 24 Jul 15 06:44:04 PM PDT 24 51504590 ps
T917 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2038640766 Jul 15 06:43:58 PM PDT 24 Jul 15 06:44:00 PM PDT 24 73559278 ps
T918 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4067067838 Jul 15 06:44:31 PM PDT 24 Jul 15 06:44:32 PM PDT 24 64283622 ps
T919 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1294980288 Jul 15 06:44:28 PM PDT 24 Jul 15 06:44:30 PM PDT 24 47080599 ps
T920 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3976159198 Jul 15 06:44:07 PM PDT 24 Jul 15 06:44:09 PM PDT 24 182173168 ps
T921 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2072359312 Jul 15 06:44:01 PM PDT 24 Jul 15 06:44:02 PM PDT 24 543661035 ps
T922 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1105897923 Jul 15 06:43:58 PM PDT 24 Jul 15 06:44:00 PM PDT 24 42917098 ps
T923 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885038328 Jul 15 06:44:13 PM PDT 24 Jul 15 06:44:14 PM PDT 24 34567949 ps
T924 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1984826318 Jul 15 06:44:26 PM PDT 24 Jul 15 06:44:27 PM PDT 24 30106226 ps
T925 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3695667757 Jul 15 06:44:21 PM PDT 24 Jul 15 06:44:23 PM PDT 24 56713771 ps
T926 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.575888141 Jul 15 06:44:09 PM PDT 24 Jul 15 06:44:10 PM PDT 24 41604807 ps
T927 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3297698981 Jul 15 06:44:24 PM PDT 24 Jul 15 06:44:25 PM PDT 24 60376199 ps
T928 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.536486885 Jul 15 06:44:32 PM PDT 24 Jul 15 06:44:34 PM PDT 24 60006042 ps
T929 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2978338375 Jul 15 06:44:12 PM PDT 24 Jul 15 06:44:14 PM PDT 24 129938773 ps
T930 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3416330405 Jul 15 06:44:24 PM PDT 24 Jul 15 06:44:25 PM PDT 24 327129134 ps
T931 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1100869863 Jul 15 06:44:24 PM PDT 24 Jul 15 06:44:25 PM PDT 24 142909382 ps
T932 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4143667683 Jul 15 06:44:03 PM PDT 24 Jul 15 06:44:05 PM PDT 24 256699453 ps
T933 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2627818643 Jul 15 06:44:32 PM PDT 24 Jul 15 06:44:33 PM PDT 24 272108725 ps
T934 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1866147242 Jul 15 06:44:20 PM PDT 24 Jul 15 06:44:22 PM PDT 24 78881842 ps
T935 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.294532972 Jul 15 06:44:07 PM PDT 24 Jul 15 06:44:08 PM PDT 24 63345931 ps
T936 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3592414303 Jul 15 06:43:57 PM PDT 24 Jul 15 06:43:58 PM PDT 24 30588320 ps
T937 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3656012654 Jul 15 06:44:07 PM PDT 24 Jul 15 06:44:09 PM PDT 24 78413464 ps
T938 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.922774654 Jul 15 06:44:26 PM PDT 24 Jul 15 06:44:28 PM PDT 24 34852624 ps
T939 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.967256526 Jul 15 06:44:29 PM PDT 24 Jul 15 06:44:31 PM PDT 24 182423561 ps
T940 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1043690671 Jul 15 06:43:56 PM PDT 24 Jul 15 06:43:58 PM PDT 24 114097163 ps
T941 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2783276163 Jul 15 06:44:13 PM PDT 24 Jul 15 06:44:15 PM PDT 24 46577203 ps
T942 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.93635839 Jul 15 06:44:22 PM PDT 24 Jul 15 06:44:24 PM PDT 24 209613117 ps
T943 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2895908657 Jul 15 06:43:56 PM PDT 24 Jul 15 06:43:58 PM PDT 24 45405116 ps
T944 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1449245948 Jul 15 06:44:13 PM PDT 24 Jul 15 06:44:15 PM PDT 24 342626390 ps

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.266283027
Short name T35
Test name
Test status
Simulation time 1548603722 ps
CPU time 6.17 seconds
Started Jul 15 07:00:23 PM PDT 24
Finished Jul 15 07:00:29 PM PDT 24
Peak memory 198588 kb
Host smart-d36f743f-fbec-4170-ad83-ae6a7f88e0c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266283027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.266283027
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4058256656
Short name T63
Test name
Test status
Simulation time 38845882 ps
CPU time 1.55 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:02:15 PM PDT 24
Peak memory 198688 kb
Host smart-5c99e1a4-f971-4fd1-9e0c-ecf37936c340
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058256656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4058256656
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.753611616
Short name T39
Test name
Test status
Simulation time 423828424611 ps
CPU time 2380.04 seconds
Started Jul 15 07:02:06 PM PDT 24
Finished Jul 15 07:41:48 PM PDT 24
Peak memory 198948 kb
Host smart-87ae70cb-5a54-4a9c-81a4-616571454af5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=753611616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.753611616
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.299760093
Short name T45
Test name
Test status
Simulation time 356246965 ps
CPU time 1.05 seconds
Started Jul 15 07:00:23 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 215360 kb
Host smart-dab3f39b-ea45-4bf3-bb83-8a309ee3a0fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299760093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.299760093
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2620192915
Short name T95
Test name
Test status
Simulation time 104528404 ps
CPU time 0.69 seconds
Started Jul 15 06:42:30 PM PDT 24
Finished Jul 15 06:42:31 PM PDT 24
Peak memory 196252 kb
Host smart-2d3c245a-2175-4e39-8b94-07b12f8d1526
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620192915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2620192915
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2113955288
Short name T2
Test name
Test status
Simulation time 7801321898 ps
CPU time 79.3 seconds
Started Jul 15 07:00:17 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 198784 kb
Host smart-7c94fd7f-7b3b-46e1-9205-8da32ad7e2b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113955288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2113955288
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.473388189
Short name T51
Test name
Test status
Simulation time 159276090 ps
CPU time 1.24 seconds
Started Jul 15 06:43:18 PM PDT 24
Finished Jul 15 06:43:20 PM PDT 24
Peak memory 198752 kb
Host smart-c0a44769-0828-48b5-9ba0-47ed5a9ea059
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473388189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.473388189
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.899671807
Short name T31
Test name
Test status
Simulation time 15636463 ps
CPU time 0.58 seconds
Started Jul 15 07:00:09 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 195368 kb
Host smart-bcec0d96-1429-45d6-8a16-9f5dab16e226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899671807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.899671807
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3445120739
Short name T105
Test name
Test status
Simulation time 32535693 ps
CPU time 0.79 seconds
Started Jul 15 06:43:10 PM PDT 24
Finished Jul 15 06:43:11 PM PDT 24
Peak memory 196704 kb
Host smart-b799011b-4d05-4945-b38f-d3b122ab8e45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445120739 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3445120739
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1289420341
Short name T49
Test name
Test status
Simulation time 109604007 ps
CPU time 0.98 seconds
Started Jul 15 06:43:12 PM PDT 24
Finished Jul 15 06:43:13 PM PDT 24
Peak memory 197944 kb
Host smart-02b78c0e-9804-4dd4-bb32-fa5e8208d2c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289420341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1289420341
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1372507324
Short name T43
Test name
Test status
Simulation time 118019740 ps
CPU time 1.51 seconds
Started Jul 15 06:43:05 PM PDT 24
Finished Jul 15 06:43:07 PM PDT 24
Peak memory 198660 kb
Host smart-7be38ebe-1b13-4d34-a21d-8d0fac8b5acd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372507324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1372507324
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1601514319
Short name T56
Test name
Test status
Simulation time 46315920 ps
CPU time 0.92 seconds
Started Jul 15 06:41:49 PM PDT 24
Finished Jul 15 06:41:50 PM PDT 24
Peak memory 197940 kb
Host smart-4f7107d4-9f7a-4901-8592-31d9d1a73be8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601514319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1601514319
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2877038905
Short name T103
Test name
Test status
Simulation time 34789510 ps
CPU time 0.9 seconds
Started Jul 15 06:41:51 PM PDT 24
Finished Jul 15 06:41:52 PM PDT 24
Peak memory 196812 kb
Host smart-211c8d6e-1472-4233-949d-8e6b17a09f41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877038905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2877038905
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2044655005
Short name T772
Test name
Test status
Simulation time 278531495 ps
CPU time 3.34 seconds
Started Jul 15 06:42:04 PM PDT 24
Finished Jul 15 06:42:07 PM PDT 24
Peak memory 197888 kb
Host smart-adfee743-008d-4318-9f9f-169308a5ec41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044655005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2044655005
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2090988125
Short name T800
Test name
Test status
Simulation time 64292875 ps
CPU time 0.64 seconds
Started Jul 15 06:42:03 PM PDT 24
Finished Jul 15 06:42:04 PM PDT 24
Peak memory 195208 kb
Host smart-82e70045-959b-4ef3-8b73-ddcbf4356225
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090988125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2090988125
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.745317907
Short name T734
Test name
Test status
Simulation time 308845850 ps
CPU time 0.81 seconds
Started Jul 15 06:41:49 PM PDT 24
Finished Jul 15 06:41:50 PM PDT 24
Peak memory 198652 kb
Host smart-bbcfcd23-66ef-4c90-9084-12324b739493
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745317907 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.745317907
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.104199548
Short name T811
Test name
Test status
Simulation time 25158663 ps
CPU time 0.59 seconds
Started Jul 15 06:41:48 PM PDT 24
Finished Jul 15 06:41:49 PM PDT 24
Peak memory 195100 kb
Host smart-ef8dba1a-7e86-409a-a91c-78fe8e8eb9b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104199548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.104199548
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1355984747
Short name T818
Test name
Test status
Simulation time 46006749 ps
CPU time 0.6 seconds
Started Jul 15 06:41:55 PM PDT 24
Finished Jul 15 06:41:56 PM PDT 24
Peak memory 194940 kb
Host smart-03553310-f23c-4074-9be0-1795613bcf59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355984747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1355984747
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1722622766
Short name T109
Test name
Test status
Simulation time 36701391 ps
CPU time 0.83 seconds
Started Jul 15 06:41:51 PM PDT 24
Finished Jul 15 06:41:52 PM PDT 24
Peak memory 197568 kb
Host smart-c1d8658a-3187-42a2-8f2f-b8c62ce874f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722622766 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1722622766
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3240080374
Short name T754
Test name
Test status
Simulation time 383555609 ps
CPU time 1.91 seconds
Started Jul 15 06:41:55 PM PDT 24
Finished Jul 15 06:41:57 PM PDT 24
Peak memory 198712 kb
Host smart-306151a0-5706-4b7a-9f91-c3dffc187fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240080374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3240080374
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4041484226
Short name T91
Test name
Test status
Simulation time 242196217 ps
CPU time 0.76 seconds
Started Jul 15 06:42:00 PM PDT 24
Finished Jul 15 06:42:02 PM PDT 24
Peak memory 197244 kb
Host smart-c203b4e2-4bcd-4611-8c24-4ede483d08f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041484226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4041484226
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.732111157
Short name T825
Test name
Test status
Simulation time 121719578 ps
CPU time 1.56 seconds
Started Jul 15 06:42:22 PM PDT 24
Finished Jul 15 06:42:24 PM PDT 24
Peak memory 198712 kb
Host smart-69a7acb5-5468-491b-a469-3272da3fff46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732111157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.732111157
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1445912315
Short name T764
Test name
Test status
Simulation time 55571657 ps
CPU time 0.63 seconds
Started Jul 15 06:42:19 PM PDT 24
Finished Jul 15 06:42:20 PM PDT 24
Peak memory 195264 kb
Host smart-9d514c7b-881a-4de9-8a72-30004a0ebac5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445912315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1445912315
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1606289249
Short name T759
Test name
Test status
Simulation time 81747262 ps
CPU time 0.67 seconds
Started Jul 15 06:42:09 PM PDT 24
Finished Jul 15 06:42:10 PM PDT 24
Peak memory 197336 kb
Host smart-6a715343-6f65-4904-9c43-3fad82de4ce1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606289249 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1606289249
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1171434292
Short name T821
Test name
Test status
Simulation time 10759488 ps
CPU time 0.58 seconds
Started Jul 15 06:42:00 PM PDT 24
Finished Jul 15 06:42:01 PM PDT 24
Peak memory 194304 kb
Host smart-459e6dc8-233c-4158-b147-1f2fa31d9da0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171434292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1171434292
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.4139265950
Short name T814
Test name
Test status
Simulation time 40495205 ps
CPU time 0.58 seconds
Started Jul 15 06:42:15 PM PDT 24
Finished Jul 15 06:42:16 PM PDT 24
Peak memory 194980 kb
Host smart-33753a58-21fa-499c-b3c6-076a3b4a4066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139265950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4139265950
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1266364228
Short name T836
Test name
Test status
Simulation time 37466414 ps
CPU time 0.92 seconds
Started Jul 15 06:42:02 PM PDT 24
Finished Jul 15 06:42:03 PM PDT 24
Peak memory 197072 kb
Host smart-e92ffad3-64f3-4433-8829-b6aeca4251cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266364228 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1266364228
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2479991897
Short name T750
Test name
Test status
Simulation time 137112921 ps
CPU time 1.47 seconds
Started Jul 15 06:42:14 PM PDT 24
Finished Jul 15 06:42:15 PM PDT 24
Peak memory 198760 kb
Host smart-08620e29-dd18-4f0d-9d06-dc719925daf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479991897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2479991897
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.156751109
Short name T57
Test name
Test status
Simulation time 70265390 ps
CPU time 1.16 seconds
Started Jul 15 06:42:09 PM PDT 24
Finished Jul 15 06:42:10 PM PDT 24
Peak memory 198684 kb
Host smart-d9076923-a44d-4086-acb1-67f77352796b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156751109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.156751109
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2211238558
Short name T796
Test name
Test status
Simulation time 101068378 ps
CPU time 1.19 seconds
Started Jul 15 06:43:07 PM PDT 24
Finished Jul 15 06:43:08 PM PDT 24
Peak memory 198740 kb
Host smart-d299b74c-1652-4d0e-81f5-dc879dd457f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211238558 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2211238558
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3951554781
Short name T92
Test name
Test status
Simulation time 46569787 ps
CPU time 0.63 seconds
Started Jul 15 06:43:06 PM PDT 24
Finished Jul 15 06:43:07 PM PDT 24
Peak memory 195576 kb
Host smart-9de388b3-b6ab-4528-90f6-62c8a09ee2eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951554781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3951554781
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1555123724
Short name T817
Test name
Test status
Simulation time 26228240 ps
CPU time 0.6 seconds
Started Jul 15 06:43:10 PM PDT 24
Finished Jul 15 06:43:11 PM PDT 24
Peak memory 194384 kb
Host smart-a3364e5f-ad7b-4580-a93f-0f201e1053bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555123724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1555123724
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1853603237
Short name T790
Test name
Test status
Simulation time 16469057 ps
CPU time 0.75 seconds
Started Jul 15 06:43:04 PM PDT 24
Finished Jul 15 06:43:05 PM PDT 24
Peak memory 196732 kb
Host smart-6dce030b-bd10-4e5d-a418-e9215e8d8764
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853603237 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1853603237
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1753894799
Short name T797
Test name
Test status
Simulation time 59370580 ps
CPU time 3.23 seconds
Started Jul 15 06:43:09 PM PDT 24
Finished Jul 15 06:43:13 PM PDT 24
Peak memory 198668 kb
Host smart-fb466aef-2299-4a42-8f64-7268421d092e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753894799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1753894799
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.64961571
Short name T757
Test name
Test status
Simulation time 53055923 ps
CPU time 0.63 seconds
Started Jul 15 06:43:09 PM PDT 24
Finished Jul 15 06:43:10 PM PDT 24
Peak memory 197104 kb
Host smart-f2708532-c1d8-4f78-9983-68accee66c0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64961571 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.64961571
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3351792943
Short name T780
Test name
Test status
Simulation time 28084461 ps
CPU time 0.62 seconds
Started Jul 15 06:43:10 PM PDT 24
Finished Jul 15 06:43:11 PM PDT 24
Peak memory 196212 kb
Host smart-5c234245-824b-49e0-88c6-32604ea05a91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351792943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3351792943
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.651411974
Short name T838
Test name
Test status
Simulation time 16526735 ps
CPU time 0.6 seconds
Started Jul 15 06:43:10 PM PDT 24
Finished Jul 15 06:43:11 PM PDT 24
Peak memory 194416 kb
Host smart-45fdcb9e-ceea-4723-b4d6-bce35c4785bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651411974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.651411974
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1643011695
Short name T830
Test name
Test status
Simulation time 886898373 ps
CPU time 1.71 seconds
Started Jul 15 06:43:11 PM PDT 24
Finished Jul 15 06:43:13 PM PDT 24
Peak memory 198748 kb
Host smart-ee70da6c-5b6d-4df4-8251-9a9025b437f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643011695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1643011695
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1491920846
Short name T839
Test name
Test status
Simulation time 2015916396 ps
CPU time 1.45 seconds
Started Jul 15 06:43:11 PM PDT 24
Finished Jul 15 06:43:13 PM PDT 24
Peak memory 198564 kb
Host smart-d57db39a-8bb1-452d-bc9a-19e319621ab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491920846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1491920846
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1408322996
Short name T732
Test name
Test status
Simulation time 284363642 ps
CPU time 0.94 seconds
Started Jul 15 06:43:09 PM PDT 24
Finished Jul 15 06:43:10 PM PDT 24
Peak memory 198540 kb
Host smart-001ac5ce-47fe-4323-8ee6-62e1857f090c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408322996 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1408322996
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2485620098
Short name T776
Test name
Test status
Simulation time 24626573 ps
CPU time 0.66 seconds
Started Jul 15 06:43:10 PM PDT 24
Finished Jul 15 06:43:11 PM PDT 24
Peak memory 195244 kb
Host smart-7da8fa93-80f2-4afd-91f7-b5ce13256285
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485620098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2485620098
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.129693459
Short name T755
Test name
Test status
Simulation time 15056660 ps
CPU time 0.59 seconds
Started Jul 15 06:43:19 PM PDT 24
Finished Jul 15 06:43:20 PM PDT 24
Peak memory 194352 kb
Host smart-03c275b7-1935-47be-a0f9-df53f1ad9ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129693459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.129693459
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2866231297
Short name T806
Test name
Test status
Simulation time 18631402 ps
CPU time 0.9 seconds
Started Jul 15 06:43:09 PM PDT 24
Finished Jul 15 06:43:11 PM PDT 24
Peak memory 198020 kb
Host smart-b84d4498-ddfa-470d-8612-4ef5cd39f8d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866231297 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2866231297
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2361830807
Short name T761
Test name
Test status
Simulation time 198705667 ps
CPU time 2.16 seconds
Started Jul 15 06:43:18 PM PDT 24
Finished Jul 15 06:43:21 PM PDT 24
Peak memory 198708 kb
Host smart-78a63c06-4ffd-4f44-a596-92dd0ba2d970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361830807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2361830807
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1494650858
Short name T753
Test name
Test status
Simulation time 104421288 ps
CPU time 0.63 seconds
Started Jul 15 06:43:18 PM PDT 24
Finished Jul 15 06:43:19 PM PDT 24
Peak memory 197108 kb
Host smart-e718d456-7d52-4a90-bbf9-9d953365bb72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494650858 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1494650858
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1383063816
Short name T745
Test name
Test status
Simulation time 11540230 ps
CPU time 0.58 seconds
Started Jul 15 06:43:20 PM PDT 24
Finished Jul 15 06:43:21 PM PDT 24
Peak memory 194028 kb
Host smart-a2b2ec73-4410-4a8a-815b-27c78e5c2a9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383063816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1383063816
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.4217306039
Short name T721
Test name
Test status
Simulation time 29344537 ps
CPU time 0.61 seconds
Started Jul 15 06:43:20 PM PDT 24
Finished Jul 15 06:43:21 PM PDT 24
Peak memory 194404 kb
Host smart-35fb6f2c-fc50-4108-a5b4-4fe1b7fe1eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217306039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.4217306039
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3187201234
Short name T762
Test name
Test status
Simulation time 17456655 ps
CPU time 0.7 seconds
Started Jul 15 06:43:19 PM PDT 24
Finished Jul 15 06:43:20 PM PDT 24
Peak memory 195456 kb
Host smart-613592e8-bcb4-4317-9c51-938a53a62b8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187201234 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3187201234
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3268168705
Short name T813
Test name
Test status
Simulation time 276748778 ps
CPU time 1.38 seconds
Started Jul 15 06:43:15 PM PDT 24
Finished Jul 15 06:43:17 PM PDT 24
Peak memory 198720 kb
Host smart-3aadc18b-73b3-4de4-84b8-32c51ca57fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268168705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3268168705
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1811006544
Short name T744
Test name
Test status
Simulation time 36299802 ps
CPU time 1.02 seconds
Started Jul 15 06:43:20 PM PDT 24
Finished Jul 15 06:43:21 PM PDT 24
Peak memory 198612 kb
Host smart-bc278dcc-44f8-48bc-8b03-dc7f105df363
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811006544 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1811006544
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1418817998
Short name T102
Test name
Test status
Simulation time 14352866 ps
CPU time 0.61 seconds
Started Jul 15 06:43:22 PM PDT 24
Finished Jul 15 06:43:23 PM PDT 24
Peak memory 195380 kb
Host smart-7de3d777-16d5-412e-84bd-be03483ed95c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418817998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1418817998
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2687874638
Short name T782
Test name
Test status
Simulation time 16022245 ps
CPU time 0.59 seconds
Started Jul 15 06:43:24 PM PDT 24
Finished Jul 15 06:43:25 PM PDT 24
Peak memory 194348 kb
Host smart-778eb093-a3ee-4891-becc-affd7d7bf9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687874638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2687874638
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.50895023
Short name T89
Test name
Test status
Simulation time 123254190 ps
CPU time 0.66 seconds
Started Jul 15 06:43:21 PM PDT 24
Finished Jul 15 06:43:22 PM PDT 24
Peak memory 196196 kb
Host smart-79b7070d-d7df-4f7c-bed8-4041732a0a6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50895023 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.gpio_same_csr_outstanding.50895023
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1981478891
Short name T795
Test name
Test status
Simulation time 457425778 ps
CPU time 2.52 seconds
Started Jul 15 06:43:21 PM PDT 24
Finished Jul 15 06:43:24 PM PDT 24
Peak memory 198752 kb
Host smart-4db363b5-334a-441f-9c3e-e2f4412576f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981478891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1981478891
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2427019962
Short name T50
Test name
Test status
Simulation time 141513223 ps
CPU time 0.86 seconds
Started Jul 15 06:43:19 PM PDT 24
Finished Jul 15 06:43:21 PM PDT 24
Peak memory 197564 kb
Host smart-51662563-d83b-4c31-a413-72a7612ca5bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427019962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2427019962
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1895986747
Short name T749
Test name
Test status
Simulation time 25036440 ps
CPU time 0.78 seconds
Started Jul 15 06:43:29 PM PDT 24
Finished Jul 15 06:43:30 PM PDT 24
Peak memory 198656 kb
Host smart-cd73b0aa-5e91-48c9-a0af-3c91deb6b494
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895986747 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1895986747
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.145912478
Short name T779
Test name
Test status
Simulation time 42460800 ps
CPU time 0.65 seconds
Started Jul 15 06:43:21 PM PDT 24
Finished Jul 15 06:43:22 PM PDT 24
Peak memory 195436 kb
Host smart-25bffb12-886a-410d-9612-3c810b7556e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145912478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.145912478
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2076638877
Short name T730
Test name
Test status
Simulation time 23805107 ps
CPU time 0.6 seconds
Started Jul 15 06:43:28 PM PDT 24
Finished Jul 15 06:43:29 PM PDT 24
Peak memory 194492 kb
Host smart-f8762f02-28c6-4ee3-95cf-446e2aa1f002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076638877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2076638877
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4026727916
Short name T805
Test name
Test status
Simulation time 52444024 ps
CPU time 0.65 seconds
Started Jul 15 06:43:22 PM PDT 24
Finished Jul 15 06:43:23 PM PDT 24
Peak memory 195552 kb
Host smart-703de8d8-a4ed-414f-aed8-9eb3287398f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026727916 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.4026727916
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2652538521
Short name T842
Test name
Test status
Simulation time 31052180 ps
CPU time 1.8 seconds
Started Jul 15 06:43:30 PM PDT 24
Finished Jul 15 06:43:32 PM PDT 24
Peak memory 198740 kb
Host smart-da0c1dd9-6da1-4750-9541-c547a5dcec94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652538521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2652538521
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2530991361
Short name T116
Test name
Test status
Simulation time 221503806 ps
CPU time 1.14 seconds
Started Jul 15 06:43:29 PM PDT 24
Finished Jul 15 06:43:31 PM PDT 24
Peak memory 198692 kb
Host smart-6a01ad88-7bda-45fd-89e8-dd126e424587
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530991361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2530991361
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2267159450
Short name T824
Test name
Test status
Simulation time 166975569 ps
CPU time 1.05 seconds
Started Jul 15 06:43:29 PM PDT 24
Finished Jul 15 06:43:30 PM PDT 24
Peak memory 198596 kb
Host smart-8f881cc1-3ec2-4fc5-bdba-2469cb607e0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267159450 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2267159450
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.90312365
Short name T100
Test name
Test status
Simulation time 18042546 ps
CPU time 0.6 seconds
Started Jul 15 06:43:31 PM PDT 24
Finished Jul 15 06:43:32 PM PDT 24
Peak memory 195356 kb
Host smart-60655849-7a14-445d-a192-4a84158e5844
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90312365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_
csr_rw.90312365
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.109791520
Short name T787
Test name
Test status
Simulation time 14102644 ps
CPU time 0.61 seconds
Started Jul 15 06:43:33 PM PDT 24
Finished Jul 15 06:43:34 PM PDT 24
Peak memory 195048 kb
Host smart-f5275c5d-2016-4f3e-85d9-d29c8add99e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109791520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.109791520
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2586921544
Short name T799
Test name
Test status
Simulation time 16958631 ps
CPU time 0.75 seconds
Started Jul 15 06:43:26 PM PDT 24
Finished Jul 15 06:43:27 PM PDT 24
Peak memory 197500 kb
Host smart-4b70fa5c-2af9-4f71-9661-653fff13fe13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586921544 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2586921544
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1011696462
Short name T760
Test name
Test status
Simulation time 187121342 ps
CPU time 2.33 seconds
Started Jul 15 06:43:33 PM PDT 24
Finished Jul 15 06:43:36 PM PDT 24
Peak memory 198744 kb
Host smart-cbc82c86-9752-4067-9fb2-f8c512a540e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011696462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1011696462
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3695979445
Short name T52
Test name
Test status
Simulation time 41612352 ps
CPU time 0.87 seconds
Started Jul 15 06:43:27 PM PDT 24
Finished Jul 15 06:43:29 PM PDT 24
Peak memory 197952 kb
Host smart-d7da6521-0b64-4e75-90b6-167845dc3c63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695979445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3695979445
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2999146189
Short name T801
Test name
Test status
Simulation time 37745725 ps
CPU time 0.99 seconds
Started Jul 15 06:43:32 PM PDT 24
Finished Jul 15 06:43:33 PM PDT 24
Peak memory 198668 kb
Host smart-0b659048-cef3-4db2-8a5d-751f648b4acd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999146189 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2999146189
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.962138420
Short name T815
Test name
Test status
Simulation time 44157842 ps
CPU time 0.57 seconds
Started Jul 15 06:43:35 PM PDT 24
Finished Jul 15 06:43:35 PM PDT 24
Peak memory 194040 kb
Host smart-2a02dbce-0d7b-4179-a329-08b57d352dbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962138420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.962138420
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.461270326
Short name T804
Test name
Test status
Simulation time 17993630 ps
CPU time 0.57 seconds
Started Jul 15 06:43:32 PM PDT 24
Finished Jul 15 06:43:32 PM PDT 24
Peak memory 194308 kb
Host smart-15abc40f-93a8-4dea-9b71-aa37d93a70f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461270326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.461270326
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3526062545
Short name T107
Test name
Test status
Simulation time 29980132 ps
CPU time 0.85 seconds
Started Jul 15 06:43:35 PM PDT 24
Finished Jul 15 06:43:36 PM PDT 24
Peak memory 197852 kb
Host smart-a3ab2a8d-9ff7-4e94-97d5-86bc91650f19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526062545 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3526062545
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1176563542
Short name T739
Test name
Test status
Simulation time 49053021 ps
CPU time 2.54 seconds
Started Jul 15 06:43:35 PM PDT 24
Finished Jul 15 06:43:38 PM PDT 24
Peak memory 198756 kb
Host smart-7c671af3-636f-4d41-a2b3-8ba6e136534d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176563542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1176563542
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.596539618
Short name T53
Test name
Test status
Simulation time 48457374 ps
CPU time 0.92 seconds
Started Jul 15 06:43:32 PM PDT 24
Finished Jul 15 06:43:34 PM PDT 24
Peak memory 198540 kb
Host smart-308fd3de-cbac-40d5-b8cb-bf19dc71b3ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596539618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.596539618
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.712604466
Short name T727
Test name
Test status
Simulation time 19984194 ps
CPU time 0.81 seconds
Started Jul 15 06:43:35 PM PDT 24
Finished Jul 15 06:43:36 PM PDT 24
Peak memory 198544 kb
Host smart-075f6ca8-9474-4151-abf9-605a4efcc492
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712604466 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.712604466
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1186637173
Short name T98
Test name
Test status
Simulation time 29069435 ps
CPU time 0.64 seconds
Started Jul 15 06:43:33 PM PDT 24
Finished Jul 15 06:43:34 PM PDT 24
Peak memory 195376 kb
Host smart-36792fa3-5046-4a7a-8052-a16cdca92981
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186637173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1186637173
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1171153926
Short name T763
Test name
Test status
Simulation time 15280035 ps
CPU time 0.64 seconds
Started Jul 15 06:43:52 PM PDT 24
Finished Jul 15 06:43:53 PM PDT 24
Peak memory 194324 kb
Host smart-a3b681ca-c044-4e67-a291-dbd04c8e83e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171153926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1171153926
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3618418649
Short name T106
Test name
Test status
Simulation time 91666377 ps
CPU time 0.76 seconds
Started Jul 15 06:43:33 PM PDT 24
Finished Jul 15 06:43:34 PM PDT 24
Peak memory 196956 kb
Host smart-82d53ac1-d44a-4e81-ac7b-03e33b79ed68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618418649 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3618418649
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1156380622
Short name T722
Test name
Test status
Simulation time 163040844 ps
CPU time 1.26 seconds
Started Jul 15 06:43:34 PM PDT 24
Finished Jul 15 06:43:35 PM PDT 24
Peak memory 198740 kb
Host smart-68793599-bc20-44bd-b4ba-2077f4d271c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156380622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1156380622
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.194719028
Short name T44
Test name
Test status
Simulation time 63544734 ps
CPU time 0.92 seconds
Started Jul 15 06:43:30 PM PDT 24
Finished Jul 15 06:43:32 PM PDT 24
Peak memory 198504 kb
Host smart-8ffd1eef-e8b4-4e1f-abde-482b278ccc1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194719028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.194719028
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1266949124
Short name T827
Test name
Test status
Simulation time 36756649 ps
CPU time 0.8 seconds
Started Jul 15 06:43:41 PM PDT 24
Finished Jul 15 06:43:42 PM PDT 24
Peak memory 198668 kb
Host smart-889aeb94-c348-42b2-809c-7ea9cdd88dc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266949124 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1266949124
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1698640739
Short name T784
Test name
Test status
Simulation time 33693562 ps
CPU time 0.56 seconds
Started Jul 15 06:43:51 PM PDT 24
Finished Jul 15 06:43:52 PM PDT 24
Peak memory 193976 kb
Host smart-48cb419b-a7a0-4ced-85ff-55b4fa78578e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698640739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1698640739
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2922353819
Short name T802
Test name
Test status
Simulation time 11639567 ps
CPU time 0.62 seconds
Started Jul 15 06:43:38 PM PDT 24
Finished Jul 15 06:43:39 PM PDT 24
Peak memory 194344 kb
Host smart-8825aa6d-d39f-47ae-aa83-451f714d75bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922353819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2922353819
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1627175979
Short name T803
Test name
Test status
Simulation time 25740992 ps
CPU time 0.66 seconds
Started Jul 15 06:43:40 PM PDT 24
Finished Jul 15 06:43:41 PM PDT 24
Peak memory 195076 kb
Host smart-03853b8b-3aa1-4e23-9396-a023709d62cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627175979 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1627175979
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1988671550
Short name T837
Test name
Test status
Simulation time 634115949 ps
CPU time 2.74 seconds
Started Jul 15 06:43:52 PM PDT 24
Finished Jul 15 06:43:56 PM PDT 24
Peak memory 198716 kb
Host smart-db0f8875-f6d8-4310-b50e-f9d2e7920c76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988671550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1988671550
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1276321939
Short name T816
Test name
Test status
Simulation time 52984054 ps
CPU time 0.85 seconds
Started Jul 15 06:43:39 PM PDT 24
Finished Jul 15 06:43:40 PM PDT 24
Peak memory 198456 kb
Host smart-cfb87eef-34fb-4302-8b7e-1bcf48f522c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276321939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1276321939
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.123604785
Short name T832
Test name
Test status
Simulation time 277683661 ps
CPU time 0.84 seconds
Started Jul 15 06:42:25 PM PDT 24
Finished Jul 15 06:42:26 PM PDT 24
Peak memory 196796 kb
Host smart-c823db18-bc07-4066-8d1f-e7e6e188dc61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123604785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.123604785
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.358224792
Short name T90
Test name
Test status
Simulation time 734131289 ps
CPU time 2.42 seconds
Started Jul 15 06:42:24 PM PDT 24
Finished Jul 15 06:42:27 PM PDT 24
Peak memory 197784 kb
Host smart-c1b33b26-e9b2-4a71-b847-d3e1c37fb0b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358224792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.358224792
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2128706
Short name T771
Test name
Test status
Simulation time 178249746 ps
CPU time 1.2 seconds
Started Jul 15 06:42:25 PM PDT 24
Finished Jul 15 06:42:27 PM PDT 24
Peak memory 198736 kb
Host smart-99a1f723-ebed-488b-aa3c-86f592bcd0ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128706 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2128706
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1157905920
Short name T87
Test name
Test status
Simulation time 12622830 ps
CPU time 0.59 seconds
Started Jul 15 06:42:20 PM PDT 24
Finished Jul 15 06:42:21 PM PDT 24
Peak memory 196176 kb
Host smart-7f478059-6837-4e76-b65e-ccbaa361b96f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157905920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1157905920
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.634406985
Short name T735
Test name
Test status
Simulation time 153424183 ps
CPU time 0.59 seconds
Started Jul 15 06:42:26 PM PDT 24
Finished Jul 15 06:42:27 PM PDT 24
Peak memory 195060 kb
Host smart-1975d2e8-4949-417e-b598-06c9edf87190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634406985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.634406985
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.302361829
Short name T768
Test name
Test status
Simulation time 20978813 ps
CPU time 0.7 seconds
Started Jul 15 06:42:19 PM PDT 24
Finished Jul 15 06:42:20 PM PDT 24
Peak memory 196156 kb
Host smart-965f5757-b982-4bc0-b863-3da627a42d85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302361829 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.302361829
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3432926137
Short name T733
Test name
Test status
Simulation time 198615030 ps
CPU time 3.38 seconds
Started Jul 15 06:42:26 PM PDT 24
Finished Jul 15 06:42:30 PM PDT 24
Peak memory 198672 kb
Host smart-42173309-1a00-4479-9802-ecf3f0ca8c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432926137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3432926137
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1507609789
Short name T794
Test name
Test status
Simulation time 89766143 ps
CPU time 0.9 seconds
Started Jul 15 06:42:25 PM PDT 24
Finished Jul 15 06:42:26 PM PDT 24
Peak memory 197892 kb
Host smart-2c08e1e5-12b9-40a9-91a7-2852adfff7c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507609789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1507609789
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2724552861
Short name T748
Test name
Test status
Simulation time 20747339 ps
CPU time 0.61 seconds
Started Jul 15 06:43:41 PM PDT 24
Finished Jul 15 06:43:42 PM PDT 24
Peak memory 195080 kb
Host smart-f02cc9ac-c19b-4758-878b-369b5d6e399c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724552861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2724552861
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3925705398
Short name T758
Test name
Test status
Simulation time 14207168 ps
CPU time 0.61 seconds
Started Jul 15 06:43:40 PM PDT 24
Finished Jul 15 06:43:41 PM PDT 24
Peak memory 195012 kb
Host smart-1f4002b9-495b-4127-b3b3-f54bd05a2a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925705398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3925705398
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1992628087
Short name T822
Test name
Test status
Simulation time 46275674 ps
CPU time 0.61 seconds
Started Jul 15 06:43:52 PM PDT 24
Finished Jul 15 06:43:53 PM PDT 24
Peak memory 194472 kb
Host smart-50ca19a1-0b98-4dba-9c17-b1b99f611040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992628087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1992628087
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3783572517
Short name T807
Test name
Test status
Simulation time 11120623 ps
CPU time 0.66 seconds
Started Jul 15 06:43:52 PM PDT 24
Finished Jul 15 06:43:54 PM PDT 24
Peak memory 194392 kb
Host smart-018ac1c4-6216-4b6a-87ce-b5f635cba6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783572517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3783572517
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2646586645
Short name T834
Test name
Test status
Simulation time 20411570 ps
CPU time 0.59 seconds
Started Jul 15 06:43:40 PM PDT 24
Finished Jul 15 06:43:41 PM PDT 24
Peak memory 194356 kb
Host smart-76c1f993-ecb4-4352-90bd-fd80e736b852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646586645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2646586645
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.4191513163
Short name T767
Test name
Test status
Simulation time 20268710 ps
CPU time 0.6 seconds
Started Jul 15 06:43:40 PM PDT 24
Finished Jul 15 06:43:41 PM PDT 24
Peak memory 194944 kb
Host smart-72a228f3-c51f-4f49-8280-e50f60c105d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191513163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.4191513163
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2834788069
Short name T774
Test name
Test status
Simulation time 48127869 ps
CPU time 0.6 seconds
Started Jul 15 06:43:52 PM PDT 24
Finished Jul 15 06:43:54 PM PDT 24
Peak memory 194396 kb
Host smart-d011f141-a4b8-4ba9-8de9-22d992a12f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834788069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2834788069
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2327086761
Short name T792
Test name
Test status
Simulation time 11009209 ps
CPU time 0.59 seconds
Started Jul 15 06:43:47 PM PDT 24
Finished Jul 15 06:43:48 PM PDT 24
Peak memory 194364 kb
Host smart-df726de5-0ad5-48f6-a94d-6c589ee1d604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327086761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2327086761
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2598355402
Short name T751
Test name
Test status
Simulation time 12477391 ps
CPU time 0.66 seconds
Started Jul 15 06:43:45 PM PDT 24
Finished Jul 15 06:43:47 PM PDT 24
Peak memory 195132 kb
Host smart-bc835073-612c-48ac-b6e8-83e0578dc32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598355402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2598355402
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4236365411
Short name T828
Test name
Test status
Simulation time 12200105 ps
CPU time 0.59 seconds
Started Jul 15 06:43:59 PM PDT 24
Finished Jul 15 06:44:00 PM PDT 24
Peak memory 194324 kb
Host smart-59034c93-c945-4447-a669-13923f7fc44d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236365411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4236365411
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1130173664
Short name T96
Test name
Test status
Simulation time 90693196 ps
CPU time 0.75 seconds
Started Jul 15 06:42:27 PM PDT 24
Finished Jul 15 06:42:28 PM PDT 24
Peak memory 197048 kb
Host smart-9b9df68e-99ed-4f30-8f55-56968dafac28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130173664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1130173664
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2773976925
Short name T114
Test name
Test status
Simulation time 129245727 ps
CPU time 1.41 seconds
Started Jul 15 06:42:31 PM PDT 24
Finished Jul 15 06:42:33 PM PDT 24
Peak memory 197868 kb
Host smart-2c2851eb-3076-4cc2-9c9e-611565e2b7e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773976925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2773976925
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1642210313
Short name T94
Test name
Test status
Simulation time 15756103 ps
CPU time 0.61 seconds
Started Jul 15 06:42:32 PM PDT 24
Finished Jul 15 06:42:33 PM PDT 24
Peak memory 195628 kb
Host smart-8150e3a0-41bd-40d1-993f-120e0ffcb216
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642210313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1642210313
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1570545547
Short name T783
Test name
Test status
Simulation time 73004833 ps
CPU time 0.77 seconds
Started Jul 15 06:42:32 PM PDT 24
Finished Jul 15 06:42:33 PM PDT 24
Peak memory 198604 kb
Host smart-124d3b41-c3c9-4503-9361-e885d2bebaee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570545547 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1570545547
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.809973216
Short name T840
Test name
Test status
Simulation time 17071434 ps
CPU time 0.59 seconds
Started Jul 15 06:42:27 PM PDT 24
Finished Jul 15 06:42:28 PM PDT 24
Peak memory 194660 kb
Host smart-6cd2226c-2d90-41c0-982c-527f321378c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809973216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.809973216
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4008286037
Short name T765
Test name
Test status
Simulation time 23635995 ps
CPU time 0.56 seconds
Started Jul 15 06:42:32 PM PDT 24
Finished Jul 15 06:42:33 PM PDT 24
Peak memory 194960 kb
Host smart-65816c40-a875-4bbe-83e5-cfad9db5583a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008286037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4008286037
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2539050185
Short name T108
Test name
Test status
Simulation time 167961241 ps
CPU time 0.86 seconds
Started Jul 15 06:42:26 PM PDT 24
Finished Jul 15 06:42:28 PM PDT 24
Peak memory 197688 kb
Host smart-e2f0f939-0a83-4d5b-8f22-b6946dd95afa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539050185 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2539050185
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.769778038
Short name T785
Test name
Test status
Simulation time 262792266 ps
CPU time 1.46 seconds
Started Jul 15 06:42:31 PM PDT 24
Finished Jul 15 06:42:32 PM PDT 24
Peak memory 198748 kb
Host smart-89542918-33cd-4bcb-84cb-1994715e0d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769778038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.769778038
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3966084127
Short name T843
Test name
Test status
Simulation time 120986502 ps
CPU time 1.1 seconds
Started Jul 15 06:42:32 PM PDT 24
Finished Jul 15 06:42:34 PM PDT 24
Peak memory 198688 kb
Host smart-80cb1bed-f871-4439-9a7d-c94aa4f4d653
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966084127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3966084127
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4107715487
Short name T786
Test name
Test status
Simulation time 13302940 ps
CPU time 0.56 seconds
Started Jul 15 06:43:43 PM PDT 24
Finished Jul 15 06:43:44 PM PDT 24
Peak memory 194336 kb
Host smart-849b9d6d-1e40-49a2-90fe-ee1e26cda876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107715487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4107715487
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.888796117
Short name T737
Test name
Test status
Simulation time 35342712 ps
CPU time 0.57 seconds
Started Jul 15 06:43:45 PM PDT 24
Finished Jul 15 06:43:46 PM PDT 24
Peak memory 194992 kb
Host smart-8bf250ed-145b-40af-98cb-378b4ae0b128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888796117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.888796117
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3996549264
Short name T773
Test name
Test status
Simulation time 19771983 ps
CPU time 0.63 seconds
Started Jul 15 06:43:59 PM PDT 24
Finished Jul 15 06:44:00 PM PDT 24
Peak memory 194984 kb
Host smart-38cd0fd6-f153-41fd-908c-9c29a20dd972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996549264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3996549264
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.971639351
Short name T826
Test name
Test status
Simulation time 10202250 ps
CPU time 0.56 seconds
Started Jul 15 06:43:47 PM PDT 24
Finished Jul 15 06:43:48 PM PDT 24
Peak memory 194380 kb
Host smart-e17c2ed8-a1d6-40e3-b5ea-80eb3a9ab0fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971639351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.971639351
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2198599859
Short name T746
Test name
Test status
Simulation time 11147253 ps
CPU time 0.58 seconds
Started Jul 15 06:43:59 PM PDT 24
Finished Jul 15 06:44:00 PM PDT 24
Peak memory 194360 kb
Host smart-ad2aec22-a0a9-434f-90a7-22665a990415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198599859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2198599859
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.700377510
Short name T808
Test name
Test status
Simulation time 18250299 ps
CPU time 0.6 seconds
Started Jul 15 06:43:43 PM PDT 24
Finished Jul 15 06:43:44 PM PDT 24
Peak memory 195016 kb
Host smart-e6212eda-76e6-4604-ab29-7c90ecce2c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700377510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.700377510
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.40790301
Short name T791
Test name
Test status
Simulation time 24128537 ps
CPU time 0.63 seconds
Started Jul 15 06:43:53 PM PDT 24
Finished Jul 15 06:43:54 PM PDT 24
Peak memory 194348 kb
Host smart-bbcf5209-d5fa-49ae-98ae-ff069701586a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40790301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.40790301
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1381667125
Short name T738
Test name
Test status
Simulation time 30111656 ps
CPU time 0.62 seconds
Started Jul 15 06:43:44 PM PDT 24
Finished Jul 15 06:43:45 PM PDT 24
Peak memory 195124 kb
Host smart-2e14e2f2-0e4f-4550-9a4a-a37c118e8790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381667125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1381667125
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3018999395
Short name T752
Test name
Test status
Simulation time 27490872 ps
CPU time 0.57 seconds
Started Jul 15 06:43:46 PM PDT 24
Finished Jul 15 06:43:47 PM PDT 24
Peak memory 194300 kb
Host smart-acf71be5-cb4a-466a-bf67-ad5f88774cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018999395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3018999395
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1989985921
Short name T823
Test name
Test status
Simulation time 13246032 ps
CPU time 0.58 seconds
Started Jul 15 06:43:45 PM PDT 24
Finished Jul 15 06:43:46 PM PDT 24
Peak memory 194312 kb
Host smart-2910e67b-d99f-44e5-8f72-0e586ceeb4e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989985921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1989985921
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2230243250
Short name T97
Test name
Test status
Simulation time 157852172 ps
CPU time 0.84 seconds
Started Jul 15 06:42:37 PM PDT 24
Finished Jul 15 06:42:38 PM PDT 24
Peak memory 196600 kb
Host smart-88b956e0-6b7e-495b-ab02-ab0f45250dec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230243250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2230243250
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1612183930
Short name T93
Test name
Test status
Simulation time 962656458 ps
CPU time 2.49 seconds
Started Jul 15 06:42:36 PM PDT 24
Finished Jul 15 06:42:39 PM PDT 24
Peak memory 197276 kb
Host smart-b72806b3-ffbe-4fbe-99fd-5cf789f4cc96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612183930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1612183930
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3438536461
Short name T740
Test name
Test status
Simulation time 20082555 ps
CPU time 0.73 seconds
Started Jul 15 06:42:36 PM PDT 24
Finished Jul 15 06:42:37 PM PDT 24
Peak memory 195384 kb
Host smart-816e888c-86e8-45b7-a085-9cf4abb84461
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438536461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3438536461
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4103677577
Short name T741
Test name
Test status
Simulation time 93044660 ps
CPU time 0.82 seconds
Started Jul 15 06:42:41 PM PDT 24
Finished Jul 15 06:42:42 PM PDT 24
Peak memory 198644 kb
Host smart-b16c361a-c82d-4782-bb22-9a52b41bed1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103677577 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4103677577
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2376592768
Short name T101
Test name
Test status
Simulation time 14333087 ps
CPU time 0.59 seconds
Started Jul 15 06:42:34 PM PDT 24
Finished Jul 15 06:42:35 PM PDT 24
Peak memory 193984 kb
Host smart-a05285fc-987f-496d-a430-2f0473b75f2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376592768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2376592768
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4172905597
Short name T775
Test name
Test status
Simulation time 80680435 ps
CPU time 0.63 seconds
Started Jul 15 06:42:41 PM PDT 24
Finished Jul 15 06:42:42 PM PDT 24
Peak memory 195044 kb
Host smart-8d18892f-7374-4468-832d-c84738b271ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172905597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4172905597
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2188463250
Short name T104
Test name
Test status
Simulation time 16968104 ps
CPU time 0.74 seconds
Started Jul 15 06:42:37 PM PDT 24
Finished Jul 15 06:42:39 PM PDT 24
Peak memory 196992 kb
Host smart-9d2bc515-8121-4e68-8cd0-59ba3a39644a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188463250 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2188463250
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.230404741
Short name T798
Test name
Test status
Simulation time 555248950 ps
CPU time 2.61 seconds
Started Jul 15 06:42:38 PM PDT 24
Finished Jul 15 06:42:41 PM PDT 24
Peak memory 198708 kb
Host smart-ef00a5d5-5c6b-4dfd-a4aa-15b62bd44ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230404741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.230404741
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3684697870
Short name T829
Test name
Test status
Simulation time 66913806 ps
CPU time 0.83 seconds
Started Jul 15 06:42:37 PM PDT 24
Finished Jul 15 06:42:38 PM PDT 24
Peak memory 197712 kb
Host smart-b15cba4a-ca2d-439e-a63e-1b78aa86a3af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684697870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3684697870
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.157866426
Short name T769
Test name
Test status
Simulation time 22292546 ps
CPU time 0.58 seconds
Started Jul 15 06:43:44 PM PDT 24
Finished Jul 15 06:43:45 PM PDT 24
Peak memory 195016 kb
Host smart-50c2abeb-8c3a-4476-897a-723f3a4b4cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157866426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.157866426
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3418962778
Short name T809
Test name
Test status
Simulation time 14911006 ps
CPU time 0.62 seconds
Started Jul 15 06:43:45 PM PDT 24
Finished Jul 15 06:43:46 PM PDT 24
Peak memory 194408 kb
Host smart-7ba897ca-4c5c-4f53-83d9-cc37c427b539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418962778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3418962778
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1943946913
Short name T729
Test name
Test status
Simulation time 48056317 ps
CPU time 0.57 seconds
Started Jul 15 06:43:47 PM PDT 24
Finished Jul 15 06:43:48 PM PDT 24
Peak memory 194344 kb
Host smart-297ff160-f5fc-4d0f-98b5-2884424cff50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943946913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1943946913
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1532888513
Short name T833
Test name
Test status
Simulation time 15996075 ps
CPU time 0.63 seconds
Started Jul 15 06:43:45 PM PDT 24
Finished Jul 15 06:43:46 PM PDT 24
Peak memory 194976 kb
Host smart-7a8ec9a2-b964-4ab4-8132-e0cf5446ffad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532888513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1532888513
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2673503968
Short name T766
Test name
Test status
Simulation time 15705440 ps
CPU time 0.58 seconds
Started Jul 15 06:43:51 PM PDT 24
Finished Jul 15 06:43:53 PM PDT 24
Peak memory 194300 kb
Host smart-7c384b15-8496-453d-889d-3943c702ecb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673503968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2673503968
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2584443646
Short name T788
Test name
Test status
Simulation time 42608645 ps
CPU time 0.6 seconds
Started Jul 15 06:43:51 PM PDT 24
Finished Jul 15 06:43:52 PM PDT 24
Peak memory 195012 kb
Host smart-b4dc02da-5446-4a8c-b104-80e5ebe15d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584443646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2584443646
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.108795497
Short name T756
Test name
Test status
Simulation time 20536734 ps
CPU time 0.61 seconds
Started Jul 15 06:43:49 PM PDT 24
Finished Jul 15 06:43:50 PM PDT 24
Peak memory 194328 kb
Host smart-6af8ce4d-c3d2-49ed-8931-559db85b3421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108795497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.108795497
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1222339632
Short name T743
Test name
Test status
Simulation time 44333511 ps
CPU time 0.56 seconds
Started Jul 15 06:43:50 PM PDT 24
Finished Jul 15 06:43:51 PM PDT 24
Peak memory 194324 kb
Host smart-3f440c7d-1513-4c3d-87ca-7bc1ca222b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222339632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1222339632
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2765892387
Short name T731
Test name
Test status
Simulation time 46382259 ps
CPU time 0.6 seconds
Started Jul 15 06:43:49 PM PDT 24
Finished Jul 15 06:43:50 PM PDT 24
Peak memory 194976 kb
Host smart-7410fc22-b2d4-4c18-96ce-64ab169140de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765892387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2765892387
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2214328969
Short name T726
Test name
Test status
Simulation time 14295907 ps
CPU time 0.6 seconds
Started Jul 15 06:43:50 PM PDT 24
Finished Jul 15 06:43:51 PM PDT 24
Peak memory 194320 kb
Host smart-352fb087-71a2-48a2-b7aa-b93d9127b9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214328969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2214328969
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.645169759
Short name T793
Test name
Test status
Simulation time 43668020 ps
CPU time 1.11 seconds
Started Jul 15 06:42:49 PM PDT 24
Finished Jul 15 06:42:51 PM PDT 24
Peak memory 198648 kb
Host smart-5d7443a4-382e-4d59-b8d5-cee54fa9f74f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645169759 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.645169759
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3045184107
Short name T819
Test name
Test status
Simulation time 18538829 ps
CPU time 0.67 seconds
Started Jul 15 06:42:43 PM PDT 24
Finished Jul 15 06:42:44 PM PDT 24
Peak memory 196120 kb
Host smart-c2330738-488d-4187-9ee4-919c210035c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045184107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3045184107
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.385256269
Short name T747
Test name
Test status
Simulation time 19241679 ps
CPU time 0.56 seconds
Started Jul 15 06:42:49 PM PDT 24
Finished Jul 15 06:42:50 PM PDT 24
Peak memory 194996 kb
Host smart-aa2f5b3e-0cae-4d50-b5c1-bd319cc7745a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385256269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.385256269
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1313258611
Short name T781
Test name
Test status
Simulation time 75364758 ps
CPU time 0.74 seconds
Started Jul 15 06:42:42 PM PDT 24
Finished Jul 15 06:42:43 PM PDT 24
Peak memory 196892 kb
Host smart-808f03ca-db4d-4c50-9c6e-1d703067176e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313258611 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1313258611
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.847321005
Short name T736
Test name
Test status
Simulation time 185148458 ps
CPU time 2.62 seconds
Started Jul 15 06:42:47 PM PDT 24
Finished Jul 15 06:42:50 PM PDT 24
Peak memory 198720 kb
Host smart-ca7f440a-aaec-4d83-8c28-91007b5bc336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847321005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.847321005
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.976649227
Short name T54
Test name
Test status
Simulation time 511506484 ps
CPU time 1.39 seconds
Started Jul 15 06:42:47 PM PDT 24
Finished Jul 15 06:42:49 PM PDT 24
Peak memory 198848 kb
Host smart-9f7bf228-1052-40bc-99f2-1e708620d2db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976649227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.976649227
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.812257153
Short name T728
Test name
Test status
Simulation time 130302458 ps
CPU time 1.74 seconds
Started Jul 15 06:42:53 PM PDT 24
Finished Jul 15 06:42:55 PM PDT 24
Peak memory 198820 kb
Host smart-4ff4bc7b-c22c-4464-b026-1c728f7c6fd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812257153 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.812257153
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1798602984
Short name T99
Test name
Test status
Simulation time 120232510 ps
CPU time 0.63 seconds
Started Jul 15 06:42:49 PM PDT 24
Finished Jul 15 06:42:50 PM PDT 24
Peak memory 195636 kb
Host smart-b36d6416-f6e6-4447-a5d4-f8aef15ef6db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798602984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1798602984
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.4258900723
Short name T841
Test name
Test status
Simulation time 48751815 ps
CPU time 0.64 seconds
Started Jul 15 06:42:52 PM PDT 24
Finished Jul 15 06:42:53 PM PDT 24
Peak memory 194480 kb
Host smart-19d945a7-fee5-41b4-8e32-44b9b3a5528f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258900723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.4258900723
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3042994532
Short name T789
Test name
Test status
Simulation time 51039204 ps
CPU time 0.72 seconds
Started Jul 15 06:42:53 PM PDT 24
Finished Jul 15 06:42:54 PM PDT 24
Peak memory 197596 kb
Host smart-cc5760c2-a085-4d5d-9d56-0047d4d1df3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042994532 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3042994532
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2882277904
Short name T844
Test name
Test status
Simulation time 298677632 ps
CPU time 3.2 seconds
Started Jul 15 06:42:52 PM PDT 24
Finished Jul 15 06:42:56 PM PDT 24
Peak memory 198740 kb
Host smart-5aeef457-0f58-4c20-ab19-a8ab2ebab17a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882277904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2882277904
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2681475930
Short name T42
Test name
Test status
Simulation time 248928838 ps
CPU time 1.12 seconds
Started Jul 15 06:42:53 PM PDT 24
Finished Jul 15 06:42:55 PM PDT 24
Peak memory 198724 kb
Host smart-b46e40a7-3a37-4df4-a123-fb22c2c91a72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681475930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2681475930
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1792086842
Short name T723
Test name
Test status
Simulation time 33338937 ps
CPU time 0.95 seconds
Started Jul 15 06:42:58 PM PDT 24
Finished Jul 15 06:42:59 PM PDT 24
Peak memory 198636 kb
Host smart-e7613a67-6ae8-44c1-a3fb-79fe8aaa6518
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792086842 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1792086842
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3088855691
Short name T113
Test name
Test status
Simulation time 13087125 ps
CPU time 0.63 seconds
Started Jul 15 06:42:58 PM PDT 24
Finished Jul 15 06:42:58 PM PDT 24
Peak memory 196192 kb
Host smart-b10aa980-f46d-47bf-8027-4dcfad7386a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088855691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3088855691
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.291229283
Short name T725
Test name
Test status
Simulation time 41451424 ps
CPU time 0.57 seconds
Started Jul 15 06:42:59 PM PDT 24
Finished Jul 15 06:43:00 PM PDT 24
Peak memory 194960 kb
Host smart-7e0dd616-2d90-4060-a789-bf6e55a4f6a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291229283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.291229283
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1632410397
Short name T111
Test name
Test status
Simulation time 31727365 ps
CPU time 0.75 seconds
Started Jul 15 06:42:59 PM PDT 24
Finished Jul 15 06:43:00 PM PDT 24
Peak memory 197432 kb
Host smart-21dd97c8-481a-433d-9748-d23f8e10bbf1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632410397 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1632410397
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4261276954
Short name T810
Test name
Test status
Simulation time 46240427 ps
CPU time 1.15 seconds
Started Jul 15 06:43:00 PM PDT 24
Finished Jul 15 06:43:01 PM PDT 24
Peak memory 198780 kb
Host smart-ad90b753-3ec6-4862-9e70-e1d11a4f18d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261276954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.4261276954
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2145128288
Short name T831
Test name
Test status
Simulation time 87641455 ps
CPU time 0.91 seconds
Started Jul 15 06:43:00 PM PDT 24
Finished Jul 15 06:43:02 PM PDT 24
Peak memory 198464 kb
Host smart-5b498aa6-1b31-4f92-8bcd-b2af3521502e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145128288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2145128288
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.162752358
Short name T770
Test name
Test status
Simulation time 59712935 ps
CPU time 1.57 seconds
Started Jul 15 06:43:00 PM PDT 24
Finished Jul 15 06:43:02 PM PDT 24
Peak memory 198772 kb
Host smart-313a5a98-d056-42ed-a546-6ef2ef8ec075
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162752358 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.162752358
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4252197021
Short name T742
Test name
Test status
Simulation time 21929124 ps
CPU time 0.58 seconds
Started Jul 15 06:42:57 PM PDT 24
Finished Jul 15 06:42:58 PM PDT 24
Peak memory 195544 kb
Host smart-4ce24e59-fa74-4e90-b7d7-6fdb3ffcc0fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252197021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.4252197021
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3075947742
Short name T812
Test name
Test status
Simulation time 47266823 ps
CPU time 0.56 seconds
Started Jul 15 06:43:04 PM PDT 24
Finished Jul 15 06:43:06 PM PDT 24
Peak memory 194352 kb
Host smart-900292a7-b55e-46c8-9383-e83695034a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075947742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3075947742
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2652527736
Short name T110
Test name
Test status
Simulation time 93243816 ps
CPU time 0.74 seconds
Started Jul 15 06:42:58 PM PDT 24
Finished Jul 15 06:43:00 PM PDT 24
Peak memory 197236 kb
Host smart-585569c8-b87a-4826-ae9c-926cd0efc13a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652527736 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2652527736
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.716027981
Short name T820
Test name
Test status
Simulation time 310035713 ps
CPU time 3.3 seconds
Started Jul 15 06:43:06 PM PDT 24
Finished Jul 15 06:43:09 PM PDT 24
Peak memory 198748 kb
Host smart-9bebb8b5-4ee7-4892-b768-c812767d2c91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716027981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.716027981
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.594521942
Short name T115
Test name
Test status
Simulation time 224636163 ps
CPU time 0.86 seconds
Started Jul 15 06:43:04 PM PDT 24
Finished Jul 15 06:43:05 PM PDT 24
Peak memory 197612 kb
Host smart-f3de19d3-bb3f-41ce-a2be-af52f2ea3f5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594521942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.594521942
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3041695102
Short name T777
Test name
Test status
Simulation time 31675463 ps
CPU time 0.66 seconds
Started Jul 15 06:43:04 PM PDT 24
Finished Jul 15 06:43:05 PM PDT 24
Peak memory 197524 kb
Host smart-c2e72eca-4e19-46b2-9c10-754eb027d25c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041695102 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3041695102
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1686622201
Short name T778
Test name
Test status
Simulation time 33076059 ps
CPU time 0.55 seconds
Started Jul 15 06:43:05 PM PDT 24
Finished Jul 15 06:43:06 PM PDT 24
Peak memory 193992 kb
Host smart-262b09c9-459a-4006-bb3d-0efe25375c7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686622201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1686622201
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.115479170
Short name T724
Test name
Test status
Simulation time 43463211 ps
CPU time 0.58 seconds
Started Jul 15 06:43:06 PM PDT 24
Finished Jul 15 06:43:07 PM PDT 24
Peak memory 194992 kb
Host smart-40f70ad2-f8c1-472f-a7d5-5204f4e6b27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115479170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.115479170
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2723100853
Short name T88
Test name
Test status
Simulation time 184170623 ps
CPU time 0.73 seconds
Started Jul 15 06:43:21 PM PDT 24
Finished Jul 15 06:43:22 PM PDT 24
Peak memory 196708 kb
Host smart-f2327aa7-e3da-49a6-9476-f3524f448950
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723100853 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2723100853
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.517330505
Short name T835
Test name
Test status
Simulation time 83049617 ps
CPU time 1.86 seconds
Started Jul 15 06:43:04 PM PDT 24
Finished Jul 15 06:43:07 PM PDT 24
Peak memory 198736 kb
Host smart-30f926d2-cb41-4ef1-bb11-c2c2caa65cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517330505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.517330505
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.788744857
Short name T55
Test name
Test status
Simulation time 106546487 ps
CPU time 1.43 seconds
Started Jul 15 06:43:06 PM PDT 24
Finished Jul 15 06:43:08 PM PDT 24
Peak memory 198680 kb
Host smart-32858a7c-f5c8-4aaa-93e9-82ada3990fa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788744857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.788744857
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3447255971
Short name T432
Test name
Test status
Simulation time 45841382 ps
CPU time 0.91 seconds
Started Jul 15 07:00:09 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 196408 kb
Host smart-f090f07f-8d28-44f4-a7b8-37a542817353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447255971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3447255971
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2777675134
Short name T229
Test name
Test status
Simulation time 292928153 ps
CPU time 14.73 seconds
Started Jul 15 07:00:08 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 198688 kb
Host smart-f10964ee-fed5-41bd-b165-f2ba9514547d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777675134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2777675134
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1581490294
Short name T515
Test name
Test status
Simulation time 183613296 ps
CPU time 1.02 seconds
Started Jul 15 07:00:13 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 197368 kb
Host smart-1c3517db-c169-494f-a4e9-2e732c4b319d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581490294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1581490294
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2209371892
Short name T638
Test name
Test status
Simulation time 21572293 ps
CPU time 0.79 seconds
Started Jul 15 07:00:12 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 196256 kb
Host smart-b57de510-1281-4af0-bb55-03f62671e17c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209371892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2209371892
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1935374108
Short name T528
Test name
Test status
Simulation time 197643047 ps
CPU time 2.56 seconds
Started Jul 15 07:00:10 PM PDT 24
Finished Jul 15 07:00:13 PM PDT 24
Peak memory 198740 kb
Host smart-80a7a46a-805c-4b20-96e7-b385597c9b79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935374108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1935374108
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.512534959
Short name T418
Test name
Test status
Simulation time 129803894 ps
CPU time 1.65 seconds
Started Jul 15 07:00:08 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 196712 kb
Host smart-648bfbc6-0536-43f9-af5d-f52fcfd66a1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512534959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.512534959
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.361629389
Short name T692
Test name
Test status
Simulation time 214291918 ps
CPU time 1.14 seconds
Started Jul 15 07:00:11 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 196444 kb
Host smart-44787bcf-127e-4a52-b9f8-352b945bcf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361629389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.361629389
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3612202807
Short name T184
Test name
Test status
Simulation time 17130968 ps
CPU time 0.73 seconds
Started Jul 15 07:00:10 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 196064 kb
Host smart-5e1b89e6-4771-4f50-a93c-ea70e668c206
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612202807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3612202807
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.937056885
Short name T223
Test name
Test status
Simulation time 217617212 ps
CPU time 3.78 seconds
Started Jul 15 07:00:11 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 198576 kb
Host smart-d1d69c8a-964a-4c50-87ff-bc75b27fb1d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937056885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.937056885
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1892809306
Short name T59
Test name
Test status
Simulation time 58040120 ps
CPU time 0.88 seconds
Started Jul 15 07:00:09 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 214256 kb
Host smart-6dfb2a55-a77d-477c-8976-85d62d6275e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892809306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1892809306
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2246462965
Short name T220
Test name
Test status
Simulation time 552843015 ps
CPU time 1.02 seconds
Started Jul 15 07:00:12 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 196224 kb
Host smart-e78da696-8a04-47cb-bc67-9d1233fc939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246462965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2246462965
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.437089975
Short name T608
Test name
Test status
Simulation time 41210182 ps
CPU time 1.22 seconds
Started Jul 15 07:00:10 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 197800 kb
Host smart-ae73777e-51d3-4b1d-9248-b8590dc0382a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437089975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.437089975
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3194482361
Short name T409
Test name
Test status
Simulation time 6773925541 ps
CPU time 74.46 seconds
Started Jul 15 07:00:10 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 198776 kb
Host smart-446097a3-7cfb-42d6-9248-8c1888dc7562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194482361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3194482361
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.104258477
Short name T71
Test name
Test status
Simulation time 118792610374 ps
CPU time 1280.12 seconds
Started Jul 15 07:00:14 PM PDT 24
Finished Jul 15 07:21:35 PM PDT 24
Peak memory 198868 kb
Host smart-104c7d59-5780-4cb0-ac73-21615775db1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=104258477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.104258477
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4232549610
Short name T439
Test name
Test status
Simulation time 19392920 ps
CPU time 0.56 seconds
Started Jul 15 07:00:15 PM PDT 24
Finished Jul 15 07:00:16 PM PDT 24
Peak memory 194648 kb
Host smart-dacacbd1-77cb-45f2-b958-a0ad18bf9ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232549610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4232549610
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1569026468
Short name T384
Test name
Test status
Simulation time 75107128 ps
CPU time 0.7 seconds
Started Jul 15 07:00:11 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 195488 kb
Host smart-37f00a1b-78a8-4ded-8451-e2887e65f2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569026468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1569026468
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3326705474
Short name T505
Test name
Test status
Simulation time 3323897299 ps
CPU time 27.69 seconds
Started Jul 15 07:00:09 PM PDT 24
Finished Jul 15 07:00:38 PM PDT 24
Peak memory 198116 kb
Host smart-34e4626e-045f-46dc-86b6-bd907ba693b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326705474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3326705474
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.122738157
Short name T20
Test name
Test status
Simulation time 66468409 ps
CPU time 0.97 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:00:18 PM PDT 24
Peak memory 198344 kb
Host smart-c70abb80-bde0-4991-89e2-5ad1f696002f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122738157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.122738157
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.4291063833
Short name T706
Test name
Test status
Simulation time 62660434 ps
CPU time 0.88 seconds
Started Jul 15 07:00:12 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 196308 kb
Host smart-568da9b9-6c8d-44ce-8e86-175a806d1842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291063833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.4291063833
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3495914269
Short name T689
Test name
Test status
Simulation time 270254426 ps
CPU time 3.25 seconds
Started Jul 15 07:00:09 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 198644 kb
Host smart-10f9cb0a-f229-43c8-8ac4-d1373f3a4e2e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495914269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3495914269
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.518136342
Short name T628
Test name
Test status
Simulation time 179720113 ps
CPU time 1.46 seconds
Started Jul 15 07:00:13 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 196788 kb
Host smart-79de2fe4-5c19-4415-8ccf-cd582acb0579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518136342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.518136342
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2322834286
Short name T541
Test name
Test status
Simulation time 23030557 ps
CPU time 0.73 seconds
Started Jul 15 07:00:10 PM PDT 24
Finished Jul 15 07:00:11 PM PDT 24
Peak memory 196620 kb
Host smart-775b38e1-d994-420f-abd4-5d4d0ce28685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322834286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2322834286
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.408429907
Short name T343
Test name
Test status
Simulation time 24544009 ps
CPU time 0.78 seconds
Started Jul 15 07:00:13 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 196640 kb
Host smart-078f7f01-3dbb-4b20-8ae1-aa06249f15e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408429907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.408429907
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2620909937
Short name T457
Test name
Test status
Simulation time 4452490315 ps
CPU time 4.68 seconds
Started Jul 15 07:00:14 PM PDT 24
Finished Jul 15 07:00:19 PM PDT 24
Peak memory 198640 kb
Host smart-34bb47a4-1797-461a-b8e5-d966ea27d5a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620909937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2620909937
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.177584793
Short name T47
Test name
Test status
Simulation time 160042043 ps
CPU time 0.82 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:00:17 PM PDT 24
Peak memory 214200 kb
Host smart-c3ce026b-20eb-43e0-9423-1ce695d34f34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177584793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.177584793
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1921492460
Short name T290
Test name
Test status
Simulation time 27801020 ps
CPU time 0.88 seconds
Started Jul 15 07:00:10 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 196716 kb
Host smart-67b46156-7bd1-4fda-b4a9-da622c1a6a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921492460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1921492460
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3989816551
Short name T248
Test name
Test status
Simulation time 100510173 ps
CPU time 1.08 seconds
Started Jul 15 07:00:11 PM PDT 24
Finished Jul 15 07:00:13 PM PDT 24
Peak memory 196840 kb
Host smart-c4ddf16d-d166-479d-8972-b45456bc2d32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989816551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3989816551
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.4255692446
Short name T454
Test name
Test status
Simulation time 381743556382 ps
CPU time 2209.29 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:37:06 PM PDT 24
Peak memory 198956 kb
Host smart-ef1a9643-a154-4310-86a0-47ebd3daa2ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4255692446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.4255692446
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3312628614
Short name T29
Test name
Test status
Simulation time 18498881 ps
CPU time 0.58 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:46 PM PDT 24
Peak memory 195336 kb
Host smart-ba54426d-4395-490d-a324-37ffdef154a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312628614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3312628614
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3989540014
Short name T252
Test name
Test status
Simulation time 191897702 ps
CPU time 0.91 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:00:52 PM PDT 24
Peak memory 197200 kb
Host smart-5f9abe79-416b-4962-b7dd-d1afd54369ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989540014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3989540014
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3518700838
Short name T154
Test name
Test status
Simulation time 785539748 ps
CPU time 27.24 seconds
Started Jul 15 07:00:47 PM PDT 24
Finished Jul 15 07:01:14 PM PDT 24
Peak memory 197596 kb
Host smart-fa599be8-2cd4-47f8-b72f-612c3d8b5177
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518700838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3518700838
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.4212916534
Short name T349
Test name
Test status
Simulation time 383521952 ps
CPU time 0.75 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:46 PM PDT 24
Peak memory 195284 kb
Host smart-5b4625ed-46d1-42c5-8180-3f5559f1eca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212916534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.4212916534
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.294157315
Short name T128
Test name
Test status
Simulation time 145653936 ps
CPU time 1.14 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 196640 kb
Host smart-436c91fe-ca90-432f-b092-42ac9dccf6ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294157315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.294157315
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2385331467
Short name T580
Test name
Test status
Simulation time 89301958 ps
CPU time 3.47 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:48 PM PDT 24
Peak memory 198780 kb
Host smart-b8660b1e-1fb5-469d-bb97-51374c420fc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385331467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2385331467
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3205615150
Short name T561
Test name
Test status
Simulation time 392574103 ps
CPU time 2.25 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:47 PM PDT 24
Peak memory 197912 kb
Host smart-6e6f1161-1cbd-4dad-899e-b2f0de7b3113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205615150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3205615150
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2805321504
Short name T630
Test name
Test status
Simulation time 134401687 ps
CPU time 1.26 seconds
Started Jul 15 07:00:45 PM PDT 24
Finished Jul 15 07:00:47 PM PDT 24
Peak memory 196516 kb
Host smart-3038f5d2-45aa-4a16-b537-204f14a7cdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805321504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2805321504
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2106327678
Short name T476
Test name
Test status
Simulation time 40100478 ps
CPU time 0.93 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:00:51 PM PDT 24
Peak memory 196540 kb
Host smart-dbf23410-ddfb-47c1-8411-87081ec5cd0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106327678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2106327678
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1733299787
Short name T280
Test name
Test status
Simulation time 155239352 ps
CPU time 2.16 seconds
Started Jul 15 07:00:46 PM PDT 24
Finished Jul 15 07:00:49 PM PDT 24
Peak memory 198612 kb
Host smart-6406095f-8b3e-4495-a608-9cf20d2482d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733299787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1733299787
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.52586843
Short name T169
Test name
Test status
Simulation time 51958145 ps
CPU time 1.07 seconds
Started Jul 15 07:00:45 PM PDT 24
Finished Jul 15 07:00:47 PM PDT 24
Peak memory 196412 kb
Host smart-5df5e061-5bf6-4c19-b0a2-8765c13528be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52586843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.52586843
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.627018363
Short name T416
Test name
Test status
Simulation time 29659792 ps
CPU time 0.86 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:44 PM PDT 24
Peak memory 196932 kb
Host smart-049d1409-0b65-4eb8-9301-e7f274336a7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627018363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.627018363
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.137940224
Short name T472
Test name
Test status
Simulation time 24027568952 ps
CPU time 84.22 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:02:09 PM PDT 24
Peak memory 198764 kb
Host smart-c29f177f-297b-4eba-891d-71a8e6ee086e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137940224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.137940224
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1648799136
Short name T425
Test name
Test status
Simulation time 21928377 ps
CPU time 0.54 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 195312 kb
Host smart-3084390c-e87b-4be2-ad16-0f0db22a5bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648799136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1648799136
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3369204739
Short name T566
Test name
Test status
Simulation time 42121895 ps
CPU time 0.74 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:00:51 PM PDT 24
Peak memory 194800 kb
Host smart-ba21944b-fc04-4c7e-b520-c571604c0db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369204739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3369204739
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2263135077
Short name T254
Test name
Test status
Simulation time 800417685 ps
CPU time 14.52 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:01:09 PM PDT 24
Peak memory 198692 kb
Host smart-54cee006-9b45-4666-8766-ec938cd2c638
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263135077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2263135077
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2488837436
Short name T443
Test name
Test status
Simulation time 90324684 ps
CPU time 0.76 seconds
Started Jul 15 07:00:56 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 195440 kb
Host smart-cda2135b-e359-42d1-b867-9f3794129c26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488837436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2488837436
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.238425738
Short name T361
Test name
Test status
Simulation time 36548085 ps
CPU time 0.87 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 197044 kb
Host smart-70962e57-2603-4eb9-8578-4d69ffcb1e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238425738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.238425738
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1782154345
Short name T286
Test name
Test status
Simulation time 42522172 ps
CPU time 1.82 seconds
Started Jul 15 07:00:56 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 198804 kb
Host smart-9d63b831-55e7-4295-8342-f22298a86397
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782154345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1782154345
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2136086788
Short name T304
Test name
Test status
Simulation time 55931584 ps
CPU time 1.25 seconds
Started Jul 15 07:00:56 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 196108 kb
Host smart-92a91525-9008-4d40-8b72-2e1957dec4f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136086788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2136086788
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1009662586
Short name T650
Test name
Test status
Simulation time 31439145 ps
CPU time 1.04 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:00:52 PM PDT 24
Peak memory 196584 kb
Host smart-659bcc04-cd68-46ac-8642-adc39f1fe840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009662586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1009662586
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.178333490
Short name T312
Test name
Test status
Simulation time 57694642 ps
CPU time 1.22 seconds
Started Jul 15 07:00:55 PM PDT 24
Finished Jul 15 07:00:57 PM PDT 24
Peak memory 197796 kb
Host smart-ef2b69b4-a395-4d91-9218-204956b6e219
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178333490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.178333490
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.829751654
Short name T61
Test name
Test status
Simulation time 101278378 ps
CPU time 2.57 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 198508 kb
Host smart-5dbfafc4-106b-41b9-9f1f-49ee8507fcdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829751654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.829751654
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.381471502
Short name T225
Test name
Test status
Simulation time 96494170 ps
CPU time 1.3 seconds
Started Jul 15 07:00:44 PM PDT 24
Finished Jul 15 07:00:47 PM PDT 24
Peak memory 198672 kb
Host smart-5d39b4d1-c93d-468d-bc88-8cafce06c61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381471502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.381471502
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2154817893
Short name T431
Test name
Test status
Simulation time 82595943 ps
CPU time 1.22 seconds
Started Jul 15 07:00:44 PM PDT 24
Finished Jul 15 07:00:46 PM PDT 24
Peak memory 197332 kb
Host smart-1c2c1974-2169-40f3-9029-01c908cd2bf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154817893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2154817893
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3788211123
Short name T148
Test name
Test status
Simulation time 1272149629 ps
CPU time 27.63 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:01:20 PM PDT 24
Peak memory 198648 kb
Host smart-75aaf556-8726-4dac-8029-936dcfad02e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788211123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3788211123
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1468914793
Short name T135
Test name
Test status
Simulation time 14194212 ps
CPU time 0.61 seconds
Started Jul 15 07:00:51 PM PDT 24
Finished Jul 15 07:00:52 PM PDT 24
Peak memory 195284 kb
Host smart-ac16bc6e-6775-4830-a50e-020289ee49bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468914793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1468914793
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.709258497
Short name T15
Test name
Test status
Simulation time 23897779 ps
CPU time 0.7 seconds
Started Jul 15 07:00:51 PM PDT 24
Finished Jul 15 07:00:53 PM PDT 24
Peak memory 195544 kb
Host smart-0a89f372-334c-49e9-80de-5961490ed286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709258497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.709258497
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2433249872
Short name T310
Test name
Test status
Simulation time 590109953 ps
CPU time 19 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:01:12 PM PDT 24
Peak memory 197696 kb
Host smart-98880124-3df0-4f7c-a0c6-bf9187a89baa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433249872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2433249872
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.790627948
Short name T444
Test name
Test status
Simulation time 139397013 ps
CPU time 0.76 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 197288 kb
Host smart-47a4db4e-a7de-48b9-a774-0a9c6aee78e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790627948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.790627948
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2590624352
Short name T435
Test name
Test status
Simulation time 115892559 ps
CPU time 0.8 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:00:51 PM PDT 24
Peak memory 196172 kb
Host smart-65dcb2ee-e3bf-44e4-8f4f-ae6d1c5564ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590624352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2590624352
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2300898518
Short name T427
Test name
Test status
Simulation time 69232070 ps
CPU time 2.91 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:57 PM PDT 24
Peak memory 198716 kb
Host smart-f069c9cd-384b-4779-94e0-c43c982d26b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300898518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2300898518
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.200628515
Short name T216
Test name
Test status
Simulation time 272559920 ps
CPU time 1.55 seconds
Started Jul 15 07:00:54 PM PDT 24
Finished Jul 15 07:00:57 PM PDT 24
Peak memory 196740 kb
Host smart-9ab37d10-6585-4ee1-ab1a-387f4aee6efb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200628515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
200628515
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.625411819
Short name T652
Test name
Test status
Simulation time 75925562 ps
CPU time 1.04 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 196640 kb
Host smart-2edebd01-2524-4e01-943a-de68a0493200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625411819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.625411819
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2383030007
Short name T201
Test name
Test status
Simulation time 105468072 ps
CPU time 0.8 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 196000 kb
Host smart-fdb5986b-f2dc-435e-ae38-ce104ca43bcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383030007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2383030007
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.751563983
Short name T287
Test name
Test status
Simulation time 941470775 ps
CPU time 5.76 seconds
Started Jul 15 07:00:51 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 198592 kb
Host smart-6cabd823-ed46-4d44-8874-cc5217605af2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751563983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.751563983
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3707750632
Short name T265
Test name
Test status
Simulation time 223269207 ps
CPU time 1.27 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 197384 kb
Host smart-b559cae6-327f-4ca7-a7c0-4facf99a181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707750632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3707750632
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2696695171
Short name T181
Test name
Test status
Simulation time 307492044 ps
CPU time 0.9 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 195816 kb
Host smart-528e2422-d869-4309-b489-2f30e644c607
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696695171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2696695171
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4113345355
Short name T9
Test name
Test status
Simulation time 56903407817 ps
CPU time 79.41 seconds
Started Jul 15 07:00:55 PM PDT 24
Finished Jul 15 07:02:15 PM PDT 24
Peak memory 198740 kb
Host smart-3e7d1cef-5099-457f-a789-b4385de849d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113345355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4113345355
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2084644796
Short name T69
Test name
Test status
Simulation time 6649155486 ps
CPU time 239.71 seconds
Started Jul 15 07:00:54 PM PDT 24
Finished Jul 15 07:04:54 PM PDT 24
Peak memory 199084 kb
Host smart-9d3cc696-d7aa-42e0-8c03-a655df29508a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2084644796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2084644796
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3035338726
Short name T266
Test name
Test status
Simulation time 41659159 ps
CPU time 0.6 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 195676 kb
Host smart-6a8341d9-2459-47b1-acd4-c052f022b6e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035338726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3035338726
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2975432189
Short name T616
Test name
Test status
Simulation time 23950321 ps
CPU time 0.71 seconds
Started Jul 15 07:00:51 PM PDT 24
Finished Jul 15 07:00:52 PM PDT 24
Peak memory 195840 kb
Host smart-ebaa74c3-cd08-4e15-b679-3abb58f5f797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975432189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2975432189
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3965350117
Short name T593
Test name
Test status
Simulation time 628478735 ps
CPU time 17.42 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:01:15 PM PDT 24
Peak memory 197360 kb
Host smart-d0d44ea8-056c-4de7-8f08-5b6818527919
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965350117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3965350117
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.4009037225
Short name T640
Test name
Test status
Simulation time 563990882 ps
CPU time 0.98 seconds
Started Jul 15 07:00:51 PM PDT 24
Finished Jul 15 07:00:53 PM PDT 24
Peak memory 198676 kb
Host smart-cd5cfb61-9783-4213-abaf-8bb3729b5f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009037225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.4009037225
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3638301172
Short name T623
Test name
Test status
Simulation time 121692116 ps
CPU time 0.8 seconds
Started Jul 15 07:00:51 PM PDT 24
Finished Jul 15 07:00:52 PM PDT 24
Peak memory 196924 kb
Host smart-4360e371-b585-4a3a-af59-15a87a855537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638301172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3638301172
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3119602903
Short name T206
Test name
Test status
Simulation time 176610058 ps
CPU time 1.97 seconds
Started Jul 15 07:00:55 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 197116 kb
Host smart-ad6c011b-b8f6-49ff-ad93-c0aac16472c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119602903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3119602903
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4166084174
Short name T533
Test name
Test status
Simulation time 155662944 ps
CPU time 3.56 seconds
Started Jul 15 07:00:55 PM PDT 24
Finished Jul 15 07:01:00 PM PDT 24
Peak memory 196532 kb
Host smart-3b6d07ef-e411-4de2-81bf-535f5d00b035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166084174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4166084174
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1547313763
Short name T152
Test name
Test status
Simulation time 17671485 ps
CPU time 0.74 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 196084 kb
Host smart-7d622ab9-5f4d-4cac-b634-21988153097b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547313763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1547313763
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.4219616074
Short name T198
Test name
Test status
Simulation time 343719030 ps
CPU time 1.04 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 196452 kb
Host smart-549e7be7-9ab0-4215-8ae4-58af2c91c3c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219616074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.4219616074
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.381011254
Short name T668
Test name
Test status
Simulation time 236834448 ps
CPU time 2.94 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 198696 kb
Host smart-799f8496-17f0-487a-b195-650037673879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381011254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.381011254
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.192421973
Short name T588
Test name
Test status
Simulation time 79705809 ps
CPU time 1.26 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 197076 kb
Host smart-8cd4a360-890c-4131-8384-f90e16273129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192421973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.192421973
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1354674871
Short name T370
Test name
Test status
Simulation time 62375843 ps
CPU time 1.14 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 196208 kb
Host smart-78e6c1f6-94c5-47af-8b23-588dce3b82b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354674871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1354674871
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1601138342
Short name T714
Test name
Test status
Simulation time 25477604567 ps
CPU time 89.48 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:02:21 PM PDT 24
Peak memory 198768 kb
Host smart-71b3a197-6065-41da-b171-f71aa4e2c1e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601138342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1601138342
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1610778361
Short name T70
Test name
Test status
Simulation time 91951034484 ps
CPU time 1017.62 seconds
Started Jul 15 07:00:51 PM PDT 24
Finished Jul 15 07:17:49 PM PDT 24
Peak memory 198884 kb
Host smart-933f7903-f862-4831-98d7-2e97b5878c9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1610778361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1610778361
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3064231357
Short name T121
Test name
Test status
Simulation time 19237814 ps
CPU time 0.65 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 194624 kb
Host smart-a66c7af6-cedc-4f56-8e45-670ef5b49ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064231357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3064231357
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2446098908
Short name T512
Test name
Test status
Simulation time 73308037 ps
CPU time 0.88 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 196656 kb
Host smart-18e6a5c0-5ead-4b59-8ac9-22877074ba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446098908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2446098908
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.887899807
Short name T522
Test name
Test status
Simulation time 1947926002 ps
CPU time 13.37 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:01:11 PM PDT 24
Peak memory 197444 kb
Host smart-ace5460b-b6ab-496f-994a-16a84863adf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887899807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.887899807
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2497399734
Short name T685
Test name
Test status
Simulation time 89012084 ps
CPU time 0.85 seconds
Started Jul 15 07:00:56 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 197252 kb
Host smart-397ce578-3642-4ff5-8de8-e4a2829dfb59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497399734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2497399734
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2416874176
Short name T202
Test name
Test status
Simulation time 367786924 ps
CPU time 1.22 seconds
Started Jul 15 07:00:50 PM PDT 24
Finished Jul 15 07:00:52 PM PDT 24
Peak memory 196792 kb
Host smart-faa203bb-885d-4792-9ef3-fbebba9e74d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416874176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2416874176
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1525282784
Short name T556
Test name
Test status
Simulation time 93505516 ps
CPU time 3.76 seconds
Started Jul 15 07:00:59 PM PDT 24
Finished Jul 15 07:01:04 PM PDT 24
Peak memory 196984 kb
Host smart-ea0e6e3a-68c6-43f5-bc8d-969b8392f5f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525282784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1525282784
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2368227097
Short name T699
Test name
Test status
Simulation time 106631007 ps
CPU time 2.34 seconds
Started Jul 15 07:00:52 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 197688 kb
Host smart-3c1604a5-d923-4d86-a374-1def0e519ca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368227097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2368227097
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.144988596
Short name T164
Test name
Test status
Simulation time 26634080 ps
CPU time 0.95 seconds
Started Jul 15 07:00:49 PM PDT 24
Finished Jul 15 07:00:51 PM PDT 24
Peak memory 196452 kb
Host smart-8a726928-5601-44c4-a3be-3d8ed563c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144988596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.144988596
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3855672022
Short name T176
Test name
Test status
Simulation time 22224835 ps
CPU time 0.98 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 196764 kb
Host smart-a1785213-a613-42c4-9584-e9df72dd4c2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855672022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3855672022
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1798785900
Short name T211
Test name
Test status
Simulation time 69153798 ps
CPU time 1.32 seconds
Started Jul 15 07:00:55 PM PDT 24
Finished Jul 15 07:00:57 PM PDT 24
Peak memory 198456 kb
Host smart-ca4d33a5-0155-43f0-859e-03f2b52f0319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798785900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1798785900
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2741641006
Short name T174
Test name
Test status
Simulation time 45877470 ps
CPU time 1.21 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 197148 kb
Host smart-d87171c3-e8c9-4eea-abd0-71da7996ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741641006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2741641006
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2064057901
Short name T575
Test name
Test status
Simulation time 76089120 ps
CPU time 1.19 seconds
Started Jul 15 07:00:53 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 196368 kb
Host smart-f2ec936b-e553-4afc-99de-cf5719c393de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064057901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2064057901
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3387909580
Short name T693
Test name
Test status
Simulation time 9726857239 ps
CPU time 26.68 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 198820 kb
Host smart-0fc15e8a-ee19-468f-ab7d-da59ec1d1eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387909580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3387909580
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2703223471
Short name T268
Test name
Test status
Simulation time 38013126 ps
CPU time 0.57 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:01:00 PM PDT 24
Peak memory 194592 kb
Host smart-3d3f5747-7d67-4ed0-afaf-69c90e08874c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703223471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2703223471
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1315695797
Short name T544
Test name
Test status
Simulation time 64541100 ps
CPU time 0.8 seconds
Started Jul 15 07:00:56 PM PDT 24
Finished Jul 15 07:00:57 PM PDT 24
Peak memory 196012 kb
Host smart-7e13c9ac-b093-44ba-863e-05f7939e837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315695797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1315695797
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1191208975
Short name T568
Test name
Test status
Simulation time 2184582945 ps
CPU time 13.11 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:01:12 PM PDT 24
Peak memory 197836 kb
Host smart-de5d884a-6f72-463f-acd9-c3780ded075f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191208975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1191208975
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2189287208
Short name T296
Test name
Test status
Simulation time 45181801 ps
CPU time 0.78 seconds
Started Jul 15 07:00:59 PM PDT 24
Finished Jul 15 07:01:01 PM PDT 24
Peak memory 196540 kb
Host smart-032a2750-0aa1-4a7a-9a46-79b231e86497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189287208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2189287208
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2073331835
Short name T674
Test name
Test status
Simulation time 327576257 ps
CPU time 1.24 seconds
Started Jul 15 07:00:56 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 196736 kb
Host smart-0d23168f-80a1-488d-a193-98cad2c0a3ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073331835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2073331835
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3859679391
Short name T183
Test name
Test status
Simulation time 245613465 ps
CPU time 1.05 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:01:00 PM PDT 24
Peak memory 197724 kb
Host smart-03652b07-1393-4886-bed1-de7dd7cd80d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859679391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3859679391
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2414826047
Short name T298
Test name
Test status
Simulation time 312564579 ps
CPU time 2.53 seconds
Started Jul 15 07:00:55 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 197640 kb
Host smart-c61092a1-7fdc-444e-9ad2-1a811fbda373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414826047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2414826047
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4140598135
Short name T543
Test name
Test status
Simulation time 156249286 ps
CPU time 1.36 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 198696 kb
Host smart-3904d3fb-da33-4482-9e54-7c254b5829db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140598135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4140598135
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1018914365
Short name T412
Test name
Test status
Simulation time 15849270 ps
CPU time 0.69 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:01:00 PM PDT 24
Peak memory 194844 kb
Host smart-c918f8b3-c1f9-4171-851e-5b1abebe24f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018914365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1018914365
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.645445229
Short name T657
Test name
Test status
Simulation time 146719241 ps
CPU time 3.76 seconds
Started Jul 15 07:00:59 PM PDT 24
Finished Jul 15 07:01:04 PM PDT 24
Peak memory 198572 kb
Host smart-115dbd6b-d790-4034-b7e6-bd0e237b7a5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645445229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.645445229
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.837971276
Short name T83
Test name
Test status
Simulation time 62581839 ps
CPU time 1.13 seconds
Started Jul 15 07:00:56 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 196456 kb
Host smart-60fa3b8e-825a-4657-afe5-f03f47578141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837971276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.837971276
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2022573731
Short name T218
Test name
Test status
Simulation time 175155147 ps
CPU time 1.64 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:01:01 PM PDT 24
Peak memory 197300 kb
Host smart-cc6a6e64-6f10-4e99-943d-38e30d410c54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022573731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2022573731
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3834936400
Short name T351
Test name
Test status
Simulation time 4735210991 ps
CPU time 115.68 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 198820 kb
Host smart-10e86135-7357-41a6-bdab-e788b93827b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834936400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3834936400
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.765227645
Short name T716
Test name
Test status
Simulation time 97834414992 ps
CPU time 2173.66 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:37:12 PM PDT 24
Peak memory 198932 kb
Host smart-c862e3d1-b8d7-46ce-8ad8-21c57193d1d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=765227645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.765227645
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.213731536
Short name T433
Test name
Test status
Simulation time 42488313 ps
CPU time 0.56 seconds
Started Jul 15 07:01:05 PM PDT 24
Finished Jul 15 07:01:06 PM PDT 24
Peak memory 194636 kb
Host smart-54984e18-29a0-45b1-bd6c-11839135efa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213731536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.213731536
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3727492921
Short name T237
Test name
Test status
Simulation time 86545115 ps
CPU time 0.62 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 195404 kb
Host smart-01ec44d9-45b9-44dc-bd56-fd2c2b10e113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727492921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3727492921
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2802896628
Short name T635
Test name
Test status
Simulation time 947183527 ps
CPU time 11.17 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:01:10 PM PDT 24
Peak memory 197364 kb
Host smart-2473e08a-82d4-47c2-a2e4-f0ea573555ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802896628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2802896628
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1419203199
Short name T709
Test name
Test status
Simulation time 252769929 ps
CPU time 1.18 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:01:04 PM PDT 24
Peak memory 198520 kb
Host smart-1c0f9cc8-94fc-4e93-a174-d88b71d1ff01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419203199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1419203199
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1759907814
Short name T576
Test name
Test status
Simulation time 114939084 ps
CPU time 0.69 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 195628 kb
Host smart-48a6c5b5-e10e-43f9-a144-18c0a3d89db9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759907814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1759907814
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4166738186
Short name T368
Test name
Test status
Simulation time 97508121 ps
CPU time 1.07 seconds
Started Jul 15 07:00:59 PM PDT 24
Finished Jul 15 07:01:01 PM PDT 24
Peak memory 197672 kb
Host smart-f73f5e06-7450-45a3-b49a-878b8d4ffaf0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166738186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4166738186
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3260205354
Short name T141
Test name
Test status
Simulation time 54048730 ps
CPU time 1.3 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 196452 kb
Host smart-8e0ff917-30d4-4601-bad9-c7fb174e1c05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260205354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3260205354
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2058432628
Short name T513
Test name
Test status
Simulation time 16521987 ps
CPU time 0.64 seconds
Started Jul 15 07:00:59 PM PDT 24
Finished Jul 15 07:01:01 PM PDT 24
Peak memory 194852 kb
Host smart-efd9d5ed-2110-4507-912a-8067f61f4f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058432628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2058432628
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.813376385
Short name T278
Test name
Test status
Simulation time 85811541 ps
CPU time 1.06 seconds
Started Jul 15 07:00:58 PM PDT 24
Finished Jul 15 07:01:00 PM PDT 24
Peak memory 196504 kb
Host smart-317c5cb1-41dc-4291-8245-b250c190dc6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813376385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.813376385
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3559609148
Short name T527
Test name
Test status
Simulation time 102526810 ps
CPU time 1.75 seconds
Started Jul 15 07:00:55 PM PDT 24
Finished Jul 15 07:00:58 PM PDT 24
Peak memory 198588 kb
Host smart-9ac7b856-e87b-49fd-891f-3604d0104c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559609148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3559609148
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.100406589
Short name T189
Test name
Test status
Simulation time 34286379 ps
CPU time 0.84 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 197604 kb
Host smart-c28778f3-134f-42bb-897f-ea0ab46a2c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100406589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.100406589
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.299868783
Short name T333
Test name
Test status
Simulation time 48837136 ps
CPU time 1.31 seconds
Started Jul 15 07:00:57 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 197556 kb
Host smart-1178fb84-6992-4ada-8331-06d3f4d3ebb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299868783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.299868783
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.331766286
Short name T307
Test name
Test status
Simulation time 27628586787 ps
CPU time 102.77 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:02:45 PM PDT 24
Peak memory 198804 kb
Host smart-af16780d-e652-4a17-9697-5f459ca4dbf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331766286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.331766286
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.787871777
Short name T606
Test name
Test status
Simulation time 24859035 ps
CPU time 0.56 seconds
Started Jul 15 07:01:01 PM PDT 24
Finished Jul 15 07:01:02 PM PDT 24
Peak memory 193452 kb
Host smart-d4c8da1e-8da6-4a00-884c-2256b475d6d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787871777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.787871777
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2642118259
Short name T520
Test name
Test status
Simulation time 138619655 ps
CPU time 0.79 seconds
Started Jul 15 07:01:04 PM PDT 24
Finished Jul 15 07:01:06 PM PDT 24
Peak memory 196040 kb
Host smart-1d190c0b-e8bf-4f8d-8afd-4ee015c68bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642118259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2642118259
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3583586481
Short name T542
Test name
Test status
Simulation time 303618709 ps
CPU time 3.71 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:01:06 PM PDT 24
Peak memory 197280 kb
Host smart-d39ee556-0cfd-4749-b738-7208f833bb58
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583586481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3583586481
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.154023547
Short name T383
Test name
Test status
Simulation time 168870626 ps
CPU time 0.94 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:01:03 PM PDT 24
Peak memory 197872 kb
Host smart-471c1210-9c36-4160-8fe8-63406cf6d1ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154023547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.154023547
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2245098693
Short name T166
Test name
Test status
Simulation time 34934851 ps
CPU time 0.74 seconds
Started Jul 15 07:01:05 PM PDT 24
Finished Jul 15 07:01:06 PM PDT 24
Peak memory 195104 kb
Host smart-b73b4493-102c-4ca7-a266-1a1ba90e9c5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245098693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2245098693
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3497494964
Short name T634
Test name
Test status
Simulation time 648444181 ps
CPU time 2.02 seconds
Started Jul 15 07:01:04 PM PDT 24
Finished Jul 15 07:01:06 PM PDT 24
Peak memory 198636 kb
Host smart-b943adb3-0a8a-45ae-86df-350d7dabe350
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497494964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3497494964
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1720975284
Short name T313
Test name
Test status
Simulation time 51746194 ps
CPU time 1.3 seconds
Started Jul 15 07:01:05 PM PDT 24
Finished Jul 15 07:01:08 PM PDT 24
Peak memory 198244 kb
Host smart-531a84d9-4a78-4f0c-a62f-f95aed3a6248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720975284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1720975284
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1669844446
Short name T589
Test name
Test status
Simulation time 35094028 ps
CPU time 0.94 seconds
Started Jul 15 07:01:06 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 196160 kb
Host smart-a4597337-74b5-48be-8859-47e48795cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669844446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1669844446
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3571075038
Short name T67
Test name
Test status
Simulation time 36841356 ps
CPU time 1.27 seconds
Started Jul 15 07:01:01 PM PDT 24
Finished Jul 15 07:01:03 PM PDT 24
Peak memory 197708 kb
Host smart-82d17d41-fedf-40db-95c4-a83b3e10fd81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571075038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3571075038
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3109436499
Short name T552
Test name
Test status
Simulation time 62165912 ps
CPU time 1.5 seconds
Started Jul 15 07:01:06 PM PDT 24
Finished Jul 15 07:01:08 PM PDT 24
Peak memory 198620 kb
Host smart-b31ff8f5-8461-4876-bc6b-729a9ad5d651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109436499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3109436499
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3365713562
Short name T386
Test name
Test status
Simulation time 96641448 ps
CPU time 1 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:01:04 PM PDT 24
Peak memory 196308 kb
Host smart-c0e29a5a-ae96-43df-af28-a79a326206dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365713562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3365713562
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1087199637
Short name T159
Test name
Test status
Simulation time 37272522 ps
CPU time 0.99 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:01:03 PM PDT 24
Peak memory 197044 kb
Host smart-561b06c1-75d7-427d-b339-a44fda8cb94a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087199637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1087199637
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2684463296
Short name T601
Test name
Test status
Simulation time 44338953382 ps
CPU time 204.39 seconds
Started Jul 15 07:01:03 PM PDT 24
Finished Jul 15 07:04:28 PM PDT 24
Peak memory 198824 kb
Host smart-08f3a677-abc3-4af8-ac42-2bce1a06fb21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684463296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2684463296
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1245660624
Short name T253
Test name
Test status
Simulation time 15006780 ps
CPU time 0.61 seconds
Started Jul 15 07:01:05 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 195364 kb
Host smart-9095cd78-c6d3-4c0e-8418-9851d27a5767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245660624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1245660624
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.392537500
Short name T535
Test name
Test status
Simulation time 347453448 ps
CPU time 0.89 seconds
Started Jul 15 07:01:06 PM PDT 24
Finished Jul 15 07:01:08 PM PDT 24
Peak memory 196428 kb
Host smart-7573d072-f10e-48e7-9a0c-e167d67acd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392537500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.392537500
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.77468800
Short name T337
Test name
Test status
Simulation time 539027337 ps
CPU time 15.71 seconds
Started Jul 15 07:01:04 PM PDT 24
Finished Jul 15 07:01:20 PM PDT 24
Peak memory 197468 kb
Host smart-7248fb35-4bfb-41c5-b249-aa2015169973
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77468800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stress
.77468800
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1017415935
Short name T658
Test name
Test status
Simulation time 86040856 ps
CPU time 0.88 seconds
Started Jul 15 07:01:05 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 197880 kb
Host smart-152ea5fc-817a-4fa5-9955-fddcd38c6749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017415935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1017415935
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3293142088
Short name T415
Test name
Test status
Simulation time 229638143 ps
CPU time 0.94 seconds
Started Jul 15 07:01:05 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 197908 kb
Host smart-61b98bb5-bd5e-4673-a438-baf84fda6a23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293142088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3293142088
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3599071202
Short name T485
Test name
Test status
Simulation time 35272047 ps
CPU time 1.55 seconds
Started Jul 15 07:01:03 PM PDT 24
Finished Jul 15 07:01:06 PM PDT 24
Peak memory 197096 kb
Host smart-0a3e5c7a-a96c-4546-84d3-56f65eb8f169
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599071202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3599071202
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3563855727
Short name T187
Test name
Test status
Simulation time 196618244 ps
CPU time 1.32 seconds
Started Jul 15 07:01:03 PM PDT 24
Finished Jul 15 07:01:05 PM PDT 24
Peak memory 197540 kb
Host smart-d6d7a443-9dda-432f-b961-50a924fdda48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563855727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3563855727
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2636385517
Short name T585
Test name
Test status
Simulation time 126845351 ps
CPU time 0.92 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:01:04 PM PDT 24
Peak memory 196480 kb
Host smart-0da875a9-3d76-4583-a755-35750d84976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636385517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2636385517
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3046400663
Short name T341
Test name
Test status
Simulation time 23293253 ps
CPU time 0.75 seconds
Started Jul 15 07:01:03 PM PDT 24
Finished Jul 15 07:01:05 PM PDT 24
Peak memory 196056 kb
Host smart-4661acae-9778-4094-85ec-3af7c714e06a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046400663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3046400663
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3487223107
Short name T573
Test name
Test status
Simulation time 66924678 ps
CPU time 3.05 seconds
Started Jul 15 07:01:04 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 198648 kb
Host smart-0210cc35-bd3f-4eb7-9538-f85dca89c692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487223107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3487223107
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1623767498
Short name T715
Test name
Test status
Simulation time 195089052 ps
CPU time 1.09 seconds
Started Jul 15 07:01:05 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 196464 kb
Host smart-2bf6e6ac-d267-45ae-893a-85b4d3ea8150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623767498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1623767498
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1615384233
Short name T460
Test name
Test status
Simulation time 962252031 ps
CPU time 1.48 seconds
Started Jul 15 07:01:02 PM PDT 24
Finished Jul 15 07:01:05 PM PDT 24
Peak memory 197532 kb
Host smart-1c0474a0-e2a8-4f0b-9d17-3d9bc181a411
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615384233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1615384233
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4110378844
Short name T336
Test name
Test status
Simulation time 87016434922 ps
CPU time 56.15 seconds
Started Jul 15 07:01:04 PM PDT 24
Finished Jul 15 07:02:00 PM PDT 24
Peak memory 198780 kb
Host smart-9cbffcbd-c5ce-4bcc-9152-659718b1ac86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110378844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4110378844
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3638138124
Short name T648
Test name
Test status
Simulation time 19403229 ps
CPU time 0.58 seconds
Started Jul 15 07:01:09 PM PDT 24
Finished Jul 15 07:01:10 PM PDT 24
Peak memory 194636 kb
Host smart-d0d27e0d-4444-46af-b759-98acd107a5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638138124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3638138124
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2444228251
Short name T324
Test name
Test status
Simulation time 96134676 ps
CPU time 0.68 seconds
Started Jul 15 07:01:13 PM PDT 24
Finished Jul 15 07:01:14 PM PDT 24
Peak memory 195436 kb
Host smart-53eb80aa-ff67-4084-9d62-f70b5adff12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444228251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2444228251
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3401782589
Short name T124
Test name
Test status
Simulation time 528679668 ps
CPU time 27.35 seconds
Started Jul 15 07:01:10 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 198676 kb
Host smart-6f650008-6075-457e-b632-89e37a6d27dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401782589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3401782589
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1222825771
Short name T719
Test name
Test status
Simulation time 38161986 ps
CPU time 0.73 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:13 PM PDT 24
Peak memory 196384 kb
Host smart-27d658c0-f7ea-4610-bed9-db09e9a084b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222825771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1222825771
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2066972508
Short name T200
Test name
Test status
Simulation time 17116847 ps
CPU time 0.69 seconds
Started Jul 15 07:01:10 PM PDT 24
Finished Jul 15 07:01:11 PM PDT 24
Peak memory 194992 kb
Host smart-52b32402-f5fd-422c-af23-afa5a609519d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066972508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2066972508
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2297037385
Short name T598
Test name
Test status
Simulation time 330664912 ps
CPU time 3.47 seconds
Started Jul 15 07:01:13 PM PDT 24
Finished Jul 15 07:01:17 PM PDT 24
Peak memory 198724 kb
Host smart-27013b86-763a-47b6-be50-8976d2fdb584
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297037385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2297037385
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1790620194
Short name T292
Test name
Test status
Simulation time 1298804410 ps
CPU time 3.27 seconds
Started Jul 15 07:01:14 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 196508 kb
Host smart-6af10abc-a39e-4dd2-b566-8c9f7955f5b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790620194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1790620194
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1694312687
Short name T279
Test name
Test status
Simulation time 126671902 ps
CPU time 1.2 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:13 PM PDT 24
Peak memory 197704 kb
Host smart-326674ea-3dc1-4ac5-a528-dfa07fb95ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694312687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1694312687
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.827514934
Short name T559
Test name
Test status
Simulation time 106593653 ps
CPU time 1.16 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:13 PM PDT 24
Peak memory 197332 kb
Host smart-4a132410-4b13-4cc9-93e4-6d1d6cd08c08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827514934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.827514934
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.10293768
Short name T66
Test name
Test status
Simulation time 175819417 ps
CPU time 1.43 seconds
Started Jul 15 07:01:10 PM PDT 24
Finished Jul 15 07:01:12 PM PDT 24
Peak memory 198572 kb
Host smart-39a708c3-df57-4faa-ab6c-e31bcc0fdc25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10293768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand
om_long_reg_writes_reg_reads.10293768
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3107699581
Short name T530
Test name
Test status
Simulation time 38542245 ps
CPU time 0.88 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:13 PM PDT 24
Peak memory 197136 kb
Host smart-833d9eca-a5d3-4204-8a65-a60eed87bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107699581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3107699581
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.295302956
Short name T134
Test name
Test status
Simulation time 64271926 ps
CPU time 1.14 seconds
Started Jul 15 07:01:13 PM PDT 24
Finished Jul 15 07:01:15 PM PDT 24
Peak memory 197136 kb
Host smart-a547f19a-4784-414b-924e-61c30c570651
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295302956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.295302956
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1548031992
Short name T188
Test name
Test status
Simulation time 3770333965 ps
CPU time 41.45 seconds
Started Jul 15 07:01:10 PM PDT 24
Finished Jul 15 07:01:52 PM PDT 24
Peak memory 198780 kb
Host smart-129ccd61-7b30-4dc9-932f-9629d76ce539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548031992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1548031992
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2698015271
Short name T626
Test name
Test status
Simulation time 22443212546 ps
CPU time 345.14 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 198916 kb
Host smart-3f1e9653-b1dc-470b-8b45-91547725a1a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2698015271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2698015271
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4291903149
Short name T718
Test name
Test status
Simulation time 25086702 ps
CPU time 0.56 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:00:18 PM PDT 24
Peak memory 195344 kb
Host smart-3d0fd581-402e-4cc8-b1ad-6cfedfe446ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291903149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4291903149
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1682344997
Short name T707
Test name
Test status
Simulation time 117364467 ps
CPU time 0.72 seconds
Started Jul 15 07:00:19 PM PDT 24
Finished Jul 15 07:00:20 PM PDT 24
Peak memory 194704 kb
Host smart-64801163-0c3e-4f41-aec0-83aade3ae617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682344997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1682344997
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1611204973
Short name T82
Test name
Test status
Simulation time 5505463424 ps
CPU time 24.68 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:00:42 PM PDT 24
Peak memory 197828 kb
Host smart-62858a99-add9-4693-9a00-3893771f1615
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611204973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1611204973
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2523426594
Short name T682
Test name
Test status
Simulation time 94371616 ps
CPU time 0.66 seconds
Started Jul 15 07:00:15 PM PDT 24
Finished Jul 15 07:00:16 PM PDT 24
Peak memory 195204 kb
Host smart-70461086-5d64-4962-88c6-869f79fa9ae0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523426594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2523426594
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.682442280
Short name T696
Test name
Test status
Simulation time 509480359 ps
CPU time 1.07 seconds
Started Jul 15 07:00:17 PM PDT 24
Finished Jul 15 07:00:18 PM PDT 24
Peak memory 196412 kb
Host smart-e2c95c84-bbe4-4288-bbe7-9eb1ead96166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682442280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.682442280
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3799562045
Short name T617
Test name
Test status
Simulation time 99927347 ps
CPU time 1.93 seconds
Started Jul 15 07:00:17 PM PDT 24
Finished Jul 15 07:00:19 PM PDT 24
Peak memory 198768 kb
Host smart-2bcaedc9-203e-4e19-8d6c-dd4a9358fdf7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799562045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3799562045
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2777025119
Short name T36
Test name
Test status
Simulation time 180254117 ps
CPU time 1.58 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:00:18 PM PDT 24
Peak memory 196700 kb
Host smart-e168ffb9-1159-4c9a-a3f3-54eed0d0e44f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777025119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2777025119
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4050256788
Short name T375
Test name
Test status
Simulation time 56680144 ps
CPU time 0.74 seconds
Started Jul 15 07:00:15 PM PDT 24
Finished Jul 15 07:00:17 PM PDT 24
Peak memory 196084 kb
Host smart-e289e23b-d4d7-4229-807f-1d2e4c47bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050256788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4050256788
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1857077055
Short name T179
Test name
Test status
Simulation time 271093569 ps
CPU time 1.33 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:00:17 PM PDT 24
Peak memory 197176 kb
Host smart-d44fa358-016d-416d-bf06-e1fd13ee833c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857077055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1857077055
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3604487086
Short name T129
Test name
Test status
Simulation time 73828146 ps
CPU time 2.96 seconds
Started Jul 15 07:00:17 PM PDT 24
Finished Jul 15 07:00:20 PM PDT 24
Peak memory 198628 kb
Host smart-50c83e2a-dbd4-455b-90bf-290c180410a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604487086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3604487086
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.786047145
Short name T46
Test name
Test status
Simulation time 134514478 ps
CPU time 0.77 seconds
Started Jul 15 07:00:14 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 214260 kb
Host smart-8e64cbd1-d0d3-461f-b8cd-a7f5761e822f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786047145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.786047145
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2389379453
Short name T605
Test name
Test status
Simulation time 104115832 ps
CPU time 0.75 seconds
Started Jul 15 07:00:16 PM PDT 24
Finished Jul 15 07:00:18 PM PDT 24
Peak memory 195936 kb
Host smart-866ce14d-415c-4597-acde-b6e1b39901c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389379453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2389379453
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.136031916
Short name T11
Test name
Test status
Simulation time 304396699 ps
CPU time 1.25 seconds
Started Jul 15 07:00:20 PM PDT 24
Finished Jul 15 07:00:22 PM PDT 24
Peak memory 196308 kb
Host smart-11290cc0-6680-4d4b-9225-6e685e7aadf1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136031916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.136031916
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.81592893
Short name T294
Test name
Test status
Simulation time 12632212373 ps
CPU time 46.95 seconds
Started Jul 15 07:00:20 PM PDT 24
Finished Jul 15 07:01:07 PM PDT 24
Peak memory 198852 kb
Host smart-d2809c23-962d-45fd-b637-b7d43de569be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81592893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpi
o_stress_all.81592893
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.458147180
Short name T708
Test name
Test status
Simulation time 31070922 ps
CPU time 0.6 seconds
Started Jul 15 07:01:16 PM PDT 24
Finished Jul 15 07:01:17 PM PDT 24
Peak memory 195352 kb
Host smart-0c1e25b1-c530-4bea-a339-55383b515f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458147180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.458147180
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4228382491
Short name T683
Test name
Test status
Simulation time 119366713 ps
CPU time 0.82 seconds
Started Jul 15 07:01:12 PM PDT 24
Finished Jul 15 07:01:13 PM PDT 24
Peak memory 196748 kb
Host smart-615e2849-7c72-4581-b35c-633c0cf431f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228382491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4228382491
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2640902331
Short name T426
Test name
Test status
Simulation time 446665336 ps
CPU time 22.68 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:34 PM PDT 24
Peak memory 197312 kb
Host smart-ce040d5c-7ca3-49a1-8d79-b3f41a6bd646
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640902331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2640902331
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.513027090
Short name T539
Test name
Test status
Simulation time 244651306 ps
CPU time 0.91 seconds
Started Jul 15 07:01:09 PM PDT 24
Finished Jul 15 07:01:10 PM PDT 24
Peak memory 197644 kb
Host smart-f5bd4f5e-703e-462d-9a19-91e987cf41cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513027090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.513027090
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2860143819
Short name T574
Test name
Test status
Simulation time 62576049 ps
CPU time 1.2 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:13 PM PDT 24
Peak memory 196764 kb
Host smart-6e492d65-a3f9-4d63-9184-6c2d10ed44ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860143819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2860143819
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.949260764
Short name T387
Test name
Test status
Simulation time 137844680 ps
CPU time 1.55 seconds
Started Jul 15 07:01:10 PM PDT 24
Finished Jul 15 07:01:12 PM PDT 24
Peak memory 197296 kb
Host smart-9c69a81a-fa27-430a-a4a7-51582d80a05e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949260764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.949260764
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4209759182
Short name T396
Test name
Test status
Simulation time 414159770 ps
CPU time 3.39 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:16 PM PDT 24
Peak memory 197476 kb
Host smart-cbaa43b4-6e79-42e5-b5ec-1d1ee16a1284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209759182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4209759182
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1078543282
Short name T221
Test name
Test status
Simulation time 57605768 ps
CPU time 1.41 seconds
Started Jul 15 07:01:10 PM PDT 24
Finished Jul 15 07:01:12 PM PDT 24
Peak memory 198704 kb
Host smart-27606fcf-c115-4c7e-b43d-b805b11af5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078543282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1078543282
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.436386469
Short name T494
Test name
Test status
Simulation time 73847261 ps
CPU time 1.36 seconds
Started Jul 15 07:01:12 PM PDT 24
Finished Jul 15 07:01:14 PM PDT 24
Peak memory 198700 kb
Host smart-62748c39-1d2e-4cb3-96e9-c32d95795408
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436386469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.436386469
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2060551959
Short name T711
Test name
Test status
Simulation time 130921331 ps
CPU time 1.93 seconds
Started Jul 15 07:01:14 PM PDT 24
Finished Jul 15 07:01:16 PM PDT 24
Peak memory 198628 kb
Host smart-372903a9-4811-4c49-b83c-dddd7720248b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060551959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2060551959
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3008178322
Short name T345
Test name
Test status
Simulation time 45193588 ps
CPU time 1.37 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:01:13 PM PDT 24
Peak memory 197348 kb
Host smart-3ba055d5-6a4a-4e0e-96d6-b723b01823e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008178322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3008178322
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3601648140
Short name T85
Test name
Test status
Simulation time 71270496 ps
CPU time 1.32 seconds
Started Jul 15 07:01:13 PM PDT 24
Finished Jul 15 07:01:15 PM PDT 24
Peak memory 196520 kb
Host smart-afde1aca-0146-4af6-b09b-6412447c95ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601648140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3601648140
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1784347939
Short name T17
Test name
Test status
Simulation time 50476255874 ps
CPU time 165.93 seconds
Started Jul 15 07:01:11 PM PDT 24
Finished Jul 15 07:03:58 PM PDT 24
Peak memory 198832 kb
Host smart-b6bd9d41-5e6e-42da-b6b6-8cdd4bb43fc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784347939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1784347939
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3288119249
Short name T40
Test name
Test status
Simulation time 37329398947 ps
CPU time 1032.68 seconds
Started Jul 15 07:01:19 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 198896 kb
Host smart-6b9efc1c-6501-406b-a624-7a64b8c3dbe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3288119249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3288119249
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3756702935
Short name T572
Test name
Test status
Simulation time 16539496 ps
CPU time 0.57 seconds
Started Jul 15 07:01:18 PM PDT 24
Finished Jul 15 07:01:20 PM PDT 24
Peak memory 194656 kb
Host smart-9fe28241-9a72-40f7-afb3-ce4dc165e548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756702935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3756702935
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.445659634
Short name T391
Test name
Test status
Simulation time 23368303 ps
CPU time 0.64 seconds
Started Jul 15 07:01:16 PM PDT 24
Finished Jul 15 07:01:17 PM PDT 24
Peak memory 195444 kb
Host smart-b2597be4-daf0-4f3f-aae4-d316571a37e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445659634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.445659634
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4114674492
Short name T80
Test name
Test status
Simulation time 836669337 ps
CPU time 9.56 seconds
Started Jul 15 07:01:14 PM PDT 24
Finished Jul 15 07:01:24 PM PDT 24
Peak memory 196228 kb
Host smart-b78c3f53-92b8-4f1b-9333-8ef5e74868eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114674492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4114674492
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1905357202
Short name T447
Test name
Test status
Simulation time 148122097 ps
CPU time 0.89 seconds
Started Jul 15 07:01:20 PM PDT 24
Finished Jul 15 07:01:22 PM PDT 24
Peak memory 197268 kb
Host smart-5e290f17-4fa3-498e-b162-d39be0cdb4ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905357202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1905357202
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3875766814
Short name T151
Test name
Test status
Simulation time 778886811 ps
CPU time 1.41 seconds
Started Jul 15 07:01:20 PM PDT 24
Finished Jul 15 07:01:22 PM PDT 24
Peak memory 197868 kb
Host smart-896b8f59-b7bb-4213-8c9b-a99ed4cc1de3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875766814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3875766814
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1647855595
Short name T446
Test name
Test status
Simulation time 228653685 ps
CPU time 2.44 seconds
Started Jul 15 07:01:16 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 198692 kb
Host smart-ae01fa13-1059-4d27-9c08-db6e762add5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647855595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1647855595
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4198704268
Short name T619
Test name
Test status
Simulation time 160818707 ps
CPU time 1.95 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:27 PM PDT 24
Peak memory 196856 kb
Host smart-968c9a24-a800-4b11-bb55-cca09f4ea364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198704268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4198704268
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2420303539
Short name T193
Test name
Test status
Simulation time 150861811 ps
CPU time 0.89 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:25 PM PDT 24
Peak memory 196832 kb
Host smart-75a0d99a-c082-4e41-93e5-06c6c6a0f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420303539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2420303539
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2358558501
Short name T430
Test name
Test status
Simulation time 53623989 ps
CPU time 1.02 seconds
Started Jul 15 07:01:16 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 196468 kb
Host smart-90456554-5077-41ee-8a5e-1717f4a4b370
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358558501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2358558501
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1867913675
Short name T331
Test name
Test status
Simulation time 3343855607 ps
CPU time 4.24 seconds
Started Jul 15 07:01:18 PM PDT 24
Finished Jul 15 07:01:23 PM PDT 24
Peak memory 198756 kb
Host smart-ad818dde-4d5c-49a1-ad8f-c1dd75980c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867913675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1867913675
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2769946059
Short name T398
Test name
Test status
Simulation time 33251577 ps
CPU time 0.96 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 196272 kb
Host smart-c8671c70-d619-4e56-b2c1-19cf7dcfe54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769946059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2769946059
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.744002309
Short name T146
Test name
Test status
Simulation time 97570695 ps
CPU time 0.95 seconds
Started Jul 15 07:01:16 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 196408 kb
Host smart-db48f84a-6f5c-4e20-9c38-43f262135ceb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744002309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.744002309
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4222374289
Short name T554
Test name
Test status
Simulation time 7158660092 ps
CPU time 186.49 seconds
Started Jul 15 07:01:20 PM PDT 24
Finished Jul 15 07:04:28 PM PDT 24
Peak memory 198784 kb
Host smart-099626e6-db64-441f-b6e8-c73287167a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222374289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4222374289
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2715458289
Short name T609
Test name
Test status
Simulation time 13976895648 ps
CPU time 219.32 seconds
Started Jul 15 07:01:16 PM PDT 24
Finished Jul 15 07:04:56 PM PDT 24
Peak memory 198912 kb
Host smart-f3761326-f150-436b-beae-a6c493d73c9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2715458289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2715458289
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.310415109
Short name T48
Test name
Test status
Simulation time 14828698 ps
CPU time 0.56 seconds
Started Jul 15 07:01:19 PM PDT 24
Finished Jul 15 07:01:20 PM PDT 24
Peak memory 194904 kb
Host smart-4df838af-77bf-43e5-ac88-2a2403b1af4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310415109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.310415109
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1387923709
Short name T306
Test name
Test status
Simulation time 80278308 ps
CPU time 0.72 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 195508 kb
Host smart-f143cb51-fd5c-40bc-bbc3-3a74fd4993d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387923709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1387923709
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3219021984
Short name T269
Test name
Test status
Simulation time 317651206 ps
CPU time 5.1 seconds
Started Jul 15 07:01:20 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 196696 kb
Host smart-c499e6e1-5cdb-4e70-a79a-5705196a80da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219021984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3219021984
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.4285301230
Short name T4
Test name
Test status
Simulation time 95403376 ps
CPU time 1.09 seconds
Started Jul 15 07:01:15 PM PDT 24
Finished Jul 15 07:01:17 PM PDT 24
Peak memory 197044 kb
Host smart-c7ee718c-d04a-40af-a7df-af58f1154cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285301230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4285301230
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.4234013388
Short name T64
Test name
Test status
Simulation time 33727259 ps
CPU time 0.89 seconds
Started Jul 15 07:01:18 PM PDT 24
Finished Jul 15 07:01:20 PM PDT 24
Peak memory 196624 kb
Host smart-cb073bd0-e128-478e-bbb2-d496d1f16603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234013388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.4234013388
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2399102702
Short name T500
Test name
Test status
Simulation time 174435828 ps
CPU time 1.97 seconds
Started Jul 15 07:01:19 PM PDT 24
Finished Jul 15 07:01:22 PM PDT 24
Peak memory 196992 kb
Host smart-13acc268-ba43-4877-b28c-f99f56a8b272
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399102702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2399102702
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.832101181
Short name T713
Test name
Test status
Simulation time 102491321 ps
CPU time 3.13 seconds
Started Jul 15 07:01:18 PM PDT 24
Finished Jul 15 07:01:22 PM PDT 24
Peak memory 198720 kb
Host smart-51b951d1-9c71-4dea-9de0-3e951ceb17c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832101181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
832101181
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1455827775
Short name T137
Test name
Test status
Simulation time 30906023 ps
CPU time 0.87 seconds
Started Jul 15 07:01:17 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 197284 kb
Host smart-aa8fb928-f553-4d3f-b78e-9ff24caa90ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455827775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1455827775
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1005191948
Short name T353
Test name
Test status
Simulation time 41703286 ps
CPU time 0.97 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 196484 kb
Host smart-aaa80bcc-5584-46f1-859d-40b72c530f97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005191948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1005191948
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.125227434
Short name T245
Test name
Test status
Simulation time 238018234 ps
CPU time 1.61 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:27 PM PDT 24
Peak memory 198648 kb
Host smart-fa7911d9-3e2a-4104-99e4-2b874e3d77f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125227434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.125227434
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3558866846
Short name T621
Test name
Test status
Simulation time 124604453 ps
CPU time 1.11 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:27 PM PDT 24
Peak memory 196216 kb
Host smart-1a556d5b-981e-4714-93dd-b30e22ad84d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558866846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3558866846
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2615770004
Short name T615
Test name
Test status
Simulation time 53007266 ps
CPU time 1.42 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:27 PM PDT 24
Peak memory 197452 kb
Host smart-d6573b70-a8ba-4c60-b7b5-e43d6c938395
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615770004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2615770004
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3766238865
Short name T348
Test name
Test status
Simulation time 18416625508 ps
CPU time 120.65 seconds
Started Jul 15 07:01:17 PM PDT 24
Finished Jul 15 07:03:18 PM PDT 24
Peak memory 198792 kb
Host smart-3bd7dc88-c852-4647-a940-2bc4f2cc8949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766238865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3766238865
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.94794435
Short name T676
Test name
Test status
Simulation time 23220594 ps
CPU time 0.56 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 195272 kb
Host smart-99fb0c10-7232-418a-ae97-f94c722cf82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94794435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.94794435
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.337653071
Short name T534
Test name
Test status
Simulation time 88616639 ps
CPU time 0.85 seconds
Started Jul 15 07:01:16 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 197128 kb
Host smart-bb768e0d-310b-4b95-baa8-72911112b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337653071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.337653071
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3932239941
Short name T498
Test name
Test status
Simulation time 120652384 ps
CPU time 6.62 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:30 PM PDT 24
Peak memory 196220 kb
Host smart-a27a74b3-d016-4b10-ba72-0b3e3b1cc533
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932239941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3932239941
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3349739900
Short name T665
Test name
Test status
Simulation time 66173010 ps
CPU time 0.82 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:25 PM PDT 24
Peak memory 197292 kb
Host smart-348587ef-4c06-498b-ac01-4cd7d0d899c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349739900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3349739900
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4269729837
Short name T303
Test name
Test status
Simulation time 177215500 ps
CPU time 1.21 seconds
Started Jul 15 07:01:18 PM PDT 24
Finished Jul 15 07:01:20 PM PDT 24
Peak memory 196548 kb
Host smart-25c8501b-b343-462a-b9a0-c742bee46b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269729837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4269729837
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3662754365
Short name T463
Test name
Test status
Simulation time 162439028 ps
CPU time 3.46 seconds
Started Jul 15 07:01:15 PM PDT 24
Finished Jul 15 07:01:19 PM PDT 24
Peak memory 198732 kb
Host smart-def9393e-6d31-4878-a098-8ad11080a5de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662754365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3662754365
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.138627414
Short name T178
Test name
Test status
Simulation time 88493625 ps
CPU time 2.05 seconds
Started Jul 15 07:01:21 PM PDT 24
Finished Jul 15 07:01:24 PM PDT 24
Peak memory 196872 kb
Host smart-b574b593-057d-46e9-bc56-92e430e44ff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138627414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
138627414
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1349314732
Short name T362
Test name
Test status
Simulation time 31234424 ps
CPU time 1.14 seconds
Started Jul 15 07:01:21 PM PDT 24
Finished Jul 15 07:01:23 PM PDT 24
Peak memory 196632 kb
Host smart-9a1ef44d-6562-442d-b4b1-416b74d4ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349314732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1349314732
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1690725945
Short name T489
Test name
Test status
Simulation time 14111656 ps
CPU time 0.66 seconds
Started Jul 15 07:01:19 PM PDT 24
Finished Jul 15 07:01:21 PM PDT 24
Peak memory 194928 kb
Host smart-2e8b9924-d08b-4b9c-8d24-0f9ae3909e4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690725945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1690725945
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1110695706
Short name T571
Test name
Test status
Simulation time 1104356572 ps
CPU time 4.35 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:29 PM PDT 24
Peak memory 198628 kb
Host smart-df828d95-84de-4824-909d-bc24dcf9d0a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110695706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1110695706
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1098707641
Short name T132
Test name
Test status
Simulation time 40144788 ps
CPU time 0.88 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 195824 kb
Host smart-65491c0e-6180-4a01-9ccd-93ebed5fb7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098707641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1098707641
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3251381843
Short name T86
Test name
Test status
Simulation time 174672237 ps
CPU time 0.93 seconds
Started Jul 15 07:01:15 PM PDT 24
Finished Jul 15 07:01:16 PM PDT 24
Peak memory 196384 kb
Host smart-220dc30b-60b0-4cfa-8b5d-be34d8cc5a12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251381843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3251381843
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4221365654
Short name T30
Test name
Test status
Simulation time 4664891364 ps
CPU time 65.37 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:02:31 PM PDT 24
Peak memory 198744 kb
Host smart-2c484179-e4c1-4a00-8f0a-4262f4b4660c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221365654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4221365654
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1071822986
Short name T662
Test name
Test status
Simulation time 58286837503 ps
CPU time 365.54 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:07:30 PM PDT 24
Peak memory 207164 kb
Host smart-68590ba2-e955-4579-8c50-18032be344c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1071822986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1071822986
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.519344772
Short name T261
Test name
Test status
Simulation time 16860339 ps
CPU time 0.62 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 194820 kb
Host smart-7e45482f-ab5d-472d-8305-9ac4a2cf30a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519344772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.519344772
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.4260241609
Short name T663
Test name
Test status
Simulation time 127763961 ps
CPU time 0.79 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:24 PM PDT 24
Peak memory 196056 kb
Host smart-f2c7a9b1-0efb-41ff-b6ce-fa975d322d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260241609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.4260241609
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.569800466
Short name T140
Test name
Test status
Simulation time 77847753 ps
CPU time 3.97 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 196616 kb
Host smart-ada37e4d-3ab9-4799-be9e-b7efd2625522
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569800466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.569800466
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.170963812
Short name T614
Test name
Test status
Simulation time 314769746 ps
CPU time 0.87 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 196768 kb
Host smart-b0818fc6-05cf-4f06-a064-b6f044a32b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170963812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.170963812
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1149957405
Short name T639
Test name
Test status
Simulation time 416145485 ps
CPU time 1.11 seconds
Started Jul 15 07:01:25 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 196656 kb
Host smart-c88f64a9-546f-419d-885b-3934e5eaae1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149957405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1149957405
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3307515005
Short name T264
Test name
Test status
Simulation time 51800950 ps
CPU time 1.97 seconds
Started Jul 15 07:01:26 PM PDT 24
Finished Jul 15 07:01:29 PM PDT 24
Peak memory 198612 kb
Host smart-e3d61b1d-444a-4db5-a72a-d79574f94eb2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307515005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3307515005
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.4071770064
Short name T231
Test name
Test status
Simulation time 744392405 ps
CPU time 3.25 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 197612 kb
Host smart-5f368752-2be5-40be-ac58-ce42b0e1bc9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071770064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.4071770064
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1889472574
Short name T473
Test name
Test status
Simulation time 24712261 ps
CPU time 0.76 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 196656 kb
Host smart-77eb2df7-3f03-4182-963f-4ab1fadf2885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889472574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1889472574
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1813437726
Short name T78
Test name
Test status
Simulation time 186461901 ps
CPU time 0.94 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:26 PM PDT 24
Peak memory 196684 kb
Host smart-a2d72ac2-daa9-41e4-9ba5-7390e3450540
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813437726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1813437726
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3237989762
Short name T5
Test name
Test status
Simulation time 865371207 ps
CPU time 2.88 seconds
Started Jul 15 07:01:24 PM PDT 24
Finished Jul 15 07:01:29 PM PDT 24
Peak memory 198692 kb
Host smart-876a40eb-ead0-45a6-9b6f-5375c7506a69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237989762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3237989762
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.64732505
Short name T672
Test name
Test status
Simulation time 26067814 ps
CPU time 0.83 seconds
Started Jul 15 07:01:26 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 195960 kb
Host smart-b0c65c0e-8cdc-4b7b-a24c-7b318dc25231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64732505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.64732505
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2806270014
Short name T65
Test name
Test status
Simulation time 34603795 ps
CPU time 0.84 seconds
Started Jul 15 07:01:33 PM PDT 24
Finished Jul 15 07:01:34 PM PDT 24
Peak memory 196040 kb
Host smart-cd4d2739-a277-4ec2-b9ac-4d1104bf0f8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806270014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2806270014
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2522807377
Short name T16
Test name
Test status
Simulation time 3525641974 ps
CPU time 90.72 seconds
Started Jul 15 07:01:26 PM PDT 24
Finished Jul 15 07:02:58 PM PDT 24
Peak memory 198756 kb
Host smart-33b12bd3-0384-489e-a723-591796015f11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522807377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2522807377
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.144378811
Short name T374
Test name
Test status
Simulation time 14848393 ps
CPU time 0.58 seconds
Started Jul 15 07:01:33 PM PDT 24
Finished Jul 15 07:01:35 PM PDT 24
Peak memory 194840 kb
Host smart-67e1f3d0-ca35-4b6e-9947-53936d18ff56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144378811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.144378811
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3164589115
Short name T163
Test name
Test status
Simulation time 72845934 ps
CPU time 0.86 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:24 PM PDT 24
Peak memory 196984 kb
Host smart-4e3e1dfd-38ea-4071-b7f3-3af98ac5aeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164589115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3164589115
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1033248431
Short name T586
Test name
Test status
Simulation time 1014712260 ps
CPU time 7.65 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:47 PM PDT 24
Peak memory 198684 kb
Host smart-06fde93b-b613-4765-af48-1b14e8b34110
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033248431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1033248431
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3903059411
Short name T560
Test name
Test status
Simulation time 422373736 ps
CPU time 1.06 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 198716 kb
Host smart-4413bd52-4adc-4f83-870a-4d16ef7c8fc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903059411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3903059411
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2431819643
Short name T501
Test name
Test status
Simulation time 539169859 ps
CPU time 0.74 seconds
Started Jul 15 07:01:28 PM PDT 24
Finished Jul 15 07:01:29 PM PDT 24
Peak memory 196096 kb
Host smart-0e72bf33-d038-4feb-953c-4493bbc062f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431819643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2431819643
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4265774958
Short name T209
Test name
Test status
Simulation time 236805088 ps
CPU time 2.37 seconds
Started Jul 15 07:01:29 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 198732 kb
Host smart-2c11f25c-a763-4ff4-90a0-16808f33aa2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265774958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4265774958
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3128125857
Short name T271
Test name
Test status
Simulation time 885842768 ps
CPU time 1.9 seconds
Started Jul 15 07:01:32 PM PDT 24
Finished Jul 15 07:01:35 PM PDT 24
Peak memory 197536 kb
Host smart-3e73ca37-fe11-4cbe-8026-b340435d0c45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128125857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3128125857
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3722588739
Short name T350
Test name
Test status
Simulation time 45365082 ps
CPU time 0.86 seconds
Started Jul 15 07:01:27 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 197076 kb
Host smart-18301b21-d38f-40fa-aa5b-0a04922d9a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722588739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3722588739
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2097079247
Short name T687
Test name
Test status
Simulation time 103033187 ps
CPU time 1.02 seconds
Started Jul 15 07:01:25 PM PDT 24
Finished Jul 15 07:01:27 PM PDT 24
Peak memory 196464 kb
Host smart-9b745704-9a89-4d10-9212-5cf72dd8e93c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097079247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2097079247
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.752284810
Short name T627
Test name
Test status
Simulation time 496676937 ps
CPU time 5.65 seconds
Started Jul 15 07:01:27 PM PDT 24
Finished Jul 15 07:01:33 PM PDT 24
Peak memory 198564 kb
Host smart-294c9077-723a-4ee9-92c8-75ed6aad3bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752284810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.752284810
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3768845718
Short name T487
Test name
Test status
Simulation time 50111535 ps
CPU time 0.8 seconds
Started Jul 15 07:01:27 PM PDT 24
Finished Jul 15 07:01:28 PM PDT 24
Peak memory 195592 kb
Host smart-f9098358-af6a-42f6-937a-a991d594f14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768845718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3768845718
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1987301427
Short name T406
Test name
Test status
Simulation time 171897713 ps
CPU time 1.21 seconds
Started Jul 15 07:01:23 PM PDT 24
Finished Jul 15 07:01:24 PM PDT 24
Peak memory 197084 kb
Host smart-569604e2-7b57-49ee-8926-4bbd20f3d6be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987301427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1987301427
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1495841473
Short name T168
Test name
Test status
Simulation time 4854813785 ps
CPU time 31.07 seconds
Started Jul 15 07:01:29 PM PDT 24
Finished Jul 15 07:02:01 PM PDT 24
Peak memory 198636 kb
Host smart-b60c4177-40cd-424b-a982-e010cb11e79b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495841473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1495841473
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1147153806
Short name T467
Test name
Test status
Simulation time 18416622 ps
CPU time 0.58 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:31 PM PDT 24
Peak memory 194644 kb
Host smart-9f40cfc3-fead-49f8-b883-6018cc3317ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147153806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1147153806
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2959283252
Short name T540
Test name
Test status
Simulation time 41244138 ps
CPU time 0.86 seconds
Started Jul 15 07:01:28 PM PDT 24
Finished Jul 15 07:01:29 PM PDT 24
Peak memory 197156 kb
Host smart-fb8cfd08-2ef3-46c8-affc-944a0897f62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959283252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2959283252
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2469932105
Short name T686
Test name
Test status
Simulation time 1291456859 ps
CPU time 20.97 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:59 PM PDT 24
Peak memory 197276 kb
Host smart-1fa6d993-340d-406e-8cc1-810f3e21c8c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469932105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2469932105
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.4671930
Short name T563
Test name
Test status
Simulation time 568434968 ps
CPU time 1.08 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 197040 kb
Host smart-8dc1b7cf-07ab-4a5a-812d-9e526b7207fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4671930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.4671930
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1654446004
Short name T410
Test name
Test status
Simulation time 26809981 ps
CPU time 0.89 seconds
Started Jul 15 07:01:31 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 197204 kb
Host smart-0671d54d-4dd8-4aed-95e1-eec52bf5b68e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654446004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1654446004
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4059339149
Short name T475
Test name
Test status
Simulation time 91512890 ps
CPU time 1.13 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 197544 kb
Host smart-c28603df-2190-47be-949b-79c02b8f8777
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059339149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4059339149
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1868644945
Short name T452
Test name
Test status
Simulation time 577608871 ps
CPU time 2.8 seconds
Started Jul 15 07:01:32 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 198700 kb
Host smart-98ad26f4-3d03-4eaf-a36b-f9581109c89d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868644945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1868644945
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3020233101
Short name T400
Test name
Test status
Simulation time 59874418 ps
CPU time 0.64 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:31 PM PDT 24
Peak memory 194940 kb
Host smart-01953341-a9b5-487c-bd17-b8d0d93c921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020233101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3020233101
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2341833833
Short name T301
Test name
Test status
Simulation time 27176156 ps
CPU time 0.79 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 195996 kb
Host smart-8cc7e2a5-19c4-4e45-820b-5b9997b5a162
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341833833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2341833833
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.505915720
Short name T469
Test name
Test status
Simulation time 85032566 ps
CPU time 1.72 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 198692 kb
Host smart-beabf1b9-8e21-4cbf-989d-ed32cb26b3bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505915720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.505915720
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.706804719
Short name T423
Test name
Test status
Simulation time 40454346 ps
CPU time 1 seconds
Started Jul 15 07:01:32 PM PDT 24
Finished Jul 15 07:01:34 PM PDT 24
Peak memory 197080 kb
Host smart-7b089f3e-dc0f-4354-b48a-6d0370d4efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706804719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.706804719
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2862661532
Short name T653
Test name
Test status
Simulation time 251631781 ps
CPU time 1.21 seconds
Started Jul 15 07:01:28 PM PDT 24
Finished Jul 15 07:01:30 PM PDT 24
Peak memory 197792 kb
Host smart-f00b4d98-de43-4a2e-ac2e-eb710c6c01f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862661532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2862661532
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.800399396
Short name T441
Test name
Test status
Simulation time 14299170854 ps
CPU time 169.79 seconds
Started Jul 15 07:01:29 PM PDT 24
Finished Jul 15 07:04:19 PM PDT 24
Peak memory 198760 kb
Host smart-ef411fb5-f36c-4226-937d-ec872e40340f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800399396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.800399396
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2362360852
Short name T119
Test name
Test status
Simulation time 14283836 ps
CPU time 0.59 seconds
Started Jul 15 07:01:29 PM PDT 24
Finished Jul 15 07:01:30 PM PDT 24
Peak memory 194844 kb
Host smart-539eae27-b39d-4eee-845d-f34413bca341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362360852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2362360852
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.35499252
Short name T171
Test name
Test status
Simulation time 28067726 ps
CPU time 0.72 seconds
Started Jul 15 07:01:28 PM PDT 24
Finished Jul 15 07:01:29 PM PDT 24
Peak memory 195488 kb
Host smart-69c0a4ef-39e6-4dab-afb4-e0deaf0972e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35499252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.35499252
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2037030231
Short name T309
Test name
Test status
Simulation time 349821999 ps
CPU time 4.75 seconds
Started Jul 15 07:01:28 PM PDT 24
Finished Jul 15 07:01:34 PM PDT 24
Peak memory 196508 kb
Host smart-79d194f6-bd68-4152-bce4-67a6ea2092fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037030231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2037030231
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.574607874
Short name T7
Test name
Test status
Simulation time 383878786 ps
CPU time 0.99 seconds
Started Jul 15 07:01:29 PM PDT 24
Finished Jul 15 07:01:31 PM PDT 24
Peak memory 198576 kb
Host smart-7ac513da-d6ed-4531-9ef6-028f643a3461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574607874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.574607874
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1298431550
Short name T465
Test name
Test status
Simulation time 81718124 ps
CPU time 0.89 seconds
Started Jul 15 07:01:28 PM PDT 24
Finished Jul 15 07:01:30 PM PDT 24
Peak memory 196472 kb
Host smart-401b4a6e-b918-4f77-ba32-8783a5d490ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298431550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1298431550
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2036339139
Short name T582
Test name
Test status
Simulation time 191993080 ps
CPU time 1.74 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 197368 kb
Host smart-20a6c952-bf07-40f2-b314-d65d3711aa50
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036339139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2036339139
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.687899409
Short name T369
Test name
Test status
Simulation time 283255129 ps
CPU time 3.12 seconds
Started Jul 15 07:01:28 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 197656 kb
Host smart-424fc732-6132-486d-8f70-3de7d4fd0d68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687899409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
687899409
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1374252258
Short name T177
Test name
Test status
Simulation time 54347779 ps
CPU time 1.16 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 197772 kb
Host smart-3373d8ee-ac74-480e-b888-86146360691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374252258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1374252258
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3063593071
Short name T364
Test name
Test status
Simulation time 40550801 ps
CPU time 1.2 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:40 PM PDT 24
Peak memory 197736 kb
Host smart-63f2b92f-d69c-400d-a7d7-bab134f51c51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063593071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3063593071
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3152682933
Short name T695
Test name
Test status
Simulation time 178330803 ps
CPU time 3.09 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:33 PM PDT 24
Peak memory 198576 kb
Host smart-662de231-d1d4-4578-a75b-87c4390e3fe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152682933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3152682933
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1820684741
Short name T342
Test name
Test status
Simulation time 176074206 ps
CPU time 1.02 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 196192 kb
Host smart-b984390b-e1a5-404e-a57d-635495255b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820684741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1820684741
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.400139079
Short name T318
Test name
Test status
Simulation time 139101356 ps
CPU time 1.35 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 197456 kb
Host smart-0066344b-e02c-415a-988b-43c608af3654
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400139079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.400139079
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1649184692
Short name T649
Test name
Test status
Simulation time 19467484878 ps
CPU time 111.1 seconds
Started Jul 15 07:01:29 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 198748 kb
Host smart-e2cf29bc-163c-4a0c-ba95-036964d97959
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649184692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1649184692
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.513228391
Short name T690
Test name
Test status
Simulation time 13348997 ps
CPU time 0.57 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 194876 kb
Host smart-2ee38879-5637-4723-b581-10fef095d02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513228391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.513228391
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2838349808
Short name T157
Test name
Test status
Simulation time 64388009 ps
CPU time 0.72 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:40 PM PDT 24
Peak memory 195924 kb
Host smart-e83b5834-9f25-4679-86b9-c61168d90dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838349808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2838349808
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2100825195
Short name T381
Test name
Test status
Simulation time 221372215 ps
CPU time 3.52 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:40 PM PDT 24
Peak memory 196140 kb
Host smart-bb65dcab-dc8f-48bc-915c-4f1765f8a0a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100825195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2100825195
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1653417731
Short name T130
Test name
Test status
Simulation time 339688093 ps
CPU time 0.93 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 197180 kb
Host smart-cf9bf540-8b5c-4c0f-8af7-6b0e6111c67a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653417731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1653417731
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.904676001
Short name T334
Test name
Test status
Simulation time 58884829 ps
CPU time 1.14 seconds
Started Jul 15 07:01:32 PM PDT 24
Finished Jul 15 07:01:34 PM PDT 24
Peak memory 196840 kb
Host smart-ee3c3a64-181b-40d5-aaea-9e44531812a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904676001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.904676001
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.692952369
Short name T474
Test name
Test status
Simulation time 140528311 ps
CPU time 1.54 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 197508 kb
Host smart-e379b1ef-7028-4035-88b4-7767e667ade7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692952369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.692952369
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.451626106
Short name T618
Test name
Test status
Simulation time 380254506 ps
CPU time 3.17 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:39 PM PDT 24
Peak memory 198704 kb
Host smart-4420c024-2c20-4389-9b81-d0e9177d4094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451626106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
451626106
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.4089483201
Short name T340
Test name
Test status
Simulation time 46487296 ps
CPU time 1 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 196648 kb
Host smart-4758c524-3579-4f20-9ea2-75660c73be76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089483201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.4089483201
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2172350998
Short name T302
Test name
Test status
Simulation time 41376771 ps
CPU time 1.06 seconds
Started Jul 15 07:01:31 PM PDT 24
Finished Jul 15 07:01:33 PM PDT 24
Peak memory 196752 kb
Host smart-575b4d0e-fdc7-4e42-9d93-456213529112
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172350998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2172350998
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3604620875
Short name T167
Test name
Test status
Simulation time 121456447 ps
CPU time 1.67 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 198612 kb
Host smart-b1de49e1-603e-4999-8d00-6b92b68dc85e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604620875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3604620875
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3348204740
Short name T562
Test name
Test status
Simulation time 317920015 ps
CPU time 1.15 seconds
Started Jul 15 07:01:30 PM PDT 24
Finished Jul 15 07:01:31 PM PDT 24
Peak memory 197188 kb
Host smart-9f7d644c-47c1-428a-b158-85c61b06d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348204740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3348204740
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1828292933
Short name T371
Test name
Test status
Simulation time 30179435 ps
CPU time 1 seconds
Started Jul 15 07:01:32 PM PDT 24
Finished Jul 15 07:01:34 PM PDT 24
Peak memory 196468 kb
Host smart-89244ba6-f4e8-44b6-ba26-28bf75b86526
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828292933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1828292933
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1329487816
Short name T622
Test name
Test status
Simulation time 13456618388 ps
CPU time 158.2 seconds
Started Jul 15 07:01:33 PM PDT 24
Finished Jul 15 07:04:12 PM PDT 24
Peak memory 198784 kb
Host smart-aecb298d-5db3-46cc-a482-34ccc1871aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329487816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1329487816
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2064327993
Short name T481
Test name
Test status
Simulation time 68081590483 ps
CPU time 287.64 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:06:24 PM PDT 24
Peak memory 207132 kb
Host smart-c3de9130-f394-4a05-a795-51fd9463a413
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2064327993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2064327993
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1004150649
Short name T308
Test name
Test status
Simulation time 28260681 ps
CPU time 0.54 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 195324 kb
Host smart-9a099c67-820c-48fd-bf2a-f91b4ba614b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004150649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1004150649
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3536010449
Short name T417
Test name
Test status
Simulation time 37294842 ps
CPU time 0.84 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 197096 kb
Host smart-c3d7418f-2f5f-4d12-a950-75f9e39eceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536010449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3536010449
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2498795332
Short name T550
Test name
Test status
Simulation time 2902018349 ps
CPU time 12.77 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 198780 kb
Host smart-af2156a7-3d6e-468c-b9ae-f4e315f14e98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498795332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2498795332
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3081328532
Short name T19
Test name
Test status
Simulation time 94493549 ps
CPU time 0.69 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 195216 kb
Host smart-86e91fae-2a2a-41e1-885e-c9412fda1a89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081328532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3081328532
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1006405527
Short name T429
Test name
Test status
Simulation time 40368382 ps
CPU time 0.69 seconds
Started Jul 15 07:01:32 PM PDT 24
Finished Jul 15 07:01:34 PM PDT 24
Peak memory 194912 kb
Host smart-bec4a2e1-dc34-4c24-bf6e-38da0fd678d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006405527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1006405527
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1026664916
Short name T710
Test name
Test status
Simulation time 40654518 ps
CPU time 1.12 seconds
Started Jul 15 07:01:33 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 196748 kb
Host smart-171862a4-9e82-4ccc-b33b-60124047b086
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026664916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1026664916
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.426336070
Short name T637
Test name
Test status
Simulation time 51201846 ps
CPU time 0.92 seconds
Started Jul 15 07:01:33 PM PDT 24
Finished Jul 15 07:01:35 PM PDT 24
Peak memory 197008 kb
Host smart-7786055d-3bc7-480c-a8b6-8aa78ba2ba24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426336070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
426336070
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.890064630
Short name T311
Test name
Test status
Simulation time 39758466 ps
CPU time 1.33 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 196496 kb
Host smart-39442528-d16d-4dd2-bb59-803b70f9a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890064630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.890064630
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3279501450
Short name T497
Test name
Test status
Simulation time 67663882 ps
CPU time 1.33 seconds
Started Jul 15 07:01:33 PM PDT 24
Finished Jul 15 07:01:35 PM PDT 24
Peak memory 197692 kb
Host smart-e2b759df-3021-4657-b479-8666caa11436
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279501450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3279501450
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2288359431
Short name T322
Test name
Test status
Simulation time 718499566 ps
CPU time 5.7 seconds
Started Jul 15 07:01:33 PM PDT 24
Finished Jul 15 07:01:39 PM PDT 24
Peak memory 198408 kb
Host smart-b693aabb-e1e1-4a99-ad98-4142eb0e7b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288359431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2288359431
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1901381075
Short name T526
Test name
Test status
Simulation time 21858892 ps
CPU time 0.73 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 194880 kb
Host smart-cc34fd9f-7b3b-445e-9dda-3c27834ce977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901381075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1901381075
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1700670144
Short name T419
Test name
Test status
Simulation time 40414538 ps
CPU time 1.21 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 196176 kb
Host smart-33a284b0-9606-43e6-a48e-c91588ef26ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700670144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1700670144
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3877872507
Short name T242
Test name
Test status
Simulation time 4158032389 ps
CPU time 110.97 seconds
Started Jul 15 07:01:36 PM PDT 24
Finished Jul 15 07:03:28 PM PDT 24
Peak memory 198760 kb
Host smart-c9c5a4d1-c0fd-40dc-a4dc-064fb16b2d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877872507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3877872507
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1774104433
Short name T437
Test name
Test status
Simulation time 64656265985 ps
CPU time 1621.02 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:28:40 PM PDT 24
Peak memory 198736 kb
Host smart-2ff5fc93-2010-44c3-8f0a-0d07f57aa2cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1774104433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1774104433
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2761274647
Short name T172
Test name
Test status
Simulation time 48150681 ps
CPU time 0.58 seconds
Started Jul 15 07:00:23 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 194892 kb
Host smart-e5775342-6c15-483c-a4ce-792f9c8a2ec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761274647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2761274647
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2225007767
Short name T191
Test name
Test status
Simulation time 241791026 ps
CPU time 0.91 seconds
Started Jul 15 07:00:23 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 196124 kb
Host smart-343e8d37-552d-4240-91c4-329ebe7c5853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225007767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2225007767
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1328573296
Short name T604
Test name
Test status
Simulation time 669340785 ps
CPU time 8.72 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:00:30 PM PDT 24
Peak memory 197288 kb
Host smart-f4398195-ea2b-48ff-8dc6-a62062603a04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328573296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1328573296
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1685482719
Short name T445
Test name
Test status
Simulation time 80445197 ps
CPU time 0.64 seconds
Started Jul 15 07:00:20 PM PDT 24
Finished Jul 15 07:00:21 PM PDT 24
Peak memory 195960 kb
Host smart-dcbfa749-a14a-4cd9-b273-091870867803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685482719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1685482719
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1138088999
Short name T503
Test name
Test status
Simulation time 99750653 ps
CPU time 0.75 seconds
Started Jul 15 07:00:22 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 196172 kb
Host smart-f05b9f8c-d557-4509-bf96-94abbe7a344e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138088999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1138088999
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1224332013
Short name T197
Test name
Test status
Simulation time 25100920 ps
CPU time 1.13 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:00:22 PM PDT 24
Peak memory 197760 kb
Host smart-e109e9b5-284d-4a11-81d6-3942b681a4bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224332013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1224332013
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2571502031
Short name T214
Test name
Test status
Simulation time 185319442 ps
CPU time 1.24 seconds
Started Jul 15 07:00:20 PM PDT 24
Finished Jul 15 07:00:22 PM PDT 24
Peak memory 196172 kb
Host smart-045abf0d-d27e-4b5d-9a76-5cf6a3c47c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571502031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2571502031
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.578618287
Short name T681
Test name
Test status
Simulation time 86652000 ps
CPU time 0.75 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:00:22 PM PDT 24
Peak memory 196692 kb
Host smart-c288980d-d6de-4522-ad1e-4554b18757a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578618287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.578618287
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3713724113
Short name T327
Test name
Test status
Simulation time 49753086 ps
CPU time 0.72 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 195984 kb
Host smart-2e74b9a5-efeb-4c63-9bdb-33a408c704b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713724113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3713724113
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_smoke.2847884237
Short name T205
Test name
Test status
Simulation time 40290598 ps
CPU time 1.12 seconds
Started Jul 15 07:00:18 PM PDT 24
Finished Jul 15 07:00:20 PM PDT 24
Peak memory 196912 kb
Host smart-10c14bb8-ee99-4d9a-80d5-002a191308e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847884237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2847884237
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2943996331
Short name T155
Test name
Test status
Simulation time 206080514 ps
CPU time 1 seconds
Started Jul 15 07:00:24 PM PDT 24
Finished Jul 15 07:00:25 PM PDT 24
Peak memory 197196 kb
Host smart-0069597d-fbb2-4798-9c62-d6d97454f1e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943996331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2943996331
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.458581470
Short name T6
Test name
Test status
Simulation time 59143193506 ps
CPU time 193.08 seconds
Started Jul 15 07:00:22 PM PDT 24
Finished Jul 15 07:03:36 PM PDT 24
Peak memory 198816 kb
Host smart-4a76984f-e6b4-4dd7-b595-861f4d60eb23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458581470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.458581470
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2069973432
Short name T502
Test name
Test status
Simulation time 216380254869 ps
CPU time 561.19 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:09:43 PM PDT 24
Peak memory 198924 kb
Host smart-6815ee01-b3e0-4a51-bcac-e79537eaf2e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2069973432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2069973432
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3287297354
Short name T531
Test name
Test status
Simulation time 16440994 ps
CPU time 0.59 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 194472 kb
Host smart-200948b1-3998-4174-a700-75c88be92a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287297354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3287297354
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1436906280
Short name T646
Test name
Test status
Simulation time 95205165 ps
CPU time 0.71 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 194828 kb
Host smart-8ca451f8-1085-40be-9fd1-2e993eb6b81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436906280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1436906280
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.957103896
Short name T127
Test name
Test status
Simulation time 463241534 ps
CPU time 14.28 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:51 PM PDT 24
Peak memory 198596 kb
Host smart-2ac7f615-bac6-4b99-b724-9baa720b489e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957103896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.957103896
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.613018186
Short name T26
Test name
Test status
Simulation time 104817068 ps
CPU time 0.82 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 196472 kb
Host smart-467b9e7e-1b47-4d7e-ae2b-2d580bf8e419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613018186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.613018186
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3718351510
Short name T344
Test name
Test status
Simulation time 282799148 ps
CPU time 1.33 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 197140 kb
Host smart-750c0d6e-a4a3-4c05-894c-cf53b4379811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718351510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3718351510
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4005774765
Short name T700
Test name
Test status
Simulation time 105156536 ps
CPU time 2.04 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 198608 kb
Host smart-21b8ece2-e0ac-481f-9c21-00119237a9fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005774765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4005774765
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2175091449
Short name T385
Test name
Test status
Simulation time 127288558 ps
CPU time 2.71 seconds
Started Jul 15 07:01:36 PM PDT 24
Finished Jul 15 07:01:40 PM PDT 24
Peak memory 197148 kb
Host smart-2d3e941f-6de4-4fe9-bb18-f4f8c9169d92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175091449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2175091449
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3789767741
Short name T149
Test name
Test status
Simulation time 49457382 ps
CPU time 0.78 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 196096 kb
Host smart-0b207a76-5d2e-40b9-afe6-4705b4b1bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789767741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3789767741
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2081348574
Short name T316
Test name
Test status
Simulation time 33091825 ps
CPU time 1.26 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 197724 kb
Host smart-48740da6-e57a-4cbf-88f4-03a91f5af477
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081348574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2081348574
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4223362815
Short name T524
Test name
Test status
Simulation time 199345397 ps
CPU time 1.59 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 198460 kb
Host smart-62d77b91-3b79-469f-aa68-77ec59f67f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223362815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4223362815
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.28570006
Short name T508
Test name
Test status
Simulation time 110950466 ps
CPU time 1.05 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 196236 kb
Host smart-cfa91157-4d6f-4521-b095-c5e68f4f4850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28570006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.28570006
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1223310502
Short name T356
Test name
Test status
Simulation time 36577697 ps
CPU time 1.14 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 196436 kb
Host smart-8162254c-9892-45eb-8ae0-6919cd112e0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223310502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1223310502
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2811117610
Short name T428
Test name
Test status
Simulation time 8930226517 ps
CPU time 62.53 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:02:39 PM PDT 24
Peak memory 198436 kb
Host smart-e748528e-8b15-47cb-84fa-b4c40699910d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811117610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2811117610
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1194428394
Short name T645
Test name
Test status
Simulation time 69623160504 ps
CPU time 311.27 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 198184 kb
Host smart-116ba9da-f5ef-4b80-adf6-3e0f03bf47fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1194428394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1194428394
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.930880095
Short name T346
Test name
Test status
Simulation time 11115906 ps
CPU time 0.58 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 194656 kb
Host smart-9e38a288-3776-400f-8a7b-8093b3b87af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930880095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.930880095
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.159030233
Short name T397
Test name
Test status
Simulation time 99460007 ps
CPU time 0.83 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 197016 kb
Host smart-7a3fb20b-9e5c-45cc-b36b-ed6fc3ace5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159030233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.159030233
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1146022900
Short name T210
Test name
Test status
Simulation time 632222569 ps
CPU time 16.36 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:55 PM PDT 24
Peak memory 197432 kb
Host smart-9fa6a86e-3c92-4e1a-b5ec-06a2bc818974
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146022900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1146022900
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.286024140
Short name T354
Test name
Test status
Simulation time 312740856 ps
CPU time 0.95 seconds
Started Jul 15 07:01:40 PM PDT 24
Finished Jul 15 07:01:42 PM PDT 24
Peak memory 197824 kb
Host smart-972b0691-ff09-4e32-a48c-1b43b1b905df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286024140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.286024140
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.343425144
Short name T281
Test name
Test status
Simulation time 20656658 ps
CPU time 0.64 seconds
Started Jul 15 07:01:31 PM PDT 24
Finished Jul 15 07:01:32 PM PDT 24
Peak memory 194940 kb
Host smart-7dc11f18-5429-48d5-961c-5e76c365564d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343425144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.343425144
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1765952620
Short name T694
Test name
Test status
Simulation time 360038161 ps
CPU time 3.85 seconds
Started Jul 15 07:01:42 PM PDT 24
Finished Jul 15 07:01:46 PM PDT 24
Peak memory 198680 kb
Host smart-4d3657e5-72c3-438c-bb38-e832181b8cfe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765952620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1765952620
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1647333678
Short name T34
Test name
Test status
Simulation time 375488372 ps
CPU time 2.97 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 197580 kb
Host smart-b3e78ff4-ef25-4868-b4fc-c29b2ef4010f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647333678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1647333678
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.244497925
Short name T701
Test name
Test status
Simulation time 63736687 ps
CPU time 1.22 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 196736 kb
Host smart-cdce4365-df5e-440e-bdc4-658fbde6d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244497925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.244497925
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.217136462
Short name T153
Test name
Test status
Simulation time 129574777 ps
CPU time 0.89 seconds
Started Jul 15 07:01:34 PM PDT 24
Finished Jul 15 07:01:37 PM PDT 24
Peak memory 197220 kb
Host smart-a71f87f5-cad8-4b46-812f-fcd225aa5b19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217136462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.217136462
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3066502046
Short name T68
Test name
Test status
Simulation time 48368219 ps
CPU time 2.39 seconds
Started Jul 15 07:01:42 PM PDT 24
Finished Jul 15 07:01:44 PM PDT 24
Peak memory 198600 kb
Host smart-0712fdee-2b1e-4d57-80f0-2dab446419f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066502046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3066502046
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.610133753
Short name T28
Test name
Test status
Simulation time 384781254 ps
CPU time 1.16 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 197076 kb
Host smart-ffece477-ef5f-476d-8bbf-60a67013b360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610133753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.610133753
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1177484397
Short name T420
Test name
Test status
Simulation time 44483681 ps
CPU time 0.92 seconds
Started Jul 15 07:01:35 PM PDT 24
Finished Jul 15 07:01:38 PM PDT 24
Peak memory 196168 kb
Host smart-4a314aa8-3da4-4f33-8c21-0d7da404ed56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177484397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1177484397
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1423582166
Short name T546
Test name
Test status
Simulation time 9483433602 ps
CPU time 120.27 seconds
Started Jul 15 07:01:42 PM PDT 24
Finished Jul 15 07:03:42 PM PDT 24
Peak memory 198800 kb
Host smart-18e042ae-8210-4255-97f3-1efa0d9ecd5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423582166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1423582166
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2942251461
Short name T76
Test name
Test status
Simulation time 12432554 ps
CPU time 0.57 seconds
Started Jul 15 07:01:46 PM PDT 24
Finished Jul 15 07:01:47 PM PDT 24
Peak memory 194640 kb
Host smart-1313eff1-f22a-4e5c-ba2c-231dac055806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942251461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2942251461
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1056764248
Short name T702
Test name
Test status
Simulation time 22002334 ps
CPU time 0.87 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 196668 kb
Host smart-b90e0d20-702d-4d81-9715-5ecf983a5c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056764248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1056764248
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1458286755
Short name T482
Test name
Test status
Simulation time 304489819 ps
CPU time 15.53 seconds
Started Jul 15 07:01:40 PM PDT 24
Finished Jul 15 07:01:56 PM PDT 24
Peak memory 196200 kb
Host smart-f54400c8-5134-4d63-8fe8-438a7f993801
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458286755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1458286755
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2349249793
Short name T21
Test name
Test status
Simulation time 387050008 ps
CPU time 1.07 seconds
Started Jul 15 07:01:41 PM PDT 24
Finished Jul 15 07:01:42 PM PDT 24
Peak memory 197048 kb
Host smart-c69c318d-85c3-4929-91fe-224fc7fa60eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349249793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2349249793
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.4060910278
Short name T477
Test name
Test status
Simulation time 52065055 ps
CPU time 0.95 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 197224 kb
Host smart-0ce646da-efb6-4c17-9add-5ae96dd58e54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060910278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.4060910278
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1021009403
Short name T234
Test name
Test status
Simulation time 140383214 ps
CPU time 0.97 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 196776 kb
Host smart-d4e67fd2-d9cd-43c0-9e6e-d937d9e191b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021009403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1021009403
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.884286566
Short name T633
Test name
Test status
Simulation time 62667642 ps
CPU time 1.24 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 197464 kb
Host smart-f0180646-d5b0-46cd-8e9b-5ae0b9d765d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884286566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
884286566
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2419858416
Short name T236
Test name
Test status
Simulation time 89217389 ps
CPU time 0.72 seconds
Started Jul 15 07:01:39 PM PDT 24
Finished Jul 15 07:01:41 PM PDT 24
Peak memory 196716 kb
Host smart-92f918b7-153e-40df-b5cb-456524d6a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419858416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2419858416
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4130900929
Short name T321
Test name
Test status
Simulation time 24784211 ps
CPU time 0.88 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:40 PM PDT 24
Peak memory 197200 kb
Host smart-2f9a6e36-1b04-4b24-80b3-d1bb50138906
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130900929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4130900929
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3473778591
Short name T3
Test name
Test status
Simulation time 2369655520 ps
CPU time 4.6 seconds
Started Jul 15 07:01:43 PM PDT 24
Finished Jul 15 07:01:48 PM PDT 24
Peak memory 198704 kb
Host smart-820be393-40bd-4150-b273-932841c52e77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473778591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3473778591
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.489133689
Short name T330
Test name
Test status
Simulation time 185035687 ps
CPU time 0.94 seconds
Started Jul 15 07:01:38 PM PDT 24
Finished Jul 15 07:01:39 PM PDT 24
Peak memory 197088 kb
Host smart-3d08ca39-37c0-4e14-b2f3-2c608ed338d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489133689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.489133689
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2040196616
Short name T486
Test name
Test status
Simulation time 58106360 ps
CPU time 1.08 seconds
Started Jul 15 07:01:42 PM PDT 24
Finished Jul 15 07:01:44 PM PDT 24
Peak memory 196504 kb
Host smart-8092fb80-a5bf-4205-ba00-5a076033d35a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040196616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2040196616
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2609936974
Short name T10
Test name
Test status
Simulation time 15873147172 ps
CPU time 170.35 seconds
Started Jul 15 07:01:48 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 198760 kb
Host smart-13d464df-9ade-4dde-ba52-75a9a4a5586b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609936974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2609936974
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.255493200
Short name T207
Test name
Test status
Simulation time 31265108 ps
CPU time 0.56 seconds
Started Jul 15 07:01:46 PM PDT 24
Finished Jul 15 07:01:47 PM PDT 24
Peak memory 196332 kb
Host smart-4d7fe477-9eea-4d0b-a39f-02f71591f14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255493200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.255493200
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3753405941
Short name T395
Test name
Test status
Simulation time 28840960 ps
CPU time 0.82 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:01:46 PM PDT 24
Peak memory 197936 kb
Host smart-7d9ea40b-2906-49fe-ae2f-128f436178b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753405941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3753405941
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3859391594
Short name T228
Test name
Test status
Simulation time 3109190765 ps
CPU time 21.16 seconds
Started Jul 15 07:01:46 PM PDT 24
Finished Jul 15 07:02:08 PM PDT 24
Peak memory 197680 kb
Host smart-e578c36a-565d-4100-a2e8-8571977ac143
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859391594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3859391594
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2058757062
Short name T58
Test name
Test status
Simulation time 66127711 ps
CPU time 0.64 seconds
Started Jul 15 07:01:48 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 195160 kb
Host smart-9787e315-df7b-4726-a9b3-0b293b8354ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058757062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2058757062
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1845518708
Short name T698
Test name
Test status
Simulation time 147494470 ps
CPU time 1.09 seconds
Started Jul 15 07:01:46 PM PDT 24
Finished Jul 15 07:01:48 PM PDT 24
Peak memory 196496 kb
Host smart-92bd1d1b-dd24-45d9-8020-dec554cfd7e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845518708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1845518708
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3114685497
Short name T434
Test name
Test status
Simulation time 89522375 ps
CPU time 3.7 seconds
Started Jul 15 07:01:47 PM PDT 24
Finished Jul 15 07:01:51 PM PDT 24
Peak memory 198800 kb
Host smart-27d68bf3-7bd1-468c-8ad5-fc9047ac0444
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114685497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3114685497
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2659114827
Short name T263
Test name
Test status
Simulation time 677478867 ps
CPU time 3.36 seconds
Started Jul 15 07:01:44 PM PDT 24
Finished Jul 15 07:01:48 PM PDT 24
Peak memory 196616 kb
Host smart-9f7952e8-86fd-48ec-bc32-15c282a07cec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659114827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2659114827
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1632741834
Short name T451
Test name
Test status
Simulation time 62834253 ps
CPU time 1.33 seconds
Started Jul 15 07:01:47 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 197764 kb
Host smart-bbd30a7c-ae99-400c-817b-a43b60ebcdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632741834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1632741834
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1247675543
Short name T461
Test name
Test status
Simulation time 286339763 ps
CPU time 1.23 seconds
Started Jul 15 07:01:47 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 196532 kb
Host smart-6240152e-ad9f-4021-b371-657d455042cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247675543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1247675543
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2695323258
Short name T532
Test name
Test status
Simulation time 1719073862 ps
CPU time 6.27 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:01:52 PM PDT 24
Peak memory 198652 kb
Host smart-6359ed09-cb0d-44b8-8fcd-54dd3cc9dd64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695323258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2695323258
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.67346118
Short name T468
Test name
Test status
Simulation time 68691401 ps
CPU time 0.84 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:01:47 PM PDT 24
Peak memory 195872 kb
Host smart-9cfe2f99-4eeb-4983-908d-2dc8941250b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67346118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.67346118
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2233979012
Short name T204
Test name
Test status
Simulation time 42625121 ps
CPU time 0.87 seconds
Started Jul 15 07:01:47 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 197036 kb
Host smart-ae1f14cf-2978-44cc-99ae-e25bb59a806a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233979012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2233979012
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3919670514
Short name T641
Test name
Test status
Simulation time 4488100887 ps
CPU time 54.86 seconds
Started Jul 15 07:01:48 PM PDT 24
Finished Jul 15 07:02:44 PM PDT 24
Peak memory 198732 kb
Host smart-7391470c-cb83-4098-841b-dcc906b8163d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919670514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3919670514
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2893663089
Short name T393
Test name
Test status
Simulation time 16133706 ps
CPU time 0.58 seconds
Started Jul 15 07:01:52 PM PDT 24
Finished Jul 15 07:01:54 PM PDT 24
Peak memory 194600 kb
Host smart-c11d0b9c-fd67-472b-8422-58e9b9587afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893663089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2893663089
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2340027675
Short name T720
Test name
Test status
Simulation time 98669650 ps
CPU time 0.78 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:01:46 PM PDT 24
Peak memory 196440 kb
Host smart-bd57b767-7209-4613-bc88-98b7e01692b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340027675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2340027675
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2612765980
Short name T33
Test name
Test status
Simulation time 1623958267 ps
CPU time 20.33 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:02:06 PM PDT 24
Peak memory 196968 kb
Host smart-e17f3ccd-6a34-49db-b5a1-a754fe2d9d0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612765980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2612765980
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.684914291
Short name T389
Test name
Test status
Simulation time 129684251 ps
CPU time 0.79 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:01:54 PM PDT 24
Peak memory 196456 kb
Host smart-399e6f5e-a82b-49e5-b8d9-48efeda04f56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684914291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.684914291
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.786388155
Short name T659
Test name
Test status
Simulation time 1245141680 ps
CPU time 1.25 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:01:47 PM PDT 24
Peak memory 196472 kb
Host smart-82ba6459-f8c3-48df-bf4d-1fbb0e4cbc6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786388155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.786388155
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3951328029
Short name T450
Test name
Test status
Simulation time 30206707 ps
CPU time 1.25 seconds
Started Jul 15 07:01:46 PM PDT 24
Finished Jul 15 07:01:48 PM PDT 24
Peak memory 198676 kb
Host smart-c39062cf-c7e5-43ff-89c5-0a031dc803c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951328029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3951328029
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1919430040
Short name T289
Test name
Test status
Simulation time 1937462168 ps
CPU time 3.13 seconds
Started Jul 15 07:01:48 PM PDT 24
Finished Jul 15 07:01:51 PM PDT 24
Peak memory 198680 kb
Host smart-b945cc7c-ad1d-4e37-9ad6-b78f9de127ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919430040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1919430040
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3280673015
Short name T632
Test name
Test status
Simulation time 358612130 ps
CPU time 1.29 seconds
Started Jul 15 07:01:46 PM PDT 24
Finished Jul 15 07:01:48 PM PDT 24
Peak memory 197356 kb
Host smart-ee777ca1-984c-41a7-a613-d108e75c97db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280673015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3280673015
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1219424515
Short name T347
Test name
Test status
Simulation time 354887391 ps
CPU time 1.13 seconds
Started Jul 15 07:01:47 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 196824 kb
Host smart-658aabd0-9c0b-4e7c-ae9b-eb5b7d33ce3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219424515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1219424515
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3926250653
Short name T366
Test name
Test status
Simulation time 1094928488 ps
CPU time 4.4 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:01:50 PM PDT 24
Peak memory 198656 kb
Host smart-ea98b34a-3ca5-4e9a-9c14-aa0675db7ce6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926250653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3926250653
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.146244814
Short name T165
Test name
Test status
Simulation time 131477307 ps
CPU time 1.27 seconds
Started Jul 15 07:01:45 PM PDT 24
Finished Jul 15 07:01:47 PM PDT 24
Peak memory 196220 kb
Host smart-64911a35-37a8-40f8-bac0-d1502c99c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146244814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.146244814
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1218413806
Short name T448
Test name
Test status
Simulation time 35973338 ps
CPU time 0.9 seconds
Started Jul 15 07:01:47 PM PDT 24
Finished Jul 15 07:01:49 PM PDT 24
Peak memory 196232 kb
Host smart-8ad57673-d2a7-4630-a8c2-8e39c32d8264
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218413806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1218413806
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.913745052
Short name T122
Test name
Test status
Simulation time 979368871 ps
CPU time 27.18 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:02:21 PM PDT 24
Peak memory 198656 kb
Host smart-3d0f849f-c535-4dea-be9e-4ff5931daf07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913745052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.913745052
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3415124900
Short name T41
Test name
Test status
Simulation time 473316059695 ps
CPU time 2451.04 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:42:43 PM PDT 24
Peak memory 198884 kb
Host smart-c30944a5-232b-4ede-90ee-6346218de787
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3415124900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3415124900
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3733355828
Short name T557
Test name
Test status
Simulation time 12959868 ps
CPU time 0.58 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:01:52 PM PDT 24
Peak memory 194656 kb
Host smart-e583acb7-6b36-461a-8447-b00d75fe16ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733355828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3733355828
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2882266814
Short name T160
Test name
Test status
Simulation time 21736959 ps
CPU time 0.71 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:01:54 PM PDT 24
Peak memory 194804 kb
Host smart-34d91e55-e83a-4c31-8c19-83782888639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882266814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2882266814
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4151219316
Short name T323
Test name
Test status
Simulation time 8598196068 ps
CPU time 27.38 seconds
Started Jul 15 07:01:50 PM PDT 24
Finished Jul 15 07:02:18 PM PDT 24
Peak memory 197344 kb
Host smart-0d3aec86-b944-4be5-a758-fba6bb63708d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151219316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4151219316
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.41259405
Short name T25
Test name
Test status
Simulation time 56061831 ps
CPU time 0.73 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:01:53 PM PDT 24
Peak memory 196448 kb
Host smart-ebc56985-38c0-40dc-8a1f-33e57c550ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41259405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.41259405
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2289919400
Short name T186
Test name
Test status
Simulation time 58058480 ps
CPU time 1.36 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:01:55 PM PDT 24
Peak memory 197876 kb
Host smart-149ea99d-14de-4449-8cf0-7580ad7f3b67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289919400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2289919400
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2474119432
Short name T691
Test name
Test status
Simulation time 89199075 ps
CPU time 3.5 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:01:56 PM PDT 24
Peak memory 198664 kb
Host smart-9f44ef3b-dc67-4d06-833d-97070b3f343d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474119432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2474119432
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.116486989
Short name T173
Test name
Test status
Simulation time 50409763 ps
CPU time 1.56 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:01:56 PM PDT 24
Peak memory 197576 kb
Host smart-48f6230c-1704-4eeb-92fc-6af84d625dae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116486989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
116486989
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.314387587
Short name T664
Test name
Test status
Simulation time 95086958 ps
CPU time 1.01 seconds
Started Jul 15 07:01:52 PM PDT 24
Finished Jul 15 07:01:54 PM PDT 24
Peak memory 196716 kb
Host smart-0963c5b9-3dca-448b-ba39-4572720471e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314387587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.314387587
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1101513252
Short name T643
Test name
Test status
Simulation time 25976307 ps
CPU time 0.87 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:01:52 PM PDT 24
Peak memory 196476 kb
Host smart-c72df6ae-6c3b-48f3-970b-42e12aa41374
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101513252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1101513252
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3378960766
Short name T388
Test name
Test status
Simulation time 136557477 ps
CPU time 3.32 seconds
Started Jul 15 07:01:52 PM PDT 24
Finished Jul 15 07:01:57 PM PDT 24
Peak memory 198604 kb
Host smart-3c097ce3-ff1d-4c0f-9926-fc1e97c1278f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378960766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3378960766
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.369883035
Short name T644
Test name
Test status
Simulation time 697217921 ps
CPU time 1.26 seconds
Started Jul 15 07:01:52 PM PDT 24
Finished Jul 15 07:01:54 PM PDT 24
Peak memory 196248 kb
Host smart-6d85d16d-44a0-4970-9b4a-d307921a158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369883035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.369883035
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1433818039
Short name T259
Test name
Test status
Simulation time 107079191 ps
CPU time 1.1 seconds
Started Jul 15 07:01:50 PM PDT 24
Finished Jul 15 07:01:52 PM PDT 24
Peak memory 196920 kb
Host smart-d081a543-4b0e-44a9-9687-55e54ad3a9fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433818039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1433818039
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.265653094
Short name T295
Test name
Test status
Simulation time 31634071020 ps
CPU time 108.65 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:03:42 PM PDT 24
Peak memory 198748 kb
Host smart-bb383989-7ba9-46f6-aa6e-26d8d4a8e9c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265653094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.265653094
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.766746081
Short name T594
Test name
Test status
Simulation time 123215653975 ps
CPU time 2120.78 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:37:15 PM PDT 24
Peak memory 199016 kb
Host smart-c5dc3a5f-7e3f-484b-b400-dfdb64b425d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=766746081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.766746081
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4088100779
Short name T484
Test name
Test status
Simulation time 48031625 ps
CPU time 0.58 seconds
Started Jul 15 07:01:57 PM PDT 24
Finished Jul 15 07:01:58 PM PDT 24
Peak memory 193732 kb
Host smart-c1095f5d-3e7f-48f7-8df2-ca1a3493dd64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088100779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4088100779
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.74672432
Short name T158
Test name
Test status
Simulation time 24583026 ps
CPU time 0.7 seconds
Started Jul 15 07:01:54 PM PDT 24
Finished Jul 15 07:01:55 PM PDT 24
Peak memory 194808 kb
Host smart-03b3a5ac-a2d1-4ec0-a8b2-ed63c219fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74672432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.74672432
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3394909450
Short name T440
Test name
Test status
Simulation time 1527613561 ps
CPU time 26.47 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:02:21 PM PDT 24
Peak memory 197596 kb
Host smart-332d11e1-381b-4ca9-814e-20f40ac64e5d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394909450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3394909450
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1882737817
Short name T564
Test name
Test status
Simulation time 31982921 ps
CPU time 0.72 seconds
Started Jul 15 07:01:53 PM PDT 24
Finished Jul 15 07:01:54 PM PDT 24
Peak memory 195524 kb
Host smart-f006aa85-c37a-4b94-ba32-13738b0f28d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882737817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1882737817
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2602161432
Short name T597
Test name
Test status
Simulation time 192244440 ps
CPU time 0.97 seconds
Started Jul 15 07:01:52 PM PDT 24
Finished Jul 15 07:01:53 PM PDT 24
Peak memory 196680 kb
Host smart-548e5a3f-e9ea-466d-99fa-76d8e90a7481
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602161432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2602161432
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.929031298
Short name T583
Test name
Test status
Simulation time 81341062 ps
CPU time 1.04 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:01:53 PM PDT 24
Peak memory 196656 kb
Host smart-d2eb53a0-9d19-48e0-b9ad-031bbcbeea86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929031298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.929031298
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3725061165
Short name T180
Test name
Test status
Simulation time 50057937 ps
CPU time 1.64 seconds
Started Jul 15 07:01:50 PM PDT 24
Finished Jul 15 07:01:52 PM PDT 24
Peak memory 196708 kb
Host smart-bc21fdfb-802a-42b5-9a77-e5e3b016ac1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725061165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3725061165
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1749875586
Short name T493
Test name
Test status
Simulation time 116976361 ps
CPU time 0.85 seconds
Started Jul 15 07:01:54 PM PDT 24
Finished Jul 15 07:01:55 PM PDT 24
Peak memory 197220 kb
Host smart-c07799c6-7223-41b7-9c2f-03f819fe5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749875586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1749875586
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2928415346
Short name T553
Test name
Test status
Simulation time 202897516 ps
CPU time 0.86 seconds
Started Jul 15 07:01:52 PM PDT 24
Finished Jul 15 07:01:53 PM PDT 24
Peak memory 196432 kb
Host smart-5415a756-1d20-493f-b12a-c0a4283195ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928415346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2928415346
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.630056824
Short name T516
Test name
Test status
Simulation time 1696850295 ps
CPU time 4.58 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:01:57 PM PDT 24
Peak memory 198636 kb
Host smart-1bccf510-d1df-4aef-9227-ed818ba39cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630056824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.630056824
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.546372618
Short name T81
Test name
Test status
Simulation time 46128697 ps
CPU time 0.97 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:01:53 PM PDT 24
Peak memory 196156 kb
Host smart-114662f6-5e8e-47dd-885e-a6d90d976710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546372618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.546372618
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2050409345
Short name T24
Test name
Test status
Simulation time 71262702 ps
CPU time 1.03 seconds
Started Jul 15 07:01:49 PM PDT 24
Finished Jul 15 07:01:50 PM PDT 24
Peak memory 197104 kb
Host smart-22a38594-33ff-454f-b913-cdccb21f612a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050409345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2050409345
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1400915346
Short name T62
Test name
Test status
Simulation time 69520082625 ps
CPU time 49.26 seconds
Started Jul 15 07:01:51 PM PDT 24
Finished Jul 15 07:02:41 PM PDT 24
Peak memory 198824 kb
Host smart-1fd47ede-56e8-4220-8422-ecd93bb15802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400915346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1400915346
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2775834134
Short name T117
Test name
Test status
Simulation time 21759071 ps
CPU time 0.63 seconds
Started Jul 15 07:01:58 PM PDT 24
Finished Jul 15 07:01:59 PM PDT 24
Peak memory 195376 kb
Host smart-3c22455b-a508-449f-82ce-47250d30dc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775834134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2775834134
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1665691885
Short name T490
Test name
Test status
Simulation time 53989943 ps
CPU time 0.78 seconds
Started Jul 15 07:01:55 PM PDT 24
Finished Jul 15 07:01:56 PM PDT 24
Peak memory 196648 kb
Host smart-95a83b65-ed92-4714-956e-d569e6b3ffbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665691885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1665691885
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3328175662
Short name T555
Test name
Test status
Simulation time 279178202 ps
CPU time 13.9 seconds
Started Jul 15 07:01:56 PM PDT 24
Finished Jul 15 07:02:10 PM PDT 24
Peak memory 196916 kb
Host smart-6cb7c0e9-9798-4daf-8fc6-c47eaa258b61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328175662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3328175662
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3148053936
Short name T422
Test name
Test status
Simulation time 229451367 ps
CPU time 0.87 seconds
Started Jul 15 07:02:02 PM PDT 24
Finished Jul 15 07:02:03 PM PDT 24
Peak memory 197256 kb
Host smart-023553a9-9ba9-44c3-a0ef-c7ba700fc6bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148053936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3148053936
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3658561524
Short name T139
Test name
Test status
Simulation time 163155982 ps
CPU time 1.34 seconds
Started Jul 15 07:01:56 PM PDT 24
Finished Jul 15 07:01:57 PM PDT 24
Peak memory 198704 kb
Host smart-7a5137f4-c956-4d83-899f-b58311d95569
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658561524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3658561524
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2387234643
Short name T239
Test name
Test status
Simulation time 96751466 ps
CPU time 3.9 seconds
Started Jul 15 07:01:55 PM PDT 24
Finished Jul 15 07:01:59 PM PDT 24
Peak memory 198636 kb
Host smart-11d1cd9c-cbd6-4f4d-b84b-e04fdc765739
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387234643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2387234643
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3072623999
Short name T123
Test name
Test status
Simulation time 264756425 ps
CPU time 2.24 seconds
Started Jul 15 07:01:57 PM PDT 24
Finished Jul 15 07:02:00 PM PDT 24
Peak memory 198724 kb
Host smart-742de6ef-e52d-49c0-a2f2-92b23ee938b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072623999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3072623999
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2065168160
Short name T291
Test name
Test status
Simulation time 201576313 ps
CPU time 1.29 seconds
Started Jul 15 07:01:55 PM PDT 24
Finished Jul 15 07:01:57 PM PDT 24
Peak memory 197676 kb
Host smart-e8ed7b61-4f2c-4a49-a16a-e5e7458b57e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065168160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2065168160
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3366396514
Short name T671
Test name
Test status
Simulation time 41233250 ps
CPU time 0.9 seconds
Started Jul 15 07:01:55 PM PDT 24
Finished Jul 15 07:01:57 PM PDT 24
Peak memory 196688 kb
Host smart-78c56de2-8b62-4642-830c-a8b855d78eb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366396514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3366396514
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1507495733
Short name T27
Test name
Test status
Simulation time 162093323 ps
CPU time 3.89 seconds
Started Jul 15 07:02:00 PM PDT 24
Finished Jul 15 07:02:04 PM PDT 24
Peak memory 198628 kb
Host smart-8728a662-1b3b-46d0-932a-46ae23cc81c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507495733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1507495733
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2057926329
Short name T230
Test name
Test status
Simulation time 331167853 ps
CPU time 1.54 seconds
Started Jul 15 07:01:56 PM PDT 24
Finished Jul 15 07:01:58 PM PDT 24
Peak memory 198664 kb
Host smart-de2a3242-736c-432b-81b5-6ea9fe0ec384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057926329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2057926329
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3815776100
Short name T712
Test name
Test status
Simulation time 69761233 ps
CPU time 1.06 seconds
Started Jul 15 07:01:56 PM PDT 24
Finished Jul 15 07:01:58 PM PDT 24
Peak memory 196520 kb
Host smart-56a119fa-aad1-407e-abb3-287cf1cd0508
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815776100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3815776100
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3967533766
Short name T577
Test name
Test status
Simulation time 45845216434 ps
CPU time 162.6 seconds
Started Jul 15 07:02:02 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 198772 kb
Host smart-d6aaa0a9-f9ec-4aad-b92a-ed0b93ff4eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967533766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3967533766
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2179520223
Short name T438
Test name
Test status
Simulation time 134762037676 ps
CPU time 947.52 seconds
Started Jul 15 07:01:57 PM PDT 24
Finished Jul 15 07:17:45 PM PDT 24
Peak memory 198128 kb
Host smart-dda5b078-c5bd-43d6-97c2-55a5db3b8796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2179520223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2179520223
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.742550411
Short name T456
Test name
Test status
Simulation time 12601335 ps
CPU time 0.56 seconds
Started Jul 15 07:02:07 PM PDT 24
Finished Jul 15 07:02:08 PM PDT 24
Peak memory 194640 kb
Host smart-74695197-261c-4c27-80d5-0d5f5da470cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742550411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.742550411
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2330144629
Short name T595
Test name
Test status
Simulation time 22540031 ps
CPU time 0.76 seconds
Started Jul 15 07:02:02 PM PDT 24
Finished Jul 15 07:02:03 PM PDT 24
Peak memory 195940 kb
Host smart-aca57ad1-d7a2-4998-b182-915e4f530949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330144629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2330144629
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1176803769
Short name T602
Test name
Test status
Simulation time 2971847741 ps
CPU time 26.55 seconds
Started Jul 15 07:01:57 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 197700 kb
Host smart-7eae9c28-40f8-4c9f-82f5-29714e873ef3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176803769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1176803769
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3954231930
Short name T414
Test name
Test status
Simulation time 229388089 ps
CPU time 0.98 seconds
Started Jul 15 07:01:58 PM PDT 24
Finished Jul 15 07:01:59 PM PDT 24
Peak memory 198432 kb
Host smart-efedf1bd-0c01-47fb-83b7-4e1017219e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954231930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3954231930
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3999802280
Short name T464
Test name
Test status
Simulation time 818649312 ps
CPU time 1.41 seconds
Started Jul 15 07:01:56 PM PDT 24
Finished Jul 15 07:01:58 PM PDT 24
Peak memory 197504 kb
Host smart-ecef7556-164e-4f18-aece-56e3066366f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999802280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3999802280
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2977788941
Short name T363
Test name
Test status
Simulation time 106705019 ps
CPU time 1.31 seconds
Started Jul 15 07:01:55 PM PDT 24
Finished Jul 15 07:01:57 PM PDT 24
Peak memory 197416 kb
Host smart-fbf95c7c-aa58-4e08-aa13-cb64899d209c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977788941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2977788941
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.236685941
Short name T190
Test name
Test status
Simulation time 68105355 ps
CPU time 1.46 seconds
Started Jul 15 07:01:56 PM PDT 24
Finished Jul 15 07:01:58 PM PDT 24
Peak memory 197436 kb
Host smart-b36d0339-22c2-4c88-bf41-be3f833bfd4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236685941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
236685941
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3102325136
Short name T161
Test name
Test status
Simulation time 43255196 ps
CPU time 0.91 seconds
Started Jul 15 07:01:57 PM PDT 24
Finished Jul 15 07:01:58 PM PDT 24
Peak memory 196644 kb
Host smart-9288ed6b-5810-4787-a1e0-8ca2577eb5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102325136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3102325136
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1206820249
Short name T258
Test name
Test status
Simulation time 33824642 ps
CPU time 1.32 seconds
Started Jul 15 07:01:58 PM PDT 24
Finished Jul 15 07:02:00 PM PDT 24
Peak memory 197492 kb
Host smart-c548eba0-9eed-4c53-a712-dfc42d09ea38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206820249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1206820249
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3162379440
Short name T378
Test name
Test status
Simulation time 152454037 ps
CPU time 3.55 seconds
Started Jul 15 07:02:02 PM PDT 24
Finished Jul 15 07:02:06 PM PDT 24
Peak memory 198636 kb
Host smart-6757fe97-fa94-4eac-b2a4-072676985bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162379440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3162379440
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1819546341
Short name T376
Test name
Test status
Simulation time 358080851 ps
CPU time 1.32 seconds
Started Jul 15 07:01:59 PM PDT 24
Finished Jul 15 07:02:01 PM PDT 24
Peak memory 196468 kb
Host smart-38e25c0d-df9a-404a-8d40-eae730dd7f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819546341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1819546341
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2414752115
Short name T251
Test name
Test status
Simulation time 519994259 ps
CPU time 0.91 seconds
Started Jul 15 07:01:58 PM PDT 24
Finished Jul 15 07:01:59 PM PDT 24
Peak memory 197048 kb
Host smart-d48beb4c-4262-41d9-b81f-9859d1b86b7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414752115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2414752115
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3589729070
Short name T379
Test name
Test status
Simulation time 14602271499 ps
CPU time 63.82 seconds
Started Jul 15 07:01:54 PM PDT 24
Finished Jul 15 07:02:58 PM PDT 24
Peak memory 198744 kb
Host smart-18309a1b-27d4-4c8b-9e75-0bd25fac3a7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589729070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3589729070
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3231137541
Short name T569
Test name
Test status
Simulation time 29894055 ps
CPU time 0.59 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:07 PM PDT 24
Peak memory 195552 kb
Host smart-e44fd2c1-01dc-4dd5-a4cc-10a432f70f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231137541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3231137541
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.918634880
Short name T496
Test name
Test status
Simulation time 225155785 ps
CPU time 0.71 seconds
Started Jul 15 07:02:04 PM PDT 24
Finished Jul 15 07:02:06 PM PDT 24
Peak memory 194812 kb
Host smart-89124307-4bb2-4cd3-b28e-8095c8e8f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918634880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.918634880
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.853094980
Short name T203
Test name
Test status
Simulation time 4271689916 ps
CPU time 13.23 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:18 PM PDT 24
Peak memory 196556 kb
Host smart-f7e0344f-445d-4b2f-84d6-846a21535e77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853094980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.853094980
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1906550005
Short name T276
Test name
Test status
Simulation time 92707090 ps
CPU time 1.04 seconds
Started Jul 15 07:02:04 PM PDT 24
Finished Jul 15 07:02:06 PM PDT 24
Peak memory 197352 kb
Host smart-b20a215a-7556-450a-a61c-7ae940e66a0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906550005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1906550005
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1024376048
Short name T547
Test name
Test status
Simulation time 33343790 ps
CPU time 1 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:07 PM PDT 24
Peak memory 196488 kb
Host smart-2fe78b0a-0568-43b8-8646-323ab5649295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024376048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1024376048
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3917736746
Short name T335
Test name
Test status
Simulation time 440977931 ps
CPU time 2.51 seconds
Started Jul 15 07:02:04 PM PDT 24
Finished Jul 15 07:02:08 PM PDT 24
Peak memory 196904 kb
Host smart-0f8b85ef-952a-4675-92ab-7f891c72b011
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917736746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3917736746
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2956210362
Short name T156
Test name
Test status
Simulation time 693513814 ps
CPU time 2.49 seconds
Started Jul 15 07:02:06 PM PDT 24
Finished Jul 15 07:02:10 PM PDT 24
Peak memory 197584 kb
Host smart-96fcea39-ead5-4018-b022-3d377b50f31e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956210362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2956210362
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4073215658
Short name T390
Test name
Test status
Simulation time 221531689 ps
CPU time 0.87 seconds
Started Jul 15 07:02:01 PM PDT 24
Finished Jul 15 07:02:02 PM PDT 24
Peak memory 196636 kb
Host smart-125c0131-4f9a-48a1-b579-73b881e8993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073215658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4073215658
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1027503383
Short name T401
Test name
Test status
Simulation time 24007503 ps
CPU time 0.9 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:07 PM PDT 24
Peak memory 196716 kb
Host smart-d1668fcf-ca8c-4890-99dc-173a0e69fba5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027503383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1027503383
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.597566488
Short name T377
Test name
Test status
Simulation time 347488810 ps
CPU time 4.91 seconds
Started Jul 15 07:02:02 PM PDT 24
Finished Jul 15 07:02:07 PM PDT 24
Peak memory 198648 kb
Host smart-f83f7681-005b-4a93-8757-bb195fbde5dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597566488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.597566488
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1455878630
Short name T570
Test name
Test status
Simulation time 76087161 ps
CPU time 1.17 seconds
Started Jul 15 07:02:01 PM PDT 24
Finished Jul 15 07:02:03 PM PDT 24
Peak memory 197448 kb
Host smart-648a5508-df5d-4402-91a7-1d75d8452c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455878630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1455878630
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.76817115
Short name T215
Test name
Test status
Simulation time 43176431 ps
CPU time 1.26 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:07 PM PDT 24
Peak memory 197148 kb
Host smart-524ab05d-7aa4-4fe3-98c3-9858d2f3263f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76817115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.76817115
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2800315431
Short name T651
Test name
Test status
Simulation time 17478282401 ps
CPU time 74.29 seconds
Started Jul 15 07:02:02 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 198764 kb
Host smart-fb29853d-a604-49f2-8eee-852c6757220e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800315431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2800315431
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1699430497
Short name T77
Test name
Test status
Simulation time 26338500649 ps
CPU time 706.09 seconds
Started Jul 15 07:02:03 PM PDT 24
Finished Jul 15 07:13:49 PM PDT 24
Peak memory 198980 kb
Host smart-f777072f-b037-4c3c-ad85-9bb0eb6ddc88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1699430497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1699430497
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1284317562
Short name T297
Test name
Test status
Simulation time 115893814 ps
CPU time 0.57 seconds
Started Jul 15 07:00:27 PM PDT 24
Finished Jul 15 07:00:28 PM PDT 24
Peak memory 194644 kb
Host smart-04906463-bc47-43e1-9184-6cd63b81b03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284317562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1284317562
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2711733746
Short name T199
Test name
Test status
Simulation time 443566797 ps
CPU time 0.91 seconds
Started Jul 15 07:00:23 PM PDT 24
Finished Jul 15 07:00:25 PM PDT 24
Peak memory 197408 kb
Host smart-bd9eff2a-665a-4c79-8711-e5ff5af6ecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711733746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2711733746
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.276150114
Short name T510
Test name
Test status
Simulation time 767972090 ps
CPU time 10.16 seconds
Started Jul 15 07:00:26 PM PDT 24
Finished Jul 15 07:00:37 PM PDT 24
Peak memory 198644 kb
Host smart-5d54dc93-1ca1-4fb2-a33b-a99ead9f3f9e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276150114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.276150114
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1513049566
Short name T660
Test name
Test status
Simulation time 32326941 ps
CPU time 0.7 seconds
Started Jul 15 07:00:26 PM PDT 24
Finished Jul 15 07:00:27 PM PDT 24
Peak memory 196052 kb
Host smart-c2196d0b-056b-4fb7-b8bc-67e439d890ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513049566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1513049566
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3085610558
Short name T138
Test name
Test status
Simulation time 77205054 ps
CPU time 0.68 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:00:22 PM PDT 24
Peak memory 195664 kb
Host smart-e0ebfbad-40fa-4094-ad80-f92a6714d538
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085610558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3085610558
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2276246387
Short name T14
Test name
Test status
Simulation time 136839192 ps
CPU time 1.64 seconds
Started Jul 15 07:00:22 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 197112 kb
Host smart-95853f76-5277-43b8-bee2-b7fd15753db1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276246387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2276246387
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2699346360
Short name T232
Test name
Test status
Simulation time 144009366 ps
CPU time 2.97 seconds
Started Jul 15 07:00:19 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 197548 kb
Host smart-704e83da-e38d-46b8-9ce3-92d034efd88c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699346360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2699346360
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1191495569
Short name T479
Test name
Test status
Simulation time 30481748 ps
CPU time 0.87 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 196208 kb
Host smart-f78cac49-4659-4c73-bec5-b02a16f399d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191495569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1191495569
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2322856896
Short name T142
Test name
Test status
Simulation time 123890071 ps
CPU time 1.18 seconds
Started Jul 15 07:00:20 PM PDT 24
Finished Jul 15 07:00:21 PM PDT 24
Peak memory 196836 kb
Host smart-e5cc605a-aaed-40dd-9e51-f6edb66d07da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322856896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2322856896
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2619484064
Short name T226
Test name
Test status
Simulation time 81583283 ps
CPU time 3.67 seconds
Started Jul 15 07:00:28 PM PDT 24
Finished Jul 15 07:00:32 PM PDT 24
Peak memory 198664 kb
Host smart-16cc474c-96cb-412e-97ca-9b18a62fdc1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619484064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2619484064
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3654617549
Short name T60
Test name
Test status
Simulation time 89081227 ps
CPU time 0.88 seconds
Started Jul 15 07:00:26 PM PDT 24
Finished Jul 15 07:00:28 PM PDT 24
Peak memory 214220 kb
Host smart-ceff4e81-51fb-4672-86a5-22780f184944
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654617549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3654617549
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.211858519
Short name T319
Test name
Test status
Simulation time 113138851 ps
CPU time 0.98 seconds
Started Jul 15 07:00:21 PM PDT 24
Finished Jul 15 07:00:22 PM PDT 24
Peak memory 196232 kb
Host smart-3e7b51e9-3226-4115-8a43-763c707ef233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211858519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.211858519
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2841640185
Short name T338
Test name
Test status
Simulation time 191685234 ps
CPU time 1.19 seconds
Started Jul 15 07:00:23 PM PDT 24
Finished Jul 15 07:00:25 PM PDT 24
Peak memory 196220 kb
Host smart-c99f0575-d868-44a1-b7a7-9f82af4eefbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841640185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2841640185
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.45342124
Short name T478
Test name
Test status
Simulation time 10890416073 ps
CPU time 147.55 seconds
Started Jul 15 07:00:25 PM PDT 24
Finished Jul 15 07:02:53 PM PDT 24
Peak memory 198776 kb
Host smart-abc552ee-364f-4994-91e4-1e00bbd87059
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45342124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpi
o_stress_all.45342124
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2188546427
Short name T147
Test name
Test status
Simulation time 22441946 ps
CPU time 0.58 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:07 PM PDT 24
Peak memory 195344 kb
Host smart-3fe66492-5125-44ce-96a9-706158a542f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188546427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2188546427
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1979447889
Short name T267
Test name
Test status
Simulation time 53910953 ps
CPU time 0.7 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:06 PM PDT 24
Peak memory 196488 kb
Host smart-16db6e5f-b154-4315-8dfb-8ef9cb69f43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979447889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1979447889
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.203401232
Short name T326
Test name
Test status
Simulation time 592359005 ps
CPU time 19.68 seconds
Started Jul 15 07:02:07 PM PDT 24
Finished Jul 15 07:02:28 PM PDT 24
Peak memory 198700 kb
Host smart-5840fea5-5164-430e-a78f-78e5698c3b87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203401232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.203401232
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1548761021
Short name T480
Test name
Test status
Simulation time 218740654 ps
CPU time 0.83 seconds
Started Jul 15 07:02:03 PM PDT 24
Finished Jul 15 07:02:04 PM PDT 24
Peak memory 197244 kb
Host smart-ed6d44da-6968-491b-858c-17b1c629865c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548761021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1548761021
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.395592242
Short name T131
Test name
Test status
Simulation time 45005618 ps
CPU time 0.89 seconds
Started Jul 15 07:02:04 PM PDT 24
Finished Jul 15 07:02:06 PM PDT 24
Peak memory 196224 kb
Host smart-054a9756-ef59-4e4f-9a0d-fb187a79f872
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395592242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.395592242
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.823816320
Short name T250
Test name
Test status
Simulation time 382266734 ps
CPU time 3.84 seconds
Started Jul 15 07:01:59 PM PDT 24
Finished Jul 15 07:02:04 PM PDT 24
Peak memory 198684 kb
Host smart-1483a16a-2cc4-4a0c-9f9a-bc69cd504d94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823816320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.823816320
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.4039889806
Short name T195
Test name
Test status
Simulation time 51760914 ps
CPU time 1.31 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:07 PM PDT 24
Peak memory 196952 kb
Host smart-62848b35-3ba9-411e-8d04-f18e8277e9a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039889806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.4039889806
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1691119916
Short name T358
Test name
Test status
Simulation time 61365474 ps
CPU time 0.9 seconds
Started Jul 15 07:02:03 PM PDT 24
Finished Jul 15 07:02:04 PM PDT 24
Peak memory 197980 kb
Host smart-1c9f2eeb-2ff0-4823-abfd-42de7b1f140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691119916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1691119916
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2579844519
Short name T357
Test name
Test status
Simulation time 299331751 ps
CPU time 1 seconds
Started Jul 15 07:02:04 PM PDT 24
Finished Jul 15 07:02:06 PM PDT 24
Peak memory 197344 kb
Host smart-a5e6d72b-62c6-43e3-b83b-380aa8cc2590
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579844519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2579844519
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3703361902
Short name T150
Test name
Test status
Simulation time 282930946 ps
CPU time 1.48 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:02:08 PM PDT 24
Peak memory 198372 kb
Host smart-f3fbc321-d0ee-4567-8bcd-c790a9982362
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703361902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3703361902
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1442012249
Short name T587
Test name
Test status
Simulation time 53123817 ps
CPU time 1.1 seconds
Started Jul 15 07:02:06 PM PDT 24
Finished Jul 15 07:02:08 PM PDT 24
Peak memory 197248 kb
Host smart-6382498b-dceb-440e-a6df-7f66393e4880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442012249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1442012249
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.442452114
Short name T185
Test name
Test status
Simulation time 45753570 ps
CPU time 1 seconds
Started Jul 15 07:02:03 PM PDT 24
Finished Jul 15 07:02:05 PM PDT 24
Peak memory 197052 kb
Host smart-30f2623b-1f31-422c-833c-5d6a44cd31d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442452114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.442452114
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1287995587
Short name T224
Test name
Test status
Simulation time 19655340657 ps
CPU time 121.92 seconds
Started Jul 15 07:02:05 PM PDT 24
Finished Jul 15 07:04:08 PM PDT 24
Peak memory 198808 kb
Host smart-0770b8fe-b786-4033-bc53-d9868944740d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287995587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1287995587
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3203014031
Short name T380
Test name
Test status
Simulation time 65589654 ps
CPU time 0.58 seconds
Started Jul 15 07:02:08 PM PDT 24
Finished Jul 15 07:02:09 PM PDT 24
Peak memory 194696 kb
Host smart-09356913-6cb4-4992-b486-4615ceea2421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203014031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3203014031
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1452778281
Short name T654
Test name
Test status
Simulation time 82717207 ps
CPU time 0.84 seconds
Started Jul 15 07:02:14 PM PDT 24
Finished Jul 15 07:02:15 PM PDT 24
Peak memory 197036 kb
Host smart-0ee68000-1a49-4322-8a83-4244620d8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452778281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1452778281
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.780012110
Short name T517
Test name
Test status
Simulation time 488996326 ps
CPU time 25.35 seconds
Started Jul 15 07:02:15 PM PDT 24
Finished Jul 15 07:02:41 PM PDT 24
Peak memory 197632 kb
Host smart-b5b5e67a-3d4b-422c-bcb0-011c385484c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780012110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.780012110
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.115363967
Short name T491
Test name
Test status
Simulation time 183502757 ps
CPU time 1.11 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:02:14 PM PDT 24
Peak memory 197276 kb
Host smart-3ddab8a4-7998-4210-8647-fa8d27c049fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115363967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.115363967
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2029013971
Short name T37
Test name
Test status
Simulation time 77543908 ps
CPU time 1.16 seconds
Started Jul 15 07:02:09 PM PDT 24
Finished Jul 15 07:02:11 PM PDT 24
Peak memory 196744 kb
Host smart-07298eef-a2b2-4456-949e-546e05ea4153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029013971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2029013971
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2678067552
Short name T175
Test name
Test status
Simulation time 20393721 ps
CPU time 1 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 196776 kb
Host smart-5c361ecd-18ee-441c-bbc0-97210258cea4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678067552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2678067552
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1967830953
Short name T703
Test name
Test status
Simulation time 142164635 ps
CPU time 3.03 seconds
Started Jul 15 07:02:14 PM PDT 24
Finished Jul 15 07:02:18 PM PDT 24
Peak memory 198740 kb
Host smart-5509f709-970b-4a54-9b6e-845b8203f633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967830953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1967830953
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3564622134
Short name T523
Test name
Test status
Simulation time 71111619 ps
CPU time 1.29 seconds
Started Jul 15 07:02:09 PM PDT 24
Finished Jul 15 07:02:10 PM PDT 24
Peak memory 196472 kb
Host smart-6ec7acff-4694-4499-86af-859b276bdca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564622134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3564622134
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1424486916
Short name T458
Test name
Test status
Simulation time 48375842 ps
CPU time 0.83 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:02:15 PM PDT 24
Peak memory 196176 kb
Host smart-e5967ed0-8660-4fce-807f-28ee1123d832
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424486916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1424486916
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3200682855
Short name T284
Test name
Test status
Simulation time 98984281 ps
CPU time 1.67 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:13 PM PDT 24
Peak memory 198448 kb
Host smart-e526d9f9-949a-4e73-af56-0fec99f043e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200682855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3200682855
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1733686004
Short name T255
Test name
Test status
Simulation time 55701125 ps
CPU time 1.15 seconds
Started Jul 15 07:02:06 PM PDT 24
Finished Jul 15 07:02:08 PM PDT 24
Peak memory 197076 kb
Host smart-9db647d4-cd25-465c-bbe3-967c0f6e6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733686004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1733686004
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1169014559
Short name T300
Test name
Test status
Simulation time 275696310 ps
CPU time 1.55 seconds
Started Jul 15 07:02:15 PM PDT 24
Finished Jul 15 07:02:17 PM PDT 24
Peak memory 197416 kb
Host smart-84b7d0f9-2ba1-4f79-857f-445409ac9292
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169014559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1169014559
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3361377928
Short name T372
Test name
Test status
Simulation time 21518548479 ps
CPU time 80.06 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:03:31 PM PDT 24
Peak memory 198816 kb
Host smart-39c45f6d-8f93-42c2-a4c4-e472727660ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361377928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3361377928
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.246722800
Short name T521
Test name
Test status
Simulation time 13171511 ps
CPU time 0.55 seconds
Started Jul 15 07:02:13 PM PDT 24
Finished Jul 15 07:02:14 PM PDT 24
Peak memory 194648 kb
Host smart-30ff9c08-2553-4c6c-a00e-89ba1c67a230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246722800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.246722800
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3095375845
Short name T584
Test name
Test status
Simulation time 42696391 ps
CPU time 0.67 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:11 PM PDT 24
Peak memory 194752 kb
Host smart-7580919a-bef1-4b77-8e37-6f9f0fe8c22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095375845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3095375845
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3198423589
Short name T365
Test name
Test status
Simulation time 2742728506 ps
CPU time 24.75 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 198240 kb
Host smart-83d847a7-a590-49ab-81eb-4dd41fb05a33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198423589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3198423589
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3685264451
Short name T352
Test name
Test status
Simulation time 113521138 ps
CPU time 0.91 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:02:14 PM PDT 24
Peak memory 196836 kb
Host smart-a2b1b886-0f52-4892-8b31-404d40c96cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685264451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3685264451
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3883714158
Short name T492
Test name
Test status
Simulation time 193794024 ps
CPU time 0.95 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 197376 kb
Host smart-780efc93-a514-4298-b282-383729280fba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883714158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3883714158
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2685631083
Short name T678
Test name
Test status
Simulation time 34851093 ps
CPU time 1.02 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 196940 kb
Host smart-799d57a5-f73f-4538-9cac-1eb49af92eea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685631083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2685631083
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1262257408
Short name T305
Test name
Test status
Simulation time 714156610 ps
CPU time 3.43 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:02:17 PM PDT 24
Peak memory 197768 kb
Host smart-071b8f0f-f23e-4728-9981-3f91110827ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262257408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1262257408
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3915064505
Short name T359
Test name
Test status
Simulation time 202986977 ps
CPU time 1.24 seconds
Started Jul 15 07:02:11 PM PDT 24
Finished Jul 15 07:02:14 PM PDT 24
Peak memory 197256 kb
Host smart-f7aa7a6e-af71-4060-acf0-566fe3f72e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915064505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3915064505
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.917554749
Short name T367
Test name
Test status
Simulation time 26957213 ps
CPU time 0.91 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 197184 kb
Host smart-9c9d2925-db60-4521-9fbe-7c16c0ae8018
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917554749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.917554749
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4146273539
Short name T629
Test name
Test status
Simulation time 113417723 ps
CPU time 5.2 seconds
Started Jul 15 07:02:15 PM PDT 24
Finished Jul 15 07:02:21 PM PDT 24
Peak memory 198648 kb
Host smart-e962d0af-deac-450f-9bd6-3273e441cfdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146273539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4146273539
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.414822252
Short name T529
Test name
Test status
Simulation time 82908806 ps
CPU time 0.7 seconds
Started Jul 15 07:02:11 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 195464 kb
Host smart-ee9d1ea3-bdcc-49c6-aa9a-7efb494ddd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414822252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.414822252
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2236115195
Short name T355
Test name
Test status
Simulation time 305125265 ps
CPU time 1.15 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 196300 kb
Host smart-c0bbe0f7-bdbd-43ee-aacb-7544a054eec5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236115195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2236115195
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.392067961
Short name T462
Test name
Test status
Simulation time 11776769236 ps
CPU time 129.81 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 198812 kb
Host smart-5885ee2f-96b2-4651-a2e0-242bfd81461b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392067961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.392067961
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3318295589
Short name T72
Test name
Test status
Simulation time 140208872074 ps
CPU time 1099.07 seconds
Started Jul 15 07:02:13 PM PDT 24
Finished Jul 15 07:20:33 PM PDT 24
Peak memory 198908 kb
Host smart-c32fac9c-8e7f-405f-95c8-2d84ae1ac746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3318295589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3318295589
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2502500406
Short name T421
Test name
Test status
Simulation time 119304717 ps
CPU time 0.68 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:02:14 PM PDT 24
Peak memory 195340 kb
Host smart-e78a243c-7147-4a2d-b8dd-b4873a015c32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502500406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2502500406
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.861817326
Short name T208
Test name
Test status
Simulation time 125473590 ps
CPU time 0.82 seconds
Started Jul 15 07:02:14 PM PDT 24
Finished Jul 15 07:02:16 PM PDT 24
Peak memory 195920 kb
Host smart-bccadba0-ffd8-4b21-bd16-6f3fac6d03a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861817326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.861817326
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1173197131
Short name T680
Test name
Test status
Simulation time 616819848 ps
CPU time 3.97 seconds
Started Jul 15 07:02:11 PM PDT 24
Finished Jul 15 07:02:16 PM PDT 24
Peak memory 196604 kb
Host smart-6b3cdee2-6dfb-4e25-901d-705fede542b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173197131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1173197131
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3513706105
Short name T679
Test name
Test status
Simulation time 63903148 ps
CPU time 0.75 seconds
Started Jul 15 07:02:07 PM PDT 24
Finished Jul 15 07:02:08 PM PDT 24
Peak memory 196996 kb
Host smart-efe13cd5-3850-4752-969c-99bdae970772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513706105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3513706105
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3368542094
Short name T613
Test name
Test status
Simulation time 336574299 ps
CPU time 1.28 seconds
Started Jul 15 07:02:14 PM PDT 24
Finished Jul 15 07:02:17 PM PDT 24
Peak memory 196604 kb
Host smart-b345d505-4eaa-4549-bc06-fade5f7f3b05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368542094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3368542094
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3020906425
Short name T603
Test name
Test status
Simulation time 34874593 ps
CPU time 1.03 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 196252 kb
Host smart-ae0e63bd-e8d4-438e-acb5-38732bbb6891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020906425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3020906425
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.23150268
Short name T162
Test name
Test status
Simulation time 30976945 ps
CPU time 1.11 seconds
Started Jul 15 07:02:13 PM PDT 24
Finished Jul 15 07:02:15 PM PDT 24
Peak memory 197256 kb
Host smart-96940505-b84c-4a4c-bdd8-67aee300a632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23150268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.23150268
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.909980508
Short name T145
Test name
Test status
Simulation time 48596997 ps
CPU time 0.99 seconds
Started Jul 15 07:02:14 PM PDT 24
Finished Jul 15 07:02:16 PM PDT 24
Peak memory 196404 kb
Host smart-e7ec3878-1490-48c6-8190-84ae6fb73dd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909980508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.909980508
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1093336218
Short name T449
Test name
Test status
Simulation time 1040203148 ps
CPU time 4.41 seconds
Started Jul 15 07:02:09 PM PDT 24
Finished Jul 15 07:02:14 PM PDT 24
Peak memory 198532 kb
Host smart-48e6306c-d2cf-42c3-8f8a-b993558bd2fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093336218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1093336218
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.187973636
Short name T262
Test name
Test status
Simulation time 124208006 ps
CPU time 1.04 seconds
Started Jul 15 07:02:10 PM PDT 24
Finished Jul 15 07:02:12 PM PDT 24
Peak memory 197208 kb
Host smart-f527a868-33fb-4857-b6f0-e25ead7e41c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187973636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.187973636
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3255489774
Short name T256
Test name
Test status
Simulation time 202827316 ps
CPU time 0.98 seconds
Started Jul 15 07:02:09 PM PDT 24
Finished Jul 15 07:02:10 PM PDT 24
Peak memory 196412 kb
Host smart-4b9de538-f661-4c14-a4c6-f33646b295fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255489774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3255489774
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2895228043
Short name T519
Test name
Test status
Simulation time 21925908300 ps
CPU time 150.2 seconds
Started Jul 15 07:02:09 PM PDT 24
Finished Jul 15 07:04:40 PM PDT 24
Peak memory 198792 kb
Host smart-5853abbf-78c9-4bf0-995d-b790a18c9cd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895228043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2895228043
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.714823772
Short name T75
Test name
Test status
Simulation time 155631013017 ps
CPU time 1031.45 seconds
Started Jul 15 07:02:12 PM PDT 24
Finished Jul 15 07:19:25 PM PDT 24
Peak memory 198952 kb
Host smart-55b239d1-e9b8-4a16-89d5-62338d2602b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=714823772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.714823772
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2019192452
Short name T241
Test name
Test status
Simulation time 12654465 ps
CPU time 0.57 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:21 PM PDT 24
Peak memory 194632 kb
Host smart-d105f6dc-7e00-494b-aa43-c3aaab0aad67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019192452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2019192452
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2222338228
Short name T144
Test name
Test status
Simulation time 80229704 ps
CPU time 0.84 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 196072 kb
Host smart-247982cc-d99c-4619-b9cb-fc63f9f329cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222338228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2222338228
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3911260998
Short name T610
Test name
Test status
Simulation time 650621265 ps
CPU time 18.45 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:02:44 PM PDT 24
Peak memory 198688 kb
Host smart-c457ed24-f421-4b64-9ad3-a329d5ffe2c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911260998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3911260998
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3462006226
Short name T592
Test name
Test status
Simulation time 21908849 ps
CPU time 0.6 seconds
Started Jul 15 07:02:21 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 194996 kb
Host smart-18f92392-5513-4c4d-a82b-f619c35f12c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462006226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3462006226
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.988662742
Short name T483
Test name
Test status
Simulation time 22258496 ps
CPU time 0.68 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 195616 kb
Host smart-096ba462-667b-454e-ac64-93c9469c333a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988662742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.988662742
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1049906424
Short name T392
Test name
Test status
Simulation time 66356224 ps
CPU time 0.88 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 196748 kb
Host smart-2bececae-022a-4870-b379-9b7e1cbe5a7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049906424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1049906424
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1875914530
Short name T611
Test name
Test status
Simulation time 304806038 ps
CPU time 2.99 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:29 PM PDT 24
Peak memory 197632 kb
Host smart-92bbc4e8-485c-42d4-86e1-9cfcb20a239e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875914530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1875914530
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2158771722
Short name T647
Test name
Test status
Simulation time 56046586 ps
CPU time 0.67 seconds
Started Jul 15 07:02:11 PM PDT 24
Finished Jul 15 07:02:13 PM PDT 24
Peak memory 196072 kb
Host smart-d9b7a1cb-1084-4b16-8b67-55ca32dee90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158771722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2158771722
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4126173011
Short name T537
Test name
Test status
Simulation time 23907360 ps
CPU time 0.75 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 196016 kb
Host smart-907e3fca-fd07-41a9-b9e2-dfb4e34c7818
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126173011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4126173011
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.454859976
Short name T273
Test name
Test status
Simulation time 110260157 ps
CPU time 2.24 seconds
Started Jul 15 07:02:17 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 198616 kb
Host smart-fd0ef746-08e1-4930-a0b4-ee6889f3dfc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454859976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.454859976
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1322183658
Short name T212
Test name
Test status
Simulation time 231765759 ps
CPU time 1.43 seconds
Started Jul 15 07:02:14 PM PDT 24
Finished Jul 15 07:02:16 PM PDT 24
Peak memory 198624 kb
Host smart-47f9541d-48e7-466c-a489-b39dfe59aa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322183658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1322183658
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1314486934
Short name T233
Test name
Test status
Simulation time 72531381 ps
CPU time 1.05 seconds
Started Jul 15 07:02:15 PM PDT 24
Finished Jul 15 07:02:17 PM PDT 24
Peak memory 196488 kb
Host smart-68641a5c-36bc-424a-924e-b4a2acf18b04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314486934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1314486934
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1576150622
Short name T545
Test name
Test status
Simulation time 5220998813 ps
CPU time 46.96 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 198692 kb
Host smart-11448303-da91-4c18-93b2-e22d5f67974b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576150622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1576150622
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3928813168
Short name T74
Test name
Test status
Simulation time 99010321059 ps
CPU time 2205.48 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:39:11 PM PDT 24
Peak memory 198912 kb
Host smart-f5b785ab-ee49-43da-83ac-bed83efca5af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3928813168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3928813168
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1524442385
Short name T339
Test name
Test status
Simulation time 37247984 ps
CPU time 0.55 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 194636 kb
Host smart-9fb656ad-70d7-4eff-a663-de9d37283caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524442385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1524442385
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1068986460
Short name T133
Test name
Test status
Simulation time 45258431 ps
CPU time 0.87 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 196092 kb
Host smart-7283378f-c234-4cc3-929a-5e7ddf653c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068986460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1068986460
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2058240269
Short name T192
Test name
Test status
Simulation time 207373787 ps
CPU time 7.87 seconds
Started Jul 15 07:02:17 PM PDT 24
Finished Jul 15 07:02:25 PM PDT 24
Peak memory 196200 kb
Host smart-8c720f84-a498-42ee-a9f5-2a5eb34a6794
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058240269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2058240269
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3910848004
Short name T18
Test name
Test status
Simulation time 221467718 ps
CPU time 0.91 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 196692 kb
Host smart-32b08ba7-276e-48f6-9b76-0002ab027b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910848004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3910848004
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.238293402
Short name T382
Test name
Test status
Simulation time 145957789 ps
CPU time 0.91 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 197328 kb
Host smart-1bf3a705-9045-4ed7-bd85-4556bdabd520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238293402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.238293402
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1411595854
Short name T182
Test name
Test status
Simulation time 216102623 ps
CPU time 1.26 seconds
Started Jul 15 07:02:22 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 197256 kb
Host smart-4d9d650d-d61d-4363-9430-4e0a1db541af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411595854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1411595854
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.840673715
Short name T666
Test name
Test status
Simulation time 771727772 ps
CPU time 3.39 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 196504 kb
Host smart-2a2dbba6-9b6e-4934-836d-2a6b2bc2fe65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840673715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
840673715
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1836396341
Short name T240
Test name
Test status
Simulation time 27168432 ps
CPU time 1.08 seconds
Started Jul 15 07:02:23 PM PDT 24
Finished Jul 15 07:02:25 PM PDT 24
Peak memory 196508 kb
Host smart-001ae096-4b18-421f-9eb9-90ca2749027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836396341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1836396341
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2357731933
Short name T394
Test name
Test status
Simulation time 163345976 ps
CPU time 1.17 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:02:26 PM PDT 24
Peak memory 198748 kb
Host smart-7e7253b9-511f-4a0c-babd-7e78ef91b7a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357731933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2357731933
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2344589767
Short name T677
Test name
Test status
Simulation time 25619190 ps
CPU time 1.23 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 198416 kb
Host smart-6c97379d-7e98-4048-a71e-239caa62d396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344589767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2344589767
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2872428791
Short name T213
Test name
Test status
Simulation time 387637443 ps
CPU time 1.49 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 196968 kb
Host smart-3baadb38-5944-4df8-b9c2-7c464adfed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872428791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2872428791
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.4116963345
Short name T536
Test name
Test status
Simulation time 50645977 ps
CPU time 1.32 seconds
Started Jul 15 07:02:22 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 197420 kb
Host smart-d3efa16b-efbb-4dc7-8394-329d47e12842
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116963345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.4116963345
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2675424259
Short name T79
Test name
Test status
Simulation time 27603984091 ps
CPU time 118.72 seconds
Started Jul 15 07:02:17 PM PDT 24
Finished Jul 15 07:04:16 PM PDT 24
Peak memory 198788 kb
Host smart-ff923075-b40d-4150-a19e-91108270ada4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675424259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2675424259
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3607571957
Short name T317
Test name
Test status
Simulation time 49830391 ps
CPU time 0.57 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 194628 kb
Host smart-f516bda8-fd91-4147-9643-8ad6f07f09b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607571957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3607571957
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1739649647
Short name T283
Test name
Test status
Simulation time 31768935 ps
CPU time 0.94 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 197220 kb
Host smart-2281462b-3795-4b06-8887-62d3dcc22835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739649647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1739649647
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2257835493
Short name T325
Test name
Test status
Simulation time 148810081 ps
CPU time 5.08 seconds
Started Jul 15 07:02:17 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 198588 kb
Host smart-1e074379-6b40-4708-b57d-ad298ebe49bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257835493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2257835493
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.571315779
Short name T466
Test name
Test status
Simulation time 161187756 ps
CPU time 0.76 seconds
Started Jul 15 07:02:17 PM PDT 24
Finished Jul 15 07:02:18 PM PDT 24
Peak memory 196572 kb
Host smart-7d55cb47-e48b-42b4-9658-78899820aa4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571315779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.571315779
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1106153217
Short name T217
Test name
Test status
Simulation time 50476703 ps
CPU time 1.39 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:21 PM PDT 24
Peak memory 197300 kb
Host smart-1860f297-51f2-4a10-b4d1-cb4a9d3a7b27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106153217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1106153217
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.42936845
Short name T399
Test name
Test status
Simulation time 63940803 ps
CPU time 2.54 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 197868 kb
Host smart-8ec123e6-2c38-40d1-a254-f8632905041c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.gpio_intr_with_filter_rand_intr_event.42936845
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3531974112
Short name T405
Test name
Test status
Simulation time 46377338 ps
CPU time 1.52 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 197336 kb
Host smart-5f8bb08d-f0ce-48dc-909d-230c243470d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531974112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3531974112
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1426352431
Short name T705
Test name
Test status
Simulation time 31774481 ps
CPU time 0.88 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 196796 kb
Host smart-75573078-5d14-409c-9138-fe1abe483acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426352431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1426352431
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2199155473
Short name T13
Test name
Test status
Simulation time 55100088 ps
CPU time 1.16 seconds
Started Jul 15 07:02:22 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 197220 kb
Host smart-1a3d965f-e256-4ae3-897a-de4bbf7cff93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199155473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2199155473
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3784998968
Short name T511
Test name
Test status
Simulation time 237985453 ps
CPU time 3.6 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 198672 kb
Host smart-27b4f052-eccc-4a70-b733-a4e390294779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784998968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3784998968
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1333564727
Short name T315
Test name
Test status
Simulation time 58879025 ps
CPU time 1.01 seconds
Started Jul 15 07:02:21 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 196964 kb
Host smart-e9f766bf-ceb1-4ac4-a52c-5ccf04594959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333564727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1333564727
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1881925439
Short name T227
Test name
Test status
Simulation time 1038781537 ps
CPU time 1.37 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:02:26 PM PDT 24
Peak memory 197876 kb
Host smart-1b4fe276-64bd-4952-bbb7-37d0285f4fe0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881925439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1881925439
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2744475937
Short name T488
Test name
Test status
Simulation time 13922420633 ps
CPU time 204.83 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 198796 kb
Host smart-a153e1cd-0c6a-46ff-a7f8-3e87578a3f75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744475937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2744475937
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2019627672
Short name T551
Test name
Test status
Simulation time 301071407982 ps
CPU time 1483.47 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:27:04 PM PDT 24
Peak memory 198956 kb
Host smart-95f38ff7-fa53-4dae-94a9-5d9379234601
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2019627672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2019627672
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1099447564
Short name T612
Test name
Test status
Simulation time 11102065 ps
CPU time 0.58 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 195300 kb
Host smart-8ac1595e-5c82-4ee6-8ff3-e60096cf71c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099447564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1099447564
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1666815245
Short name T329
Test name
Test status
Simulation time 52908517 ps
CPU time 0.74 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 194828 kb
Host smart-c84a1c6b-81fc-429f-a2f3-c9243eeb53fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666815245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1666815245
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2149432270
Short name T656
Test name
Test status
Simulation time 701467675 ps
CPU time 24.45 seconds
Started Jul 15 07:02:17 PM PDT 24
Finished Jul 15 07:02:42 PM PDT 24
Peak memory 197580 kb
Host smart-0330c626-e6dc-4a3f-b661-7027f94b9e82
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149432270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2149432270
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.850177005
Short name T38
Test name
Test status
Simulation time 125607743 ps
CPU time 0.91 seconds
Started Jul 15 07:02:18 PM PDT 24
Finished Jul 15 07:02:20 PM PDT 24
Peak memory 196740 kb
Host smart-c383cee5-f9df-4c69-9efa-70fdd8e9cab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850177005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.850177005
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2387138306
Short name T249
Test name
Test status
Simulation time 100198548 ps
CPU time 1.42 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 198760 kb
Host smart-c4d90127-9d7d-4b95-955f-8eeb8391a07e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387138306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2387138306
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.795318128
Short name T453
Test name
Test status
Simulation time 33128174 ps
CPU time 1.42 seconds
Started Jul 15 07:02:21 PM PDT 24
Finished Jul 15 07:02:23 PM PDT 24
Peak memory 198556 kb
Host smart-37880dce-563e-497b-9a98-d358501bfa1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795318128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.795318128
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2293931041
Short name T514
Test name
Test status
Simulation time 151255397 ps
CPU time 2.87 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 197888 kb
Host smart-a0bbd883-2483-44d0-9342-2bc5c8815751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293931041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2293931041
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.361369196
Short name T673
Test name
Test status
Simulation time 128756139 ps
CPU time 0.98 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:02:26 PM PDT 24
Peak memory 196728 kb
Host smart-a183e95b-1514-487e-8643-230a38564c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361369196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.361369196
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3849344373
Short name T413
Test name
Test status
Simulation time 24590820 ps
CPU time 0.63 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:21 PM PDT 24
Peak memory 195120 kb
Host smart-1730f472-d1b4-4d42-a795-f79ba4da4e51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849344373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3849344373
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.955540773
Short name T272
Test name
Test status
Simulation time 330269850 ps
CPU time 4.45 seconds
Started Jul 15 07:02:23 PM PDT 24
Finished Jul 15 07:02:28 PM PDT 24
Peak memory 198684 kb
Host smart-b0ef6ada-87a7-47cf-bb49-23dec204eb77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955540773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.955540773
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3678004505
Short name T84
Test name
Test status
Simulation time 45266266 ps
CPU time 0.82 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:26 PM PDT 24
Peak memory 195828 kb
Host smart-31588951-f9bb-4cdb-91d5-73f087d777fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678004505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3678004505
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2034516280
Short name T332
Test name
Test status
Simulation time 175413227 ps
CPU time 1.03 seconds
Started Jul 15 07:02:23 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 196520 kb
Host smart-eadeca17-c9b1-4195-b61d-592a8804d93c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034516280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2034516280
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3262113858
Short name T495
Test name
Test status
Simulation time 18084381622 ps
CPU time 115.06 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:04:15 PM PDT 24
Peak memory 198740 kb
Host smart-45013599-6216-4fe3-a48f-333507d8fa93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262113858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3262113858
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2033142763
Short name T636
Test name
Test status
Simulation time 177963695 ps
CPU time 0.59 seconds
Started Jul 15 07:02:32 PM PDT 24
Finished Jul 15 07:02:33 PM PDT 24
Peak memory 194852 kb
Host smart-d468aa53-de82-44e3-aca5-4a09cbf8ab6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033142763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2033142763
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2561001553
Short name T567
Test name
Test status
Simulation time 79913671 ps
CPU time 0.94 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:02:25 PM PDT 24
Peak memory 197976 kb
Host smart-111e3496-b6ed-42a8-9614-5888baa6aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561001553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2561001553
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2728262737
Short name T275
Test name
Test status
Simulation time 324943669 ps
CPU time 11.2 seconds
Started Jul 15 07:02:26 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 197640 kb
Host smart-e86b1519-7891-4deb-af29-d0692ce2b338
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728262737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2728262737
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.206646713
Short name T669
Test name
Test status
Simulation time 136751305 ps
CPU time 0.71 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:02:31 PM PDT 24
Peak memory 197160 kb
Host smart-a3c46bec-e6fc-4ea8-85e0-d2e46b6c45d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206646713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.206646713
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1455635580
Short name T143
Test name
Test status
Simulation time 464981692 ps
CPU time 1.41 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:28 PM PDT 24
Peak memory 198712 kb
Host smart-47a6a7a2-e47c-45f1-a95d-8e12219893b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455635580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1455635580
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3815329766
Short name T404
Test name
Test status
Simulation time 87256855 ps
CPU time 3.26 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:29 PM PDT 24
Peak memory 196960 kb
Host smart-d95ad711-76a4-4b31-895f-eef0afa208d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815329766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3815329766
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1722451803
Short name T299
Test name
Test status
Simulation time 475589114 ps
CPU time 3.52 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:02:28 PM PDT 24
Peak memory 197604 kb
Host smart-18b1c1e2-09d4-4dd9-a644-13468e1ce448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722451803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1722451803
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.808228067
Short name T32
Test name
Test status
Simulation time 68113374 ps
CPU time 1.3 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 197652 kb
Host smart-7c6001d4-8cd4-47d9-9f12-98ae17771c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808228067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.808228067
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3199896674
Short name T538
Test name
Test status
Simulation time 27599940 ps
CPU time 1.03 seconds
Started Jul 15 07:02:33 PM PDT 24
Finished Jul 15 07:02:34 PM PDT 24
Peak memory 196488 kb
Host smart-36c71bf8-81c6-4c3d-b8d0-fd1c07358e5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199896674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3199896674
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3911749892
Short name T599
Test name
Test status
Simulation time 159060801 ps
CPU time 2.84 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:29 PM PDT 24
Peak memory 198640 kb
Host smart-73d8d16f-e79a-47e4-a39f-75a25beba11b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911749892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3911749892
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1933750561
Short name T243
Test name
Test status
Simulation time 176538420 ps
CPU time 1.11 seconds
Started Jul 15 07:02:19 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 196448 kb
Host smart-48680db3-9591-4176-9d90-9cf7d741938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933750561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1933750561
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2440521831
Short name T244
Test name
Test status
Simulation time 66857782 ps
CPU time 1.18 seconds
Started Jul 15 07:02:20 PM PDT 24
Finished Jul 15 07:02:22 PM PDT 24
Peak memory 196940 kb
Host smart-3f06403e-5f88-4842-b367-d7e67df96e02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440521831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2440521831
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1936237674
Short name T600
Test name
Test status
Simulation time 5512603395 ps
CPU time 141.25 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:04:52 PM PDT 24
Peak memory 198792 kb
Host smart-b6d53e99-6062-45eb-8ad2-db01f9f2280f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936237674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1936237674
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2068285170
Short name T631
Test name
Test status
Simulation time 29522823 ps
CPU time 0.6 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:27 PM PDT 24
Peak memory 195356 kb
Host smart-c5c60f47-be7f-4618-a7f8-64f46f215803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068285170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2068285170
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1136217253
Short name T624
Test name
Test status
Simulation time 66909650 ps
CPU time 0.83 seconds
Started Jul 15 07:02:23 PM PDT 24
Finished Jul 15 07:02:24 PM PDT 24
Peak memory 196644 kb
Host smart-05af15c0-9689-4fa9-a718-83252fd8f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136217253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1136217253
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1062649350
Short name T558
Test name
Test status
Simulation time 244267928 ps
CPU time 5.66 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:32 PM PDT 24
Peak memory 197380 kb
Host smart-3ff3ad6d-7d5d-4a91-bf91-8eac3f9eda77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062649350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1062649350
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.597137963
Short name T607
Test name
Test status
Simulation time 58459516 ps
CPU time 0.67 seconds
Started Jul 15 07:02:33 PM PDT 24
Finished Jul 15 07:02:34 PM PDT 24
Peak memory 195204 kb
Host smart-3ecc8edb-aec5-4cf3-abfe-ff8d12d68d4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597137963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.597137963
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3106405153
Short name T126
Test name
Test status
Simulation time 57976996 ps
CPU time 0.76 seconds
Started Jul 15 07:02:26 PM PDT 24
Finished Jul 15 07:02:27 PM PDT 24
Peak memory 196220 kb
Host smart-ed6d1c0f-1a40-4588-a6ea-79e595b2d863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106405153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3106405153
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2412783047
Short name T470
Test name
Test status
Simulation time 235316497 ps
CPU time 1.7 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:27 PM PDT 24
Peak memory 197288 kb
Host smart-c31291be-52ca-4b81-9f71-dcdc8be8899e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412783047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2412783047
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1351495896
Short name T270
Test name
Test status
Simulation time 139870053 ps
CPU time 3.17 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:30 PM PDT 24
Peak memory 197916 kb
Host smart-7f7b41cc-c4aa-4c39-9c54-21591639f9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351495896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1351495896
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2307317573
Short name T235
Test name
Test status
Simulation time 590991472 ps
CPU time 1.38 seconds
Started Jul 15 07:02:26 PM PDT 24
Finished Jul 15 07:02:28 PM PDT 24
Peak memory 198704 kb
Host smart-ff8ea990-982d-489a-900c-d33765f54f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307317573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2307317573
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.912125736
Short name T578
Test name
Test status
Simulation time 59770994 ps
CPU time 0.99 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:27 PM PDT 24
Peak memory 196460 kb
Host smart-3269bab0-05d1-4fa9-83bb-5077498415fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912125736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.912125736
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1209093679
Short name T548
Test name
Test status
Simulation time 233175779 ps
CPU time 1.41 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:02:26 PM PDT 24
Peak memory 198632 kb
Host smart-372727e5-7c49-4446-a446-3df06a1ad5f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209093679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1209093679
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3515021691
Short name T684
Test name
Test status
Simulation time 377658177 ps
CPU time 1.09 seconds
Started Jul 15 07:02:32 PM PDT 24
Finished Jul 15 07:02:34 PM PDT 24
Peak memory 196468 kb
Host smart-9dc8b11e-b817-4ab3-a22d-3039778225ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515021691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3515021691
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3600403918
Short name T320
Test name
Test status
Simulation time 241173582 ps
CPU time 1.28 seconds
Started Jul 15 07:02:26 PM PDT 24
Finished Jul 15 07:02:28 PM PDT 24
Peak memory 197552 kb
Host smart-7a5c1d42-77e4-41cb-815d-934547649b31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600403918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3600403918
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3068390585
Short name T455
Test name
Test status
Simulation time 3870319689 ps
CPU time 98.66 seconds
Started Jul 15 07:02:24 PM PDT 24
Finished Jul 15 07:04:03 PM PDT 24
Peak memory 198772 kb
Host smart-b9483be8-4ea1-4b2b-abd9-83d5e926d2fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068390585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3068390585
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.601280450
Short name T590
Test name
Test status
Simulation time 37341992 ps
CPU time 0.59 seconds
Started Jul 15 07:00:25 PM PDT 24
Finished Jul 15 07:00:26 PM PDT 24
Peak memory 195540 kb
Host smart-ceedf88b-3eb8-4216-bbcc-0f02260624d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601280450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.601280450
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.231942047
Short name T688
Test name
Test status
Simulation time 19856009 ps
CPU time 0.72 seconds
Started Jul 15 07:00:27 PM PDT 24
Finished Jul 15 07:00:28 PM PDT 24
Peak memory 194832 kb
Host smart-7b7f1ba4-0191-4fad-aca6-82b389135f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231942047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.231942047
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1431314275
Short name T373
Test name
Test status
Simulation time 4086938091 ps
CPU time 21.08 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 197636 kb
Host smart-c3041d4c-f6dd-4a61-bd9f-b79c3f53cd1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431314275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1431314275
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2997509165
Short name T642
Test name
Test status
Simulation time 213145034 ps
CPU time 0.83 seconds
Started Jul 15 07:00:25 PM PDT 24
Finished Jul 15 07:00:26 PM PDT 24
Peak memory 197688 kb
Host smart-8ac007d6-4925-4aa9-bc4a-3131520ac638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997509165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2997509165
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.79204548
Short name T196
Test name
Test status
Simulation time 223568359 ps
CPU time 0.82 seconds
Started Jul 15 07:00:27 PM PDT 24
Finished Jul 15 07:00:29 PM PDT 24
Peak memory 196280 kb
Host smart-f5b06e89-e413-4f04-8f42-9706889954d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79204548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.79204548
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.387704917
Short name T625
Test name
Test status
Simulation time 44133355 ps
CPU time 1.77 seconds
Started Jul 15 07:00:33 PM PDT 24
Finished Jul 15 07:00:37 PM PDT 24
Peak memory 198720 kb
Host smart-3faa7d95-c8a6-4cd1-96a2-057fde06b1b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387704917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.387704917
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2187267293
Short name T471
Test name
Test status
Simulation time 123205799 ps
CPU time 3.49 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:36 PM PDT 24
Peak memory 197808 kb
Host smart-a550f489-eb61-4f26-b930-2b1496b6bef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187267293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2187267293
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.609597977
Short name T655
Test name
Test status
Simulation time 39519288 ps
CPU time 0.89 seconds
Started Jul 15 07:00:27 PM PDT 24
Finished Jul 15 07:00:28 PM PDT 24
Peak memory 197084 kb
Host smart-c317ca9e-ab0c-4be7-9ec1-62ebcab0366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609597977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.609597977
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3426805583
Short name T125
Test name
Test status
Simulation time 98098400 ps
CPU time 1.02 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 196660 kb
Host smart-b9721438-2a0d-4901-8562-6cc2698b9496
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426805583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3426805583
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1939371182
Short name T549
Test name
Test status
Simulation time 1671083352 ps
CPU time 4.9 seconds
Started Jul 15 07:00:26 PM PDT 24
Finished Jul 15 07:00:32 PM PDT 24
Peak memory 198652 kb
Host smart-9dcb39e6-3d1c-4fbe-b1e1-2036472a549b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939371182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1939371182
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.13887972
Short name T697
Test name
Test status
Simulation time 125438307 ps
CPU time 1.28 seconds
Started Jul 15 07:00:25 PM PDT 24
Finished Jul 15 07:00:26 PM PDT 24
Peak memory 196532 kb
Host smart-e8a328f2-c653-4587-916d-36b1932ad615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13887972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.13887972
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.4272450561
Short name T499
Test name
Test status
Simulation time 48331589 ps
CPU time 1.15 seconds
Started Jul 15 07:00:27 PM PDT 24
Finished Jul 15 07:00:28 PM PDT 24
Peak memory 196496 kb
Host smart-6805749f-6328-46e7-bcea-2255cb21db02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272450561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.4272450561
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1159506217
Short name T591
Test name
Test status
Simulation time 2848337263 ps
CPU time 20.29 seconds
Started Jul 15 07:00:26 PM PDT 24
Finished Jul 15 07:00:47 PM PDT 24
Peak memory 198784 kb
Host smart-76a6d278-beeb-42eb-ae60-a1b5a7927a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159506217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1159506217
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3361875945
Short name T579
Test name
Test status
Simulation time 47224508 ps
CPU time 0.58 seconds
Started Jul 15 07:00:33 PM PDT 24
Finished Jul 15 07:00:35 PM PDT 24
Peak memory 194836 kb
Host smart-f2f772aa-7bfc-4033-a9e1-ace41dabada7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361875945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3361875945
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3840637262
Short name T194
Test name
Test status
Simulation time 294960183 ps
CPU time 0.87 seconds
Started Jul 15 07:00:35 PM PDT 24
Finished Jul 15 07:00:36 PM PDT 24
Peak memory 196616 kb
Host smart-3309811e-bd57-48d6-98e1-bab160f980a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840637262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3840637262
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.374842960
Short name T507
Test name
Test status
Simulation time 455815572 ps
CPU time 21.37 seconds
Started Jul 15 07:00:31 PM PDT 24
Finished Jul 15 07:00:53 PM PDT 24
Peak memory 197444 kb
Host smart-ca491ccb-da71-4710-b9cc-dfae2dc25f76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374842960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.374842960
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.866079242
Short name T620
Test name
Test status
Simulation time 75691701 ps
CPU time 0.67 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:33 PM PDT 24
Peak memory 195828 kb
Host smart-05927995-625c-4ef5-b5eb-97d4fa3777d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866079242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.866079242
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1623836091
Short name T704
Test name
Test status
Simulation time 210284764 ps
CPU time 1.15 seconds
Started Jul 15 07:00:39 PM PDT 24
Finished Jul 15 07:00:40 PM PDT 24
Peak memory 196680 kb
Host smart-2c9f1069-8b4c-4b77-a829-2be6b33c17ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623836091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1623836091
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2447497090
Short name T257
Test name
Test status
Simulation time 59699112 ps
CPU time 1.61 seconds
Started Jul 15 07:00:34 PM PDT 24
Finished Jul 15 07:00:36 PM PDT 24
Peak memory 198708 kb
Host smart-e87aaa6b-0690-4df4-968c-e40fa87140d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447497090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2447497090
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.405985168
Short name T411
Test name
Test status
Simulation time 96706395 ps
CPU time 2.93 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:00:40 PM PDT 24
Peak memory 197812 kb
Host smart-6741f49c-5307-4193-af93-d530a35bd288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405985168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.405985168
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2694298148
Short name T246
Test name
Test status
Simulation time 102071991 ps
CPU time 1.13 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 197352 kb
Host smart-aa63377a-1606-4322-9cac-140309c39a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694298148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2694298148
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3148881699
Short name T565
Test name
Test status
Simulation time 146110312 ps
CPU time 1.38 seconds
Started Jul 15 07:00:33 PM PDT 24
Finished Jul 15 07:00:35 PM PDT 24
Peak memory 197684 kb
Host smart-ae65d4a1-f821-47fe-836e-bee86548c431
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148881699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3148881699
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3598584654
Short name T667
Test name
Test status
Simulation time 159630010 ps
CPU time 1.64 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:35 PM PDT 24
Peak memory 198464 kb
Host smart-9f525abc-c8cd-4dc6-86fe-6667557d1e8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598584654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3598584654
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2470440765
Short name T222
Test name
Test status
Simulation time 173284127 ps
CPU time 1.29 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:35 PM PDT 24
Peak memory 198716 kb
Host smart-fd0aa865-1b3b-4ec4-a936-17882bbaa5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470440765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2470440765
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2538773249
Short name T408
Test name
Test status
Simulation time 395496835 ps
CPU time 0.95 seconds
Started Jul 15 07:00:31 PM PDT 24
Finished Jul 15 07:00:33 PM PDT 24
Peak memory 196400 kb
Host smart-61ec8342-eeb6-419c-85f5-9ac32a269852
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538773249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2538773249
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1392840295
Short name T504
Test name
Test status
Simulation time 8308007097 ps
CPU time 60.89 seconds
Started Jul 15 07:00:34 PM PDT 24
Finished Jul 15 07:01:36 PM PDT 24
Peak memory 198764 kb
Host smart-65a79abe-096a-4bdd-892a-b2cfcaa05b24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392840295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1392840295
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1622567670
Short name T73
Test name
Test status
Simulation time 290398681052 ps
CPU time 2516.53 seconds
Started Jul 15 07:00:33 PM PDT 24
Finished Jul 15 07:42:31 PM PDT 24
Peak memory 198928 kb
Host smart-7ac47d05-56cb-4640-9e08-25a94ba41a30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1622567670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1622567670
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.97417783
Short name T120
Test name
Test status
Simulation time 21352040 ps
CPU time 0.57 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 194648 kb
Host smart-5d9acd9f-9e05-45a1-9971-bf6f1c28ec72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97417783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.97417783
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.545027833
Short name T293
Test name
Test status
Simulation time 188172524 ps
CPU time 0.68 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 194700 kb
Host smart-e632dcbc-d93b-48e0-a9b8-6e4c809f049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545027833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.545027833
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1552239904
Short name T675
Test name
Test status
Simulation time 818346975 ps
CPU time 24.1 seconds
Started Jul 15 07:00:32 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 196144 kb
Host smart-5b80a2bd-cef5-4e6a-9450-6ffe38901a56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552239904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1552239904
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1630425856
Short name T136
Test name
Test status
Simulation time 28725520 ps
CPU time 0.66 seconds
Started Jul 15 07:00:34 PM PDT 24
Finished Jul 15 07:00:35 PM PDT 24
Peak memory 195304 kb
Host smart-fb189a05-1b81-4ca4-b291-e272e7e863c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630425856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1630425856
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1680813199
Short name T442
Test name
Test status
Simulation time 99999091 ps
CPU time 1.04 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:00:39 PM PDT 24
Peak memory 196756 kb
Host smart-591ddeca-52e0-4ebb-80ba-2f629c29d1a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680813199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1680813199
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.744025437
Short name T274
Test name
Test status
Simulation time 83358263 ps
CPU time 1.11 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:00:39 PM PDT 24
Peak memory 198008 kb
Host smart-2ba5505b-8ced-4a11-8a66-0c4b1ed6e333
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744025437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.744025437
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1659973789
Short name T596
Test name
Test status
Simulation time 367103100 ps
CPU time 2.94 seconds
Started Jul 15 07:00:31 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 197756 kb
Host smart-574143e6-7eaf-4b5b-b8b0-c364b76ab3e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659973789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1659973789
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.681603212
Short name T403
Test name
Test status
Simulation time 190601286 ps
CPU time 0.97 seconds
Started Jul 15 07:00:35 PM PDT 24
Finished Jul 15 07:00:37 PM PDT 24
Peak memory 196488 kb
Host smart-c3a92768-2d65-475d-9056-ceb2c2e3ae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681603212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.681603212
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2374509073
Short name T402
Test name
Test status
Simulation time 68234297 ps
CPU time 0.77 seconds
Started Jul 15 07:00:31 PM PDT 24
Finished Jul 15 07:00:32 PM PDT 24
Peak memory 196668 kb
Host smart-b5bcbc6f-7482-494d-b5dd-734712688994
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374509073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2374509073
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2268963081
Short name T12
Test name
Test status
Simulation time 247792602 ps
CPU time 5.74 seconds
Started Jul 15 07:00:35 PM PDT 24
Finished Jul 15 07:00:42 PM PDT 24
Peak memory 198660 kb
Host smart-6ae78495-f1ac-471b-ae78-1cfa5392545d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268963081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2268963081
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3120460943
Short name T424
Test name
Test status
Simulation time 129626945 ps
CPU time 1.22 seconds
Started Jul 15 07:00:38 PM PDT 24
Finished Jul 15 07:00:40 PM PDT 24
Peak memory 197232 kb
Host smart-2d58b7c2-5c05-47ef-ab4e-fde6802eb89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120460943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3120460943
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.710520187
Short name T525
Test name
Test status
Simulation time 167234104 ps
CPU time 1.25 seconds
Started Jul 15 07:00:33 PM PDT 24
Finished Jul 15 07:00:36 PM PDT 24
Peak memory 197568 kb
Host smart-e63ae94b-55a7-4967-8afa-49d1eef284d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710520187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.710520187
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.465088366
Short name T670
Test name
Test status
Simulation time 23410616856 ps
CPU time 124.89 seconds
Started Jul 15 07:00:30 PM PDT 24
Finished Jul 15 07:02:36 PM PDT 24
Peak memory 198768 kb
Host smart-b0721610-7b12-4d8d-ad42-e66f1cb5aa0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465088366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.465088366
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3047157550
Short name T282
Test name
Test status
Simulation time 33574922 ps
CPU time 0.58 seconds
Started Jul 15 07:00:40 PM PDT 24
Finished Jul 15 07:00:41 PM PDT 24
Peak memory 194636 kb
Host smart-c060a21e-05e6-4a80-b6ff-560679f51a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047157550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3047157550
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2015995132
Short name T285
Test name
Test status
Simulation time 16733011 ps
CPU time 0.61 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:00:38 PM PDT 24
Peak memory 195216 kb
Host smart-0e36c79e-605f-48f2-82df-558335b7d7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015995132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2015995132
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1166626889
Short name T314
Test name
Test status
Simulation time 812119134 ps
CPU time 13.01 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:00:51 PM PDT 24
Peak memory 196120 kb
Host smart-2365c97a-c78f-4707-b446-56a033698a88
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166626889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1166626889
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.490566571
Short name T509
Test name
Test status
Simulation time 85001067 ps
CPU time 0.95 seconds
Started Jul 15 07:00:38 PM PDT 24
Finished Jul 15 07:00:39 PM PDT 24
Peak memory 197872 kb
Host smart-ae4ef17b-c44c-4166-ad68-770b97c4ee23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490566571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.490566571
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3042986179
Short name T277
Test name
Test status
Simulation time 253743046 ps
CPU time 1.43 seconds
Started Jul 15 07:00:39 PM PDT 24
Finished Jul 15 07:00:41 PM PDT 24
Peak memory 198752 kb
Host smart-61c691bb-ef1e-43dc-b36b-83052ada3d06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042986179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3042986179
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.39958609
Short name T22
Test name
Test status
Simulation time 31403941 ps
CPU time 1.36 seconds
Started Jul 15 07:00:36 PM PDT 24
Finished Jul 15 07:00:38 PM PDT 24
Peak memory 198692 kb
Host smart-41eb19fe-58a8-410c-9554-5a084498c764
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39958609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.gpio_intr_with_filter_rand_intr_event.39958609
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3502460498
Short name T238
Test name
Test status
Simulation time 29190762 ps
CPU time 0.96 seconds
Started Jul 15 07:00:38 PM PDT 24
Finished Jul 15 07:00:39 PM PDT 24
Peak memory 195160 kb
Host smart-d82642a1-5fbb-40e2-a78e-e74b719c516c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502460498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3502460498
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3072380622
Short name T518
Test name
Test status
Simulation time 173995964 ps
CPU time 1.12 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:00:38 PM PDT 24
Peak memory 197484 kb
Host smart-26be15cb-5844-4ccc-9da7-011111468a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072380622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3072380622
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2069253294
Short name T661
Test name
Test status
Simulation time 29849531 ps
CPU time 1.17 seconds
Started Jul 15 07:00:39 PM PDT 24
Finished Jul 15 07:00:41 PM PDT 24
Peak memory 196828 kb
Host smart-fc436f96-4d73-433b-b959-02d5db9cc80f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069253294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2069253294
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3939650480
Short name T407
Test name
Test status
Simulation time 538797785 ps
CPU time 5.4 seconds
Started Jul 15 07:00:42 PM PDT 24
Finished Jul 15 07:00:48 PM PDT 24
Peak memory 198648 kb
Host smart-bb7a369b-1988-4abc-b127-b953d1bc1f89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939650480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3939650480
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3022741245
Short name T328
Test name
Test status
Simulation time 37765278 ps
CPU time 1.22 seconds
Started Jul 15 07:00:35 PM PDT 24
Finished Jul 15 07:00:37 PM PDT 24
Peak memory 197296 kb
Host smart-5fe86fb0-de18-4728-a4af-4127dd5b2630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022741245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3022741245
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1945629042
Short name T247
Test name
Test status
Simulation time 199214150 ps
CPU time 1.03 seconds
Started Jul 15 07:00:39 PM PDT 24
Finished Jul 15 07:00:40 PM PDT 24
Peak memory 196260 kb
Host smart-d9845b8b-0969-4f16-850d-e955b514c363
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945629042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1945629042
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1206860690
Short name T1
Test name
Test status
Simulation time 17833972019 ps
CPU time 45.38 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:01:30 PM PDT 24
Peak memory 198840 kb
Host smart-548a13a2-c38a-4ea8-999c-11ef27bb0d1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206860690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1206860690
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4220421752
Short name T219
Test name
Test status
Simulation time 11365434 ps
CPU time 0.56 seconds
Started Jul 15 07:00:38 PM PDT 24
Finished Jul 15 07:00:39 PM PDT 24
Peak memory 194628 kb
Host smart-80caac51-98bf-4e83-aeaa-16002705747f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220421752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4220421752
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1467783307
Short name T459
Test name
Test status
Simulation time 100516480 ps
CPU time 0.79 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:46 PM PDT 24
Peak memory 196660 kb
Host smart-97210b23-197a-4470-98d5-f550ad105c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467783307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1467783307
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1050831355
Short name T170
Test name
Test status
Simulation time 6509331269 ps
CPU time 25.68 seconds
Started Jul 15 07:00:36 PM PDT 24
Finished Jul 15 07:01:03 PM PDT 24
Peak memory 198128 kb
Host smart-b0509cec-48e2-4225-a34b-53e0ff7a8f72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050831355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1050831355
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1011855008
Short name T360
Test name
Test status
Simulation time 145898893 ps
CPU time 0.95 seconds
Started Jul 15 07:00:40 PM PDT 24
Finished Jul 15 07:00:41 PM PDT 24
Peak memory 197632 kb
Host smart-83e49c88-e587-4691-83fe-b5c4c0e4d546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011855008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1011855008
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1949272562
Short name T23
Test name
Test status
Simulation time 84848346 ps
CPU time 0.68 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:45 PM PDT 24
Peak memory 195000 kb
Host smart-ea443b7c-a380-4388-8cb0-8f4345dedb67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949272562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1949272562
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3341526829
Short name T260
Test name
Test status
Simulation time 44342393 ps
CPU time 1.14 seconds
Started Jul 15 07:00:43 PM PDT 24
Finished Jul 15 07:00:46 PM PDT 24
Peak memory 197880 kb
Host smart-ed9cfb81-a345-4516-8832-70baaa4db3f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341526829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3341526829
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1432416399
Short name T436
Test name
Test status
Simulation time 692003780 ps
CPU time 3.37 seconds
Started Jul 15 07:00:42 PM PDT 24
Finished Jul 15 07:00:46 PM PDT 24
Peak memory 198020 kb
Host smart-ba7e270e-3460-4cde-a371-73db0e943398
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432416399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1432416399
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2993214238
Short name T717
Test name
Test status
Simulation time 45641162 ps
CPU time 0.75 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:00:38 PM PDT 24
Peak memory 196784 kb
Host smart-fe062ba6-cf35-412b-b044-acfbdc69a7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993214238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2993214238
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2780296064
Short name T288
Test name
Test status
Simulation time 51237104 ps
CPU time 1.13 seconds
Started Jul 15 07:00:39 PM PDT 24
Finished Jul 15 07:00:41 PM PDT 24
Peak memory 196776 kb
Host smart-8594bb3a-1715-4223-973f-e94f4ddce43b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780296064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2780296064
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1520408354
Short name T8
Test name
Test status
Simulation time 302011343 ps
CPU time 1.28 seconds
Started Jul 15 07:00:42 PM PDT 24
Finished Jul 15 07:00:44 PM PDT 24
Peak memory 198692 kb
Host smart-44de3ca2-d907-44e0-b4c7-1e2592a74164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520408354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1520408354
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2178083717
Short name T506
Test name
Test status
Simulation time 1286555114 ps
CPU time 1.2 seconds
Started Jul 15 07:00:40 PM PDT 24
Finished Jul 15 07:00:42 PM PDT 24
Peak memory 197204 kb
Host smart-ab0d963b-6881-4433-bcb8-0d5550daf908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178083717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2178083717
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3930806430
Short name T581
Test name
Test status
Simulation time 55714575 ps
CPU time 1.14 seconds
Started Jul 15 07:00:38 PM PDT 24
Finished Jul 15 07:00:40 PM PDT 24
Peak memory 196488 kb
Host smart-f23e842a-8e40-4653-ac3c-1be41b4b2a0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930806430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3930806430
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3586412050
Short name T118
Test name
Test status
Simulation time 21616017536 ps
CPU time 46.89 seconds
Started Jul 15 07:00:37 PM PDT 24
Finished Jul 15 07:01:25 PM PDT 24
Peak memory 198780 kb
Host smart-266ae0d9-ffae-4a65-aadd-18ff7bbf8eb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586412050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3586412050
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3611734456
Short name T112
Test name
Test status
Simulation time 33496776439 ps
CPU time 489.58 seconds
Started Jul 15 07:00:40 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 198948 kb
Host smart-5eae573b-8f89-41a8-b13e-20bbb9fd0229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3611734456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3611734456
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2140420900
Short name T871
Test name
Test status
Simulation time 99663827 ps
CPU time 0.84 seconds
Started Jul 15 06:43:57 PM PDT 24
Finished Jul 15 06:43:59 PM PDT 24
Peak memory 196636 kb
Host smart-d531fd81-1a36-4c2b-970c-9c0a4bf91730
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2140420900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2140420900
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3747473303
Short name T845
Test name
Test status
Simulation time 32859622 ps
CPU time 0.84 seconds
Started Jul 15 06:43:56 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 196588 kb
Host smart-32aa999f-6e7b-4bb0-9188-05f6c4d85733
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747473303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3747473303
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.204342654
Short name T912
Test name
Test status
Simulation time 103393834 ps
CPU time 1 seconds
Started Jul 15 06:43:56 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 197080 kb
Host smart-dd314228-63a7-47b9-89e8-cfeb85c84196
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=204342654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.204342654
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912741242
Short name T869
Test name
Test status
Simulation time 154416131 ps
CPU time 1.11 seconds
Started Jul 15 06:43:57 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 198448 kb
Host smart-1d665445-7212-423b-ab5c-d93f58c1813b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912741242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2912741242
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3976159198
Short name T920
Test name
Test status
Simulation time 182173168 ps
CPU time 1.41 seconds
Started Jul 15 06:44:07 PM PDT 24
Finished Jul 15 06:44:09 PM PDT 24
Peak memory 196992 kb
Host smart-207254a3-3fc4-4388-82fb-a04881ae1655
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3976159198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3976159198
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1031076493
Short name T868
Test name
Test status
Simulation time 67696223 ps
CPU time 0.85 seconds
Started Jul 15 06:44:03 PM PDT 24
Finished Jul 15 06:44:04 PM PDT 24
Peak memory 195864 kb
Host smart-d96f4764-926b-4d75-8716-6d19c2af27e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031076493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1031076493
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2978338375
Short name T929
Test name
Test status
Simulation time 129938773 ps
CPU time 1.4 seconds
Started Jul 15 06:44:12 PM PDT 24
Finished Jul 15 06:44:14 PM PDT 24
Peak memory 197236 kb
Host smart-a328607b-b8b0-4379-be01-5cbc8f9189db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978338375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2978338375
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2199771900
Short name T916
Test name
Test status
Simulation time 51504590 ps
CPU time 1.45 seconds
Started Jul 15 06:44:02 PM PDT 24
Finished Jul 15 06:44:04 PM PDT 24
Peak memory 196988 kb
Host smart-afbdf209-eba8-4c5b-8732-6687d2ebb40f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199771900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2199771900
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2328573269
Short name T876
Test name
Test status
Simulation time 150120190 ps
CPU time 1.47 seconds
Started Jul 15 06:44:03 PM PDT 24
Finished Jul 15 06:44:05 PM PDT 24
Peak memory 197184 kb
Host smart-ac38ec2b-ccca-4030-bc12-f148c1b381d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2328573269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2328573269
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348316047
Short name T907
Test name
Test status
Simulation time 187418660 ps
CPU time 0.98 seconds
Started Jul 15 06:44:02 PM PDT 24
Finished Jul 15 06:44:04 PM PDT 24
Peak memory 198260 kb
Host smart-0a7a229f-b3a9-4a06-800e-a97cc7402f7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348316047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1348316047
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1073452983
Short name T862
Test name
Test status
Simulation time 68977697 ps
CPU time 0.89 seconds
Started Jul 15 06:44:03 PM PDT 24
Finished Jul 15 06:44:04 PM PDT 24
Peak memory 196536 kb
Host smart-e214330c-cf26-4e7b-87ab-ed4c34ca81ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1073452983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1073452983
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2072359312
Short name T921
Test name
Test status
Simulation time 543661035 ps
CPU time 1.11 seconds
Started Jul 15 06:44:01 PM PDT 24
Finished Jul 15 06:44:02 PM PDT 24
Peak memory 196804 kb
Host smart-6ba4afff-90ba-4aac-af0f-797c0803b24a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072359312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2072359312
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4143667683
Short name T932
Test name
Test status
Simulation time 256699453 ps
CPU time 1.2 seconds
Started Jul 15 06:44:03 PM PDT 24
Finished Jul 15 06:44:05 PM PDT 24
Peak memory 196108 kb
Host smart-10e723d7-a6f0-4274-b50a-93febaae6d18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4143667683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4143667683
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4232934001
Short name T877
Test name
Test status
Simulation time 324396389 ps
CPU time 1.1 seconds
Started Jul 15 06:44:02 PM PDT 24
Finished Jul 15 06:44:04 PM PDT 24
Peak memory 197884 kb
Host smart-dfa68544-ab06-4d30-8f57-9361043eb293
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232934001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4232934001
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2459968295
Short name T860
Test name
Test status
Simulation time 145715326 ps
CPU time 1.12 seconds
Started Jul 15 06:44:03 PM PDT 24
Finished Jul 15 06:44:05 PM PDT 24
Peak memory 198428 kb
Host smart-39512238-5868-4e98-ab22-ec35a16cbe56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2459968295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2459968295
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2783276163
Short name T941
Test name
Test status
Simulation time 46577203 ps
CPU time 1.09 seconds
Started Jul 15 06:44:13 PM PDT 24
Finished Jul 15 06:44:15 PM PDT 24
Peak memory 197072 kb
Host smart-3405a7f2-b653-4d19-a638-598369a99075
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783276163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2783276163
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3758996506
Short name T847
Test name
Test status
Simulation time 79227540 ps
CPU time 1.27 seconds
Started Jul 15 06:44:09 PM PDT 24
Finished Jul 15 06:44:10 PM PDT 24
Peak memory 197076 kb
Host smart-d2325430-1d8b-4d8a-bf7f-78cb118801f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3758996506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3758996506
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3656012654
Short name T937
Test name
Test status
Simulation time 78413464 ps
CPU time 1.56 seconds
Started Jul 15 06:44:07 PM PDT 24
Finished Jul 15 06:44:09 PM PDT 24
Peak memory 197040 kb
Host smart-74f9e09f-19e5-426a-8b7c-5a036797fadd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656012654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3656012654
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.368528918
Short name T854
Test name
Test status
Simulation time 41496622 ps
CPU time 1.11 seconds
Started Jul 15 06:44:07 PM PDT 24
Finished Jul 15 06:44:09 PM PDT 24
Peak memory 197212 kb
Host smart-44755efb-c6c0-4c24-bf54-fb229b059218
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=368528918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.368528918
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.575888141
Short name T926
Test name
Test status
Simulation time 41604807 ps
CPU time 1.04 seconds
Started Jul 15 06:44:09 PM PDT 24
Finished Jul 15 06:44:10 PM PDT 24
Peak memory 196152 kb
Host smart-5355b115-a2a4-48d2-a1bd-cd4ccda989ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575888141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.575888141
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.256683249
Short name T865
Test name
Test status
Simulation time 97528364 ps
CPU time 1.1 seconds
Started Jul 15 06:44:07 PM PDT 24
Finished Jul 15 06:44:09 PM PDT 24
Peak memory 196896 kb
Host smart-abfd7bef-4a1d-4923-aca5-d07a6fb7e260
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=256683249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.256683249
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.794928607
Short name T851
Test name
Test status
Simulation time 186572916 ps
CPU time 1.42 seconds
Started Jul 15 06:44:13 PM PDT 24
Finished Jul 15 06:44:14 PM PDT 24
Peak memory 197224 kb
Host smart-98c973b9-28ae-4614-9f53-9d1cf15ed54c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794928607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.794928607
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.294532972
Short name T935
Test name
Test status
Simulation time 63345931 ps
CPU time 0.79 seconds
Started Jul 15 06:44:07 PM PDT 24
Finished Jul 15 06:44:08 PM PDT 24
Peak memory 195800 kb
Host smart-c1b95f11-0255-4b93-b783-ee05a39d2910
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=294532972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.294532972
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1309738812
Short name T891
Test name
Test status
Simulation time 58493516 ps
CPU time 0.81 seconds
Started Jul 15 06:44:10 PM PDT 24
Finished Jul 15 06:44:11 PM PDT 24
Peak memory 191956 kb
Host smart-2971edad-71ca-4e87-891c-8c21e3671b7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309738812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1309738812
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.572376543
Short name T875
Test name
Test status
Simulation time 56935332 ps
CPU time 1.29 seconds
Started Jul 15 06:43:59 PM PDT 24
Finished Jul 15 06:44:01 PM PDT 24
Peak memory 198420 kb
Host smart-d99b4bfe-ecfc-4d06-8344-967b9286d890
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=572376543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.572376543
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3592414303
Short name T936
Test name
Test status
Simulation time 30588320 ps
CPU time 0.95 seconds
Started Jul 15 06:43:57 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 196912 kb
Host smart-f389ef9b-2d10-411c-b992-6638d42b7430
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592414303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3592414303
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2833348517
Short name T874
Test name
Test status
Simulation time 46370479 ps
CPU time 1.08 seconds
Started Jul 15 06:44:13 PM PDT 24
Finished Jul 15 06:44:15 PM PDT 24
Peak memory 198456 kb
Host smart-d576b3ba-3b23-4b99-85dc-be528ac1c15c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2833348517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2833348517
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1352017334
Short name T913
Test name
Test status
Simulation time 62647618 ps
CPU time 1.07 seconds
Started Jul 15 06:44:05 PM PDT 24
Finished Jul 15 06:44:07 PM PDT 24
Peak memory 196208 kb
Host smart-51f44bbf-f34c-407b-9a2d-2b4ca19e5c3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352017334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1352017334
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3893958427
Short name T906
Test name
Test status
Simulation time 108973422 ps
CPU time 1.57 seconds
Started Jul 15 06:44:13 PM PDT 24
Finished Jul 15 06:44:16 PM PDT 24
Peak memory 198416 kb
Host smart-38c32044-be88-45e5-b49b-30795ec25133
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3893958427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3893958427
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1418546548
Short name T893
Test name
Test status
Simulation time 874716058 ps
CPU time 1.03 seconds
Started Jul 15 06:44:05 PM PDT 24
Finished Jul 15 06:44:06 PM PDT 24
Peak memory 196736 kb
Host smart-047fd260-8b66-43b9-a105-c92a292625bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418546548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1418546548
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1317690562
Short name T905
Test name
Test status
Simulation time 76962917 ps
CPU time 0.89 seconds
Started Jul 15 06:44:15 PM PDT 24
Finished Jul 15 06:44:17 PM PDT 24
Peak memory 198240 kb
Host smart-f466ef88-8a89-4a99-b835-66fd5fd7a848
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1317690562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1317690562
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3720962161
Short name T882
Test name
Test status
Simulation time 35183266 ps
CPU time 0.99 seconds
Started Jul 15 06:44:14 PM PDT 24
Finished Jul 15 06:44:15 PM PDT 24
Peak memory 196972 kb
Host smart-45624108-2878-4210-bd57-17172b93a1ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720962161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3720962161
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1977908067
Short name T866
Test name
Test status
Simulation time 39763355 ps
CPU time 0.82 seconds
Started Jul 15 06:44:15 PM PDT 24
Finished Jul 15 06:44:17 PM PDT 24
Peak memory 195904 kb
Host smart-3b5e95d2-1f55-4d6b-833a-c68a85b22841
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1977908067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1977908067
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1540970037
Short name T858
Test name
Test status
Simulation time 58941028 ps
CPU time 1.21 seconds
Started Jul 15 06:44:15 PM PDT 24
Finished Jul 15 06:44:17 PM PDT 24
Peak memory 196232 kb
Host smart-9593c4e7-b673-4661-a260-4484e3c80d7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540970037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1540970037
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3197537738
Short name T870
Test name
Test status
Simulation time 479821209 ps
CPU time 1.23 seconds
Started Jul 15 06:44:15 PM PDT 24
Finished Jul 15 06:44:17 PM PDT 24
Peak memory 197004 kb
Host smart-64c825c2-6645-4d6c-917d-f41120f97723
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3197537738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3197537738
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749443925
Short name T915
Test name
Test status
Simulation time 66385226 ps
CPU time 1.1 seconds
Started Jul 15 06:44:13 PM PDT 24
Finished Jul 15 06:44:14 PM PDT 24
Peak memory 197032 kb
Host smart-bf421713-395e-46b4-b0e6-17a0558dd4ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749443925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3749443925
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1449245948
Short name T944
Test name
Test status
Simulation time 342626390 ps
CPU time 1.5 seconds
Started Jul 15 06:44:13 PM PDT 24
Finished Jul 15 06:44:15 PM PDT 24
Peak memory 197044 kb
Host smart-79c12565-9205-496f-aa68-6ffc86eef03e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1449245948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1449245948
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885038328
Short name T923
Test name
Test status
Simulation time 34567949 ps
CPU time 0.97 seconds
Started Jul 15 06:44:13 PM PDT 24
Finished Jul 15 06:44:14 PM PDT 24
Peak memory 197484 kb
Host smart-9838623c-6092-4c7e-8b49-01ef733c59a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885038328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.885038328
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2939662106
Short name T914
Test name
Test status
Simulation time 272834956 ps
CPU time 1.15 seconds
Started Jul 15 06:44:14 PM PDT 24
Finished Jul 15 06:44:16 PM PDT 24
Peak memory 197944 kb
Host smart-b5700254-858f-4433-a412-76b54a9e8215
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2939662106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2939662106
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4192510740
Short name T910
Test name
Test status
Simulation time 54323438 ps
CPU time 1.11 seconds
Started Jul 15 06:44:14 PM PDT 24
Finished Jul 15 06:44:16 PM PDT 24
Peak memory 197064 kb
Host smart-188103ea-b570-4b70-a9de-a78b0126bd9c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192510740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4192510740
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2070993356
Short name T873
Test name
Test status
Simulation time 34607633 ps
CPU time 1.03 seconds
Started Jul 15 06:44:20 PM PDT 24
Finished Jul 15 06:44:21 PM PDT 24
Peak memory 196224 kb
Host smart-8318bf9a-f7a1-4bee-9bfd-69da8bcdeb7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2070993356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2070993356
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.92622261
Short name T846
Test name
Test status
Simulation time 147804085 ps
CPU time 0.85 seconds
Started Jul 15 06:44:20 PM PDT 24
Finished Jul 15 06:44:21 PM PDT 24
Peak memory 195908 kb
Host smart-e4ff427f-bcb8-4236-82a0-fb7c909eb1d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92622261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.92622261
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3019028063
Short name T883
Test name
Test status
Simulation time 321940264 ps
CPU time 1.1 seconds
Started Jul 15 06:44:18 PM PDT 24
Finished Jul 15 06:44:20 PM PDT 24
Peak memory 196224 kb
Host smart-90d1dea2-309b-43c7-88be-7dd89a90ef76
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3019028063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3019028063
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1866147242
Short name T934
Test name
Test status
Simulation time 78881842 ps
CPU time 1.46 seconds
Started Jul 15 06:44:20 PM PDT 24
Finished Jul 15 06:44:22 PM PDT 24
Peak memory 197196 kb
Host smart-de06cde9-e182-42ca-a0c1-308f325fa9ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866147242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1866147242
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1855103164
Short name T848
Test name
Test status
Simulation time 60195619 ps
CPU time 0.84 seconds
Started Jul 15 06:44:19 PM PDT 24
Finished Jul 15 06:44:20 PM PDT 24
Peak memory 195776 kb
Host smart-0c49d355-aee1-4858-9a70-e50dc1e48bfb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1855103164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1855103164
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3470304717
Short name T904
Test name
Test status
Simulation time 365742167 ps
CPU time 1.31 seconds
Started Jul 15 06:44:17 PM PDT 24
Finished Jul 15 06:44:19 PM PDT 24
Peak memory 197164 kb
Host smart-d5bd17f2-de9e-4c45-9654-a1d28c7b1c37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470304717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3470304717
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1962888593
Short name T900
Test name
Test status
Simulation time 28979900 ps
CPU time 0.99 seconds
Started Jul 15 06:43:59 PM PDT 24
Finished Jul 15 06:44:01 PM PDT 24
Peak memory 197824 kb
Host smart-e27aaf00-6c9c-42a7-9f13-f434219158f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1962888593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1962888593
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1103266339
Short name T886
Test name
Test status
Simulation time 82879278 ps
CPU time 1.29 seconds
Started Jul 15 06:43:57 PM PDT 24
Finished Jul 15 06:43:59 PM PDT 24
Peak memory 197332 kb
Host smart-f0f53fa7-d7d8-4e16-9e1e-ef79a069a159
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103266339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1103266339
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1681397360
Short name T857
Test name
Test status
Simulation time 84571645 ps
CPU time 0.9 seconds
Started Jul 15 06:44:21 PM PDT 24
Finished Jul 15 06:44:22 PM PDT 24
Peak memory 197028 kb
Host smart-c3db4145-14a4-43f4-8484-a54e25a2b38b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1681397360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1681397360
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929084320
Short name T889
Test name
Test status
Simulation time 59916768 ps
CPU time 1.21 seconds
Started Jul 15 06:44:20 PM PDT 24
Finished Jul 15 06:44:22 PM PDT 24
Peak memory 196324 kb
Host smart-5e223289-ce88-4eb9-971d-4be065e4d75c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929084320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.929084320
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.922774654
Short name T938
Test name
Test status
Simulation time 34852624 ps
CPU time 0.91 seconds
Started Jul 15 06:44:26 PM PDT 24
Finished Jul 15 06:44:28 PM PDT 24
Peak memory 195816 kb
Host smart-c492a5b0-fc8d-4097-b376-b9900b33b579
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=922774654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.922774654
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.93635839
Short name T942
Test name
Test status
Simulation time 209613117 ps
CPU time 1.02 seconds
Started Jul 15 06:44:22 PM PDT 24
Finished Jul 15 06:44:24 PM PDT 24
Peak memory 196956 kb
Host smart-7a117902-220f-4d36-a2df-37268eff340f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93635839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.93635839
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3695667757
Short name T925
Test name
Test status
Simulation time 56713771 ps
CPU time 1.26 seconds
Started Jul 15 06:44:21 PM PDT 24
Finished Jul 15 06:44:23 PM PDT 24
Peak memory 197612 kb
Host smart-ef1b54cb-913f-4323-a7a2-e01d45710678
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3695667757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3695667757
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4069050123
Short name T887
Test name
Test status
Simulation time 147704691 ps
CPU time 0.97 seconds
Started Jul 15 06:44:17 PM PDT 24
Finished Jul 15 06:44:19 PM PDT 24
Peak memory 197804 kb
Host smart-62295ef7-a8b9-4033-8226-be107b6c46a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069050123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4069050123
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.118901174
Short name T859
Test name
Test status
Simulation time 27188659 ps
CPU time 0.78 seconds
Started Jul 15 06:44:20 PM PDT 24
Finished Jul 15 06:44:21 PM PDT 24
Peak memory 194724 kb
Host smart-a6ec9a27-9708-43b7-b761-362427717498
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=118901174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.118901174
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1078777463
Short name T894
Test name
Test status
Simulation time 168523227 ps
CPU time 1.21 seconds
Started Jul 15 06:44:19 PM PDT 24
Finished Jul 15 06:44:20 PM PDT 24
Peak memory 196100 kb
Host smart-489d5297-05ce-44f8-a178-be44d2124a68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078777463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1078777463
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1103008649
Short name T903
Test name
Test status
Simulation time 41154228 ps
CPU time 0.98 seconds
Started Jul 15 06:44:24 PM PDT 24
Finished Jul 15 06:44:25 PM PDT 24
Peak memory 197052 kb
Host smart-e1114f5d-7bab-4f19-8d3b-9e3a50ddcb6c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103008649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1103008649
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3244465419
Short name T850
Test name
Test status
Simulation time 111556090 ps
CPU time 1.09 seconds
Started Jul 15 06:44:25 PM PDT 24
Finished Jul 15 06:44:27 PM PDT 24
Peak memory 197028 kb
Host smart-2ec976c9-b456-44a3-aede-e03a596a9823
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244465419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3244465419
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.176737756
Short name T867
Test name
Test status
Simulation time 137803940 ps
CPU time 1.04 seconds
Started Jul 15 06:44:27 PM PDT 24
Finished Jul 15 06:44:28 PM PDT 24
Peak memory 196932 kb
Host smart-10e76800-19b8-494e-8452-ed8f806fc462
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=176737756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.176737756
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1653422491
Short name T861
Test name
Test status
Simulation time 106293583 ps
CPU time 1.04 seconds
Started Jul 15 06:44:26 PM PDT 24
Finished Jul 15 06:44:27 PM PDT 24
Peak memory 196876 kb
Host smart-cfd1fcec-cbdf-4d32-8e29-9bc5da719d06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653422491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1653422491
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.861243359
Short name T881
Test name
Test status
Simulation time 162647148 ps
CPU time 1.31 seconds
Started Jul 15 06:44:28 PM PDT 24
Finished Jul 15 06:44:30 PM PDT 24
Peak memory 196972 kb
Host smart-ef5c2f14-5f50-4a5d-ac4e-8b54b48574b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=861243359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.861243359
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1237886720
Short name T856
Test name
Test status
Simulation time 70678911 ps
CPU time 0.71 seconds
Started Jul 15 06:44:23 PM PDT 24
Finished Jul 15 06:44:24 PM PDT 24
Peak memory 194744 kb
Host smart-e8ac4580-17c5-4f43-a259-99237a3c3071
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237886720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1237886720
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3416330405
Short name T930
Test name
Test status
Simulation time 327129134 ps
CPU time 1.26 seconds
Started Jul 15 06:44:24 PM PDT 24
Finished Jul 15 06:44:25 PM PDT 24
Peak memory 197236 kb
Host smart-0fe01b93-b602-4618-89da-c6fca3dc30b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3416330405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3416330405
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23720357
Short name T852
Test name
Test status
Simulation time 347114357 ps
CPU time 1.38 seconds
Started Jul 15 06:44:26 PM PDT 24
Finished Jul 15 06:44:27 PM PDT 24
Peak memory 197180 kb
Host smart-c6514c3c-bd9d-460d-a278-d4dab14a6358
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23720357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.23720357
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1473194320
Short name T897
Test name
Test status
Simulation time 43671653 ps
CPU time 1.36 seconds
Started Jul 15 06:44:24 PM PDT 24
Finished Jul 15 06:44:26 PM PDT 24
Peak memory 196944 kb
Host smart-aa2f85be-2da7-42e6-bf73-f14afb1f7877
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1473194320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1473194320
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1984826318
Short name T924
Test name
Test status
Simulation time 30106226 ps
CPU time 0.83 seconds
Started Jul 15 06:44:26 PM PDT 24
Finished Jul 15 06:44:27 PM PDT 24
Peak memory 196616 kb
Host smart-9889869b-5726-4857-aad6-377f30add902
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984826318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1984826318
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1100869863
Short name T931
Test name
Test status
Simulation time 142909382 ps
CPU time 0.77 seconds
Started Jul 15 06:44:24 PM PDT 24
Finished Jul 15 06:44:25 PM PDT 24
Peak memory 195744 kb
Host smart-34580a37-f94b-43a7-b4ec-9c719ddc13f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1100869863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1100869863
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863612751
Short name T901
Test name
Test status
Simulation time 32481985 ps
CPU time 0.82 seconds
Started Jul 15 06:44:28 PM PDT 24
Finished Jul 15 06:44:30 PM PDT 24
Peak memory 195788 kb
Host smart-ee43206a-c21f-4e58-87d0-f1136eb451a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863612751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2863612751
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.986061801
Short name T908
Test name
Test status
Simulation time 357568467 ps
CPU time 1.42 seconds
Started Jul 15 06:43:53 PM PDT 24
Finished Jul 15 06:43:56 PM PDT 24
Peak memory 197080 kb
Host smart-486e69e2-52f4-4460-99d8-16bc09a78099
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=986061801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.986061801
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1105897923
Short name T922
Test name
Test status
Simulation time 42917098 ps
CPU time 1.37 seconds
Started Jul 15 06:43:58 PM PDT 24
Finished Jul 15 06:44:00 PM PDT 24
Peak memory 196996 kb
Host smart-80b4436a-8166-49f7-a13c-96a2c0a9f26f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105897923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1105897923
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3212086889
Short name T878
Test name
Test status
Simulation time 50981287 ps
CPU time 1.07 seconds
Started Jul 15 06:44:23 PM PDT 24
Finished Jul 15 06:44:25 PM PDT 24
Peak memory 196820 kb
Host smart-5608ea44-f550-49c6-b50d-5ffd4710b4b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3212086889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3212086889
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2746051104
Short name T911
Test name
Test status
Simulation time 40059980 ps
CPU time 1.06 seconds
Started Jul 15 06:44:28 PM PDT 24
Finished Jul 15 06:44:29 PM PDT 24
Peak memory 197000 kb
Host smart-f1353325-e9ad-456f-bd53-3e1f1a04ff43
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746051104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2746051104
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.586841299
Short name T888
Test name
Test status
Simulation time 52120506 ps
CPU time 1.3 seconds
Started Jul 15 06:44:26 PM PDT 24
Finished Jul 15 06:44:27 PM PDT 24
Peak memory 197340 kb
Host smart-0e565b9f-a7ce-40e1-a96d-3f0d655c713c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=586841299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.586841299
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3297698981
Short name T927
Test name
Test status
Simulation time 60376199 ps
CPU time 0.95 seconds
Started Jul 15 06:44:24 PM PDT 24
Finished Jul 15 06:44:25 PM PDT 24
Peak memory 196996 kb
Host smart-4dfb5a5c-faee-48c9-99cd-992df520b8ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297698981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3297698981
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2273597773
Short name T890
Test name
Test status
Simulation time 76235559 ps
CPU time 0.78 seconds
Started Jul 15 06:44:26 PM PDT 24
Finished Jul 15 06:44:27 PM PDT 24
Peak memory 195968 kb
Host smart-f5ff21a3-0722-45d2-ae0e-1ab645759446
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2273597773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2273597773
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1150569365
Short name T863
Test name
Test status
Simulation time 78752512 ps
CPU time 1.35 seconds
Started Jul 15 06:44:29 PM PDT 24
Finished Jul 15 06:44:31 PM PDT 24
Peak memory 196960 kb
Host smart-f4bc1bb5-3495-4a57-8866-1ff68917daf6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150569365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1150569365
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1769630685
Short name T892
Test name
Test status
Simulation time 124006239 ps
CPU time 0.89 seconds
Started Jul 15 06:44:29 PM PDT 24
Finished Jul 15 06:44:30 PM PDT 24
Peak memory 196936 kb
Host smart-99266759-c45d-4046-afd2-9ee8c883941b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1769630685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1769630685
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4169824957
Short name T885
Test name
Test status
Simulation time 150357556 ps
CPU time 0.93 seconds
Started Jul 15 06:44:29 PM PDT 24
Finished Jul 15 06:44:30 PM PDT 24
Peak memory 197212 kb
Host smart-83f51671-7bb1-4190-a5ea-024b69460642
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169824957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4169824957
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.321947436
Short name T880
Test name
Test status
Simulation time 76389832 ps
CPU time 1.2 seconds
Started Jul 15 06:44:29 PM PDT 24
Finished Jul 15 06:44:31 PM PDT 24
Peak memory 197084 kb
Host smart-cfedd3e9-9510-47d2-8644-c86dfcfc9b92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=321947436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.321947436
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1294980288
Short name T919
Test name
Test status
Simulation time 47080599 ps
CPU time 1.47 seconds
Started Jul 15 06:44:28 PM PDT 24
Finished Jul 15 06:44:30 PM PDT 24
Peak memory 198480 kb
Host smart-104a90e6-de70-4dbd-87f3-991299b61348
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294980288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1294980288
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4067067838
Short name T918
Test name
Test status
Simulation time 64283622 ps
CPU time 1.18 seconds
Started Jul 15 06:44:31 PM PDT 24
Finished Jul 15 06:44:32 PM PDT 24
Peak memory 197536 kb
Host smart-2b84b374-9979-424f-90d3-67f42dfea754
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4067067838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4067067838
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2262898083
Short name T899
Test name
Test status
Simulation time 55588903 ps
CPU time 0.92 seconds
Started Jul 15 06:44:28 PM PDT 24
Finished Jul 15 06:44:29 PM PDT 24
Peak memory 195940 kb
Host smart-5a5aacdf-d1c0-4dae-91c0-4e3d4075efa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262898083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2262898083
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2627818643
Short name T933
Test name
Test status
Simulation time 272108725 ps
CPU time 1.2 seconds
Started Jul 15 06:44:32 PM PDT 24
Finished Jul 15 06:44:33 PM PDT 24
Peak memory 197036 kb
Host smart-edfc28e8-9b55-4b84-bb0c-f6171ced7ca7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2627818643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2627818643
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.967256526
Short name T939
Test name
Test status
Simulation time 182423561 ps
CPU time 1.33 seconds
Started Jul 15 06:44:29 PM PDT 24
Finished Jul 15 06:44:31 PM PDT 24
Peak memory 198404 kb
Host smart-eab5081b-fe84-40ee-8fe0-751064354a59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967256526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.967256526
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3798072327
Short name T879
Test name
Test status
Simulation time 406989563 ps
CPU time 1.5 seconds
Started Jul 15 06:44:27 PM PDT 24
Finished Jul 15 06:44:29 PM PDT 24
Peak memory 197016 kb
Host smart-26873dee-7d5d-475f-805b-b1cf28579ec1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3798072327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3798072327
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.451651106
Short name T864
Test name
Test status
Simulation time 849878343 ps
CPU time 1.07 seconds
Started Jul 15 06:44:30 PM PDT 24
Finished Jul 15 06:44:32 PM PDT 24
Peak memory 197016 kb
Host smart-f438f90f-4976-4c2c-9ccc-a9654b28d757
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451651106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.451651106
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.204655721
Short name T902
Test name
Test status
Simulation time 26188710 ps
CPU time 0.88 seconds
Started Jul 15 06:44:31 PM PDT 24
Finished Jul 15 06:44:33 PM PDT 24
Peak memory 196976 kb
Host smart-c1a784ca-ff7d-401a-b39e-7794be919250
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=204655721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.204655721
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.536486885
Short name T928
Test name
Test status
Simulation time 60006042 ps
CPU time 1.19 seconds
Started Jul 15 06:44:32 PM PDT 24
Finished Jul 15 06:44:34 PM PDT 24
Peak memory 196328 kb
Host smart-64cde99b-94e8-4248-84f7-632840a9d043
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536486885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.536486885
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1852285473
Short name T849
Test name
Test status
Simulation time 90737314 ps
CPU time 1.48 seconds
Started Jul 15 06:44:30 PM PDT 24
Finished Jul 15 06:44:32 PM PDT 24
Peak memory 197300 kb
Host smart-a4b28175-799f-4d39-b5bb-947d0cbf6d30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1852285473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1852285473
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9330251
Short name T895
Test name
Test status
Simulation time 407018192 ps
CPU time 1.06 seconds
Started Jul 15 06:44:34 PM PDT 24
Finished Jul 15 06:44:36 PM PDT 24
Peak memory 196184 kb
Host smart-b1db52cd-cb1d-4637-88b6-bdb61fa20aec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9330251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.9330251
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.261747723
Short name T896
Test name
Test status
Simulation time 233514020 ps
CPU time 1.11 seconds
Started Jul 15 06:43:55 PM PDT 24
Finished Jul 15 06:43:56 PM PDT 24
Peak memory 196292 kb
Host smart-f99dc6e4-00dd-4774-b59b-dc313fe1ef81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=261747723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.261747723
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2038640766
Short name T917
Test name
Test status
Simulation time 73559278 ps
CPU time 1.22 seconds
Started Jul 15 06:43:58 PM PDT 24
Finished Jul 15 06:44:00 PM PDT 24
Peak memory 198532 kb
Host smart-a054638d-2e94-423b-aef4-572bf8b94b42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038640766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2038640766
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2289834451
Short name T872
Test name
Test status
Simulation time 248765486 ps
CPU time 1.22 seconds
Started Jul 15 06:43:54 PM PDT 24
Finished Jul 15 06:43:56 PM PDT 24
Peak memory 196036 kb
Host smart-10bed6e7-9d00-4691-8d35-559c1410ff35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2289834451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2289834451
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1022642937
Short name T855
Test name
Test status
Simulation time 51350751 ps
CPU time 1 seconds
Started Jul 15 06:43:57 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 198376 kb
Host smart-678af961-7351-4e33-943b-21da3e5638d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022642937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1022642937
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1229951824
Short name T853
Test name
Test status
Simulation time 54687303 ps
CPU time 1.25 seconds
Started Jul 15 06:43:59 PM PDT 24
Finished Jul 15 06:44:00 PM PDT 24
Peak memory 196340 kb
Host smart-28572a79-ef45-42ce-9865-6d07eda63b86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1229951824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1229951824
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956637079
Short name T884
Test name
Test status
Simulation time 47436278 ps
CPU time 1.21 seconds
Started Jul 15 06:43:57 PM PDT 24
Finished Jul 15 06:43:59 PM PDT 24
Peak memory 196388 kb
Host smart-7de98663-7ccc-4629-9c44-3849bf5d9b3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956637079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2956637079
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2895908657
Short name T943
Test name
Test status
Simulation time 45405116 ps
CPU time 1.01 seconds
Started Jul 15 06:43:56 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 197096 kb
Host smart-34f5b22c-97c9-4abb-a81f-8a972bbdef4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2895908657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2895908657
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1043690671
Short name T940
Test name
Test status
Simulation time 114097163 ps
CPU time 1.23 seconds
Started Jul 15 06:43:56 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 197060 kb
Host smart-f8a48da6-f495-460f-930f-f72634d77816
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043690671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1043690671
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2636363261
Short name T909
Test name
Test status
Simulation time 95994087 ps
CPU time 1.11 seconds
Started Jul 15 06:43:56 PM PDT 24
Finished Jul 15 06:43:58 PM PDT 24
Peak memory 197008 kb
Host smart-cd08d68b-68d7-4c81-96e4-2c32ee36089e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2636363261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2636363261
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.843134079
Short name T898
Test name
Test status
Simulation time 53838608 ps
CPU time 1.54 seconds
Started Jul 15 06:44:00 PM PDT 24
Finished Jul 15 06:44:02 PM PDT 24
Peak memory 198400 kb
Host smart-7e859da7-94dc-45e2-81a8-5412682752a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843134079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.843134079
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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