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Group Instance : masked_out_lower_mask_data_cov_obj_pin3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin3
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_lower_mask_data_cov_obj_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_lower_mask_data_cov_obj_pin5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin5
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_lower_mask_data_cov_obj_pin6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin6
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_lower_mask_data_cov_obj_pin7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin7
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_lower_mask_data_cov_obj_pin8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin8
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_lower_mask_data_cov_obj_pin9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_lower_mask_data_cov_obj_pin9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_lower_mask_data_cov_obj_pin9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_lower_mask_data_cov_obj_pin9
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin0
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin1
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin10
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin10

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin10
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin10
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin11
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin11

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin11
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin11
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin12
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin12

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin12
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin12
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin13
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin13

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin13
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin13
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin14
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin14

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin14
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin14
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin15
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin15

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin15
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin15
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin2
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin3
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0



Group Instance : masked_out_upper_mask_data_cov_obj_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance masked_out_upper_mask_data_cov_obj_pin4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group Instance masked_out_upper_mask_data_cov_obj_pin4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_var1 2 0 2 100.00 100 1 1 2
cp_var2 2 0 2 100.00 100 1 1 2


Crosses for Group Instance masked_out_upper_mask_data_cov_obj_pin4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_var1_var2_cross 4 0 4 100.00 100 1 1 0

Go back
Group Instances:
masked_out_lower_mask_data_cov_obj_pin3
masked_out_lower_mask_data_cov_obj_pin4
masked_out_lower_mask_data_cov_obj_pin5
masked_out_lower_mask_data_cov_obj_pin6
masked_out_lower_mask_data_cov_obj_pin7
masked_out_lower_mask_data_cov_obj_pin8
masked_out_lower_mask_data_cov_obj_pin9
masked_out_upper_mask_data_cov_obj_pin0
masked_out_upper_mask_data_cov_obj_pin1
masked_out_upper_mask_data_cov_obj_pin10
masked_out_upper_mask_data_cov_obj_pin11
masked_out_upper_mask_data_cov_obj_pin12
masked_out_upper_mask_data_cov_obj_pin13
masked_out_upper_mask_data_cov_obj_pin14
masked_out_upper_mask_data_cov_obj_pin15
masked_out_upper_mask_data_cov_obj_pin2
masked_out_upper_mask_data_cov_obj_pin3
masked_out_upper_mask_data_cov_obj_pin4

Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165435 1 T43 2 T32 519 T50 20
auto[1] 165585 1 T43 2 T32 519 T50 25



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165084 1 T43 4 T32 525 T50 25
auto[1] 165936 1 T32 513 T50 20 T113 9



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82575 1 T43 2 T32 255 T50 12
auto[0] auto[1] 82860 1 T32 264 T50 8 T113 4
auto[1] auto[0] 82509 1 T43 2 T32 270 T50 13
auto[1] auto[1] 83076 1 T32 249 T50 12 T113 5


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165505 1 T43 2 T32 521 T50 28
auto[1] 165515 1 T43 2 T32 517 T50 17



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165569 1 T43 2 T32 508 T50 17
auto[1] 165451 1 T43 2 T32 530 T50 28



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82894 1 T43 2 T32 249 T50 10
auto[0] auto[1] 82611 1 T32 272 T50 18 T113 2
auto[1] auto[0] 82675 1 T32 259 T50 7 T113 7
auto[1] auto[1] 82840 1 T43 2 T32 258 T50 10


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165632 1 T43 1 T32 521 T50 19
auto[1] 165388 1 T43 3 T32 517 T50 26



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165298 1 T43 1 T32 545 T50 19
auto[1] 165722 1 T43 3 T32 493 T50 26



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82679 1 T32 282 T50 7 T113 8
auto[0] auto[1] 82953 1 T43 1 T32 239 T50 12
auto[1] auto[0] 82619 1 T43 1 T32 263 T50 12
auto[1] auto[1] 82769 1 T43 2 T32 254 T50 14


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165808 1 T43 3 T32 503 T50 21
auto[1] 165212 1 T43 1 T32 535 T50 24



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165552 1 T43 3 T32 539 T50 17
auto[1] 165468 1 T43 1 T32 499 T50 28



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 83195 1 T43 3 T32 269 T50 9
auto[0] auto[1] 82613 1 T32 234 T50 12 T113 5
auto[1] auto[0] 82357 1 T32 270 T50 8 T113 4
auto[1] auto[1] 82855 1 T43 1 T32 265 T50 16


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165542 1 T43 3 T32 517 T50 23
auto[1] 165478 1 T43 1 T32 521 T50 22



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165640 1 T43 2 T32 534 T50 19
auto[1] 165380 1 T43 2 T32 504 T50 26



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82452 1 T43 2 T32 263 T50 7
auto[0] auto[1] 83090 1 T43 1 T32 254 T50 16
auto[1] auto[0] 83188 1 T32 271 T50 12 T113 6
auto[1] auto[1] 82290 1 T43 1 T32 250 T50 10


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165401 1 T43 2 T32 518 T50 22
auto[1] 165619 1 T43 2 T32 520 T50 23



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165721 1 T43 2 T32 531 T50 27
auto[1] 165299 1 T43 2 T32 507 T50 18



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82845 1 T43 1 T32 273 T50 13
auto[0] auto[1] 82556 1 T43 1 T32 245 T50 9
auto[1] auto[0] 82876 1 T43 1 T32 258 T50 14
auto[1] auto[1] 82743 1 T43 1 T32 262 T50 9


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 166174 1 T43 2 T32 523 T50 21
auto[1] 164846 1 T43 2 T32 515 T50 24



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165767 1 T43 3 T32 511 T50 22
auto[1] 165253 1 T43 1 T32 527 T50 23



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 83348 1 T43 2 T32 264 T50 13
auto[0] auto[1] 82826 1 T32 259 T50 8 T113 3
auto[1] auto[0] 82419 1 T43 1 T32 247 T50 9
auto[1] auto[1] 82427 1 T43 1 T32 268 T50 15


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165571 1 T43 4 T32 526 T50 17
auto[1] 165359 1 T43 6 T32 533 T50 13



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165393 1 T43 4 T32 519 T50 16
auto[1] 165537 1 T43 6 T32 540 T50 14



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82512 1 T43 2 T32 247 T50 8
auto[0] auto[1] 83059 1 T43 2 T32 279 T50 9
auto[1] auto[0] 82881 1 T43 2 T32 272 T50 8
auto[1] auto[1] 82478 1 T43 4 T32 261 T50 5


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165568 1 T43 5 T32 539 T50 20
auto[1] 165362 1 T43 5 T32 520 T50 10



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165684 1 T43 6 T32 520 T50 15
auto[1] 165246 1 T43 4 T32 539 T50 15



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82922 1 T43 2 T32 255 T50 9
auto[0] auto[1] 82646 1 T43 3 T32 284 T50 11
auto[1] auto[0] 82762 1 T43 4 T32 265 T50 6
auto[1] auto[1] 82600 1 T43 1 T32 255 T50 4


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165257 1 T43 2 T32 540 T50 10
auto[1] 165673 1 T43 8 T32 519 T50 20



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165593 1 T43 5 T32 522 T50 17
auto[1] 165337 1 T43 5 T32 537 T50 13



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82611 1 T43 1 T32 263 T50 4
auto[0] auto[1] 82646 1 T43 1 T32 277 T50 6
auto[1] auto[0] 82982 1 T43 4 T32 259 T50 13
auto[1] auto[1] 82691 1 T43 4 T32 260 T50 7


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165356 1 T43 4 T32 544 T50 12
auto[1] 165574 1 T43 6 T32 515 T50 18



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165722 1 T43 5 T32 532 T50 10
auto[1] 165208 1 T43 5 T32 527 T50 20



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82745 1 T43 2 T32 281 T50 1
auto[0] auto[1] 82611 1 T43 2 T32 263 T50 11
auto[1] auto[0] 82977 1 T43 3 T32 251 T50 9
auto[1] auto[1] 82597 1 T43 3 T32 264 T50 9


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165161 1 T43 5 T32 534 T50 13
auto[1] 165769 1 T43 5 T32 525 T50 17



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165400 1 T43 5 T32 515 T50 13
auto[1] 165530 1 T43 5 T32 544 T50 17



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82852 1 T43 1 T32 253 T50 7
auto[0] auto[1] 82309 1 T43 4 T32 281 T50 6
auto[1] auto[0] 82548 1 T43 4 T32 262 T50 6
auto[1] auto[1] 83221 1 T43 1 T32 263 T50 11


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165274 1 T43 4 T32 522 T50 14
auto[1] 165656 1 T43 6 T32 537 T50 16



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165395 1 T43 5 T32 563 T50 12
auto[1] 165535 1 T43 5 T32 496 T50 18



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82472 1 T43 2 T32 289 T50 7
auto[0] auto[1] 82802 1 T43 2 T32 233 T50 7
auto[1] auto[0] 82923 1 T43 3 T32 274 T50 5
auto[1] auto[1] 82733 1 T43 3 T32 263 T50 11


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165934 1 T43 7 T32 522 T50 15
auto[1] 164996 1 T43 3 T32 537 T50 15



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165860 1 T43 5 T32 536 T50 18
auto[1] 165070 1 T43 5 T32 523 T50 12



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 83111 1 T43 2 T32 270 T50 8
auto[0] auto[1] 82823 1 T43 5 T32 252 T50 7
auto[1] auto[0] 82749 1 T43 3 T32 266 T50 10
auto[1] auto[1] 82247 1 T32 271 T50 5 T113 3


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165488 1 T43 5 T32 551 T50 9
auto[1] 165442 1 T43 5 T32 508 T50 21



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165597 1 T43 4 T32 508 T50 14
auto[1] 165333 1 T43 6 T32 551 T50 16



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82706 1 T43 2 T32 271 T50 4
auto[0] auto[1] 82782 1 T43 3 T32 280 T50 5
auto[1] auto[0] 82891 1 T43 2 T32 237 T50 10
auto[1] auto[1] 82551 1 T43 3 T32 271 T50 11


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165404 1 T43 6 T32 537 T50 13
auto[1] 165526 1 T43 4 T32 522 T50 17



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165600 1 T43 6 T32 532 T50 17
auto[1] 165330 1 T43 4 T32 527 T50 13



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82801 1 T43 4 T32 264 T50 10
auto[0] auto[1] 82603 1 T43 2 T32 273 T50 3
auto[1] auto[0] 82799 1 T43 2 T32 268 T50 7
auto[1] auto[1] 82727 1 T43 2 T32 254 T50 10


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165034 1 T43 5 T32 530 T50 13
auto[1] 165896 1 T43 5 T32 529 T50 17



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 164705 1 T43 7 T32 498 T50 19
auto[1] 166225 1 T43 3 T32 561 T50 11



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82224 1 T43 4 T32 249 T50 9
auto[0] auto[1] 82810 1 T43 1 T32 281 T50 4
auto[1] auto[0] 82481 1 T43 3 T32 249 T50 10
auto[1] auto[1] 83415 1 T43 2 T32 280 T50 7


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165494 1 T43 6 T32 529 T50 11
auto[1] 165436 1 T43 4 T32 530 T50 19



Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165220 1 T43 4 T32 496 T50 13
auto[1] 165710 1 T43 6 T32 563 T50 17



Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82754 1 T43 2 T32 243 T50 5
auto[0] auto[1] 82740 1 T43 4 T32 286 T50 6
auto[1] auto[0] 82466 1 T43 2 T32 253 T50 8
auto[1] auto[1] 82970 1 T43 2 T32 277 T50 11

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%