Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3353244	1			T21	295		T22	108		T23	98
all_pins[1]	3353244	1			T21	295		T22	108		T23	98
all_pins[2]	3353244	1			T21	295		T22	108		T23	98
all_pins[3]	3353244	1			T21	295		T22	108		T23	98
all_pins[4]	3353244	1			T21	295		T22	108		T23	98
all_pins[5]	3353244	1			T21	295		T22	108		T23	98
all_pins[6]	3353244	1			T21	295		T22	108		T23	98
all_pins[7]	3353244	1			T21	295		T22	108		T23	98
all_pins[8]	3353244	1			T21	295		T22	108		T23	98
all_pins[9]	3353244	1			T21	295		T22	108		T23	98
all_pins[10]	3353244	1			T21	295		T22	108		T23	98
all_pins[11]	3353244	1			T21	295		T22	108		T23	98
all_pins[12]	3353244	1			T21	295		T22	108		T23	98
all_pins[13]	3353244	1			T21	295		T22	108		T23	98
all_pins[14]	3353244	1			T21	295		T22	108		T23	98
all_pins[15]	3353244	1			T21	295		T22	108		T23	98
all_pins[16]	3353244	1			T21	295		T22	108		T23	98
all_pins[17]	3353244	1			T21	295		T22	108		T23	98
all_pins[18]	3353244	1			T21	295		T22	108		T23	98
all_pins[19]	3353244	1			T21	295		T22	108		T23	98
all_pins[20]	3353244	1			T21	295		T22	108		T23	98
all_pins[21]	3353244	1			T21	295		T22	108		T23	98
all_pins[22]	3353244	1			T21	295		T22	108		T23	98
all_pins[23]	3353244	1			T21	295		T22	108		T23	98
all_pins[24]	3353244	1			T21	295		T22	108		T23	98
all_pins[25]	3353244	1			T21	295		T22	108		T23	98
all_pins[26]	3353244	1			T21	295		T22	108		T23	98
all_pins[27]	3353244	1			T21	295		T22	108		T23	98
all_pins[28]	3353244	1			T21	295		T22	108		T23	98
all_pins[29]	3353244	1			T21	295		T22	108		T23	98
all_pins[30]	3353244	1			T21	295		T22	108		T23	98
all_pins[31]	3353244	1			T21	295		T22	108		T23	98

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	66649537	1			T21	5982		T22	1831		T23	1622
values[0x1]	40654271	1			T21	3458		T22	1625		T23	1514
transitions[0x0=>0x1]	24350920	1			T21	2282		T22	829		T23	785
transitions[0x1=>0x0]	24350763	1			T21	2282		T22	828		T23	784

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2083738	1			T21	186		T22	62		T23	46
all_pins[0]	values[0x1]	1269506	1			T21	109		T22	46		T23	52
all_pins[0]	transitions[0x0=>0x1]	784383	1			T21	53		T22	26		T23	29
all_pins[0]	transitions[0x1=>0x0]	787357	1			T21	97		T22	29		T23	18
all_pins[1]	values[0x0]	2086875	1			T21	202		T22	57		T23	51
all_pins[1]	values[0x1]	1266369	1			T21	93		T22	51		T23	47
all_pins[1]	transitions[0x0=>0x1]	758554	1			T21	54		T22	23		T23	23
all_pins[1]	transitions[0x1=>0x0]	761691	1			T21	70		T22	18		T23	28
all_pins[2]	values[0x0]	2084489	1			T21	181		T22	54		T23	58
all_pins[2]	values[0x1]	1268755	1			T21	114		T22	54		T23	40
all_pins[2]	transitions[0x0=>0x1]	760159	1			T21	83		T22	28		T23	21
all_pins[2]	transitions[0x1=>0x0]	757773	1			T21	62		T22	25		T23	28
all_pins[3]	values[0x0]	2083326	1			T21	137		T22	62		T23	55
all_pins[3]	values[0x1]	1269918	1			T21	158		T22	46		T23	43
all_pins[3]	transitions[0x0=>0x1]	759116	1			T21	125		T22	23		T23	27
all_pins[3]	transitions[0x1=>0x0]	757953	1			T21	81		T22	31		T23	24
all_pins[4]	values[0x0]	2088471	1			T21	191		T22	53		T23	54
all_pins[4]	values[0x1]	1264773	1			T21	104		T22	55		T23	44
all_pins[4]	transitions[0x0=>0x1]	758041	1			T21	47		T22	28		T23	29
all_pins[4]	transitions[0x1=>0x0]	763186	1			T21	101		T22	19		T23	28
all_pins[5]	values[0x0]	2081325	1			T21	154		T22	64		T23	49
all_pins[5]	values[0x1]	1271919	1			T21	141		T22	44		T23	49
all_pins[5]	transitions[0x0=>0x1]	765408	1			T21	93		T22	19		T23	28
all_pins[5]	transitions[0x1=>0x0]	758262	1			T21	56		T22	30		T23	23
all_pins[6]	values[0x0]	2080432	1			T21	173		T22	65		T23	46
all_pins[6]	values[0x1]	1272812	1			T21	122		T22	43		T23	52
all_pins[6]	transitions[0x0=>0x1]	761674	1			T21	79		T22	22		T23	26
all_pins[6]	transitions[0x1=>0x0]	760781	1			T21	98		T22	23		T23	23
all_pins[7]	values[0x0]	2083391	1			T21	213		T22	64		T23	55
all_pins[7]	values[0x1]	1269853	1			T21	82		T22	44		T23	43
all_pins[7]	transitions[0x0=>0x1]	758369	1			T21	47		T22	26		T23	21
all_pins[7]	transitions[0x1=>0x0]	761328	1			T21	87		T22	25		T23	30
all_pins[8]	values[0x0]	2081725	1			T21	210		T22	57		T23	43
all_pins[8]	values[0x1]	1271519	1			T21	85		T22	51		T23	55
all_pins[8]	transitions[0x0=>0x1]	762552	1			T21	58		T22	34		T23	29
all_pins[8]	transitions[0x1=>0x0]	760886	1			T21	55		T22	27		T23	17
all_pins[9]	values[0x0]	2084507	1			T21	182		T22	64		T23	48
all_pins[9]	values[0x1]	1268737	1			T21	113		T22	44		T23	50
all_pins[9]	transitions[0x0=>0x1]	759125	1			T21	78		T22	28		T23	19
all_pins[9]	transitions[0x1=>0x0]	761907	1			T21	50		T22	35		T23	24
all_pins[10]	values[0x0]	2083070	1			T21	206		T22	52		T23	50
all_pins[10]	values[0x1]	1270174	1			T21	89		T22	56		T23	48
all_pins[10]	transitions[0x0=>0x1]	760182	1			T21	65		T22	29		T23	25
all_pins[10]	transitions[0x1=>0x0]	758745	1			T21	89		T22	17		T23	27
all_pins[11]	values[0x0]	2079365	1			T21	153		T22	55		T23	45
all_pins[11]	values[0x1]	1273879	1			T21	142		T22	53		T23	53
all_pins[11]	transitions[0x0=>0x1]	763067	1			T21	112		T22	23		T23	25
all_pins[11]	transitions[0x1=>0x0]	759362	1			T21	59		T22	26		T23	20
all_pins[12]	values[0x0]	2082803	1			T21	241		T22	59		T23	56
all_pins[12]	values[0x1]	1270441	1			T21	54		T22	49		T23	42
all_pins[12]	transitions[0x0=>0x1]	759414	1			T21	33		T22	24		T23	22
all_pins[12]	transitions[0x1=>0x0]	762852	1			T21	121		T22	28		T23	33
all_pins[13]	values[0x0]	2074745	1			T21	172		T22	63		T23	54
all_pins[13]	values[0x1]	1278499	1			T21	123		T22	45		T23	44
all_pins[13]	transitions[0x0=>0x1]	763961	1			T21	96		T22	22		T23	26
all_pins[13]	transitions[0x1=>0x0]	755903	1			T21	27		T22	26		T23	24
all_pins[14]	values[0x0]	2083553	1			T21	187		T22	55		T23	56
all_pins[14]	values[0x1]	1269691	1			T21	108		T22	53		T23	42
all_pins[14]	transitions[0x0=>0x1]	758389	1			T21	83		T22	28		T23	20
all_pins[14]	transitions[0x1=>0x0]	767197	1			T21	98		T22	20		T23	22
all_pins[15]	values[0x0]	2083119	1			T21	181		T22	52		T23	55
all_pins[15]	values[0x1]	1270125	1			T21	114		T22	56		T23	43
all_pins[15]	transitions[0x0=>0x1]	760198	1			T21	34		T22	27		T23	22
all_pins[15]	transitions[0x1=>0x0]	759764	1			T21	28		T22	24		T23	21
all_pins[16]	values[0x0]	2082056	1			T21	204		T22	58		T23	48
all_pins[16]	values[0x1]	1271188	1			T21	91		T22	50		T23	50
all_pins[16]	transitions[0x0=>0x1]	758856	1			T21	71		T22	23		T23	22
all_pins[16]	transitions[0x1=>0x0]	757793	1			T21	94		T22	29		T23	15
all_pins[17]	values[0x0]	2083662	1			T21	222		T22	47		T23	48
all_pins[17]	values[0x1]	1269582	1			T21	73		T22	61		T23	50
all_pins[17]	transitions[0x0=>0x1]	756882	1			T21	41		T22	30		T23	26
all_pins[17]	transitions[0x1=>0x0]	758488	1			T21	59		T22	19		T23	26
all_pins[18]	values[0x0]	2085721	1			T21	169		T22	39		T23	49
all_pins[18]	values[0x1]	1267523	1			T21	126		T22	69		T23	49
all_pins[18]	transitions[0x0=>0x1]	759652	1			T21	107		T22	31		T23	26
all_pins[18]	transitions[0x1=>0x0]	761711	1			T21	54		T22	23		T23	27
all_pins[19]	values[0x0]	2084433	1			T21	232		T22	53		T23	53
all_pins[19]	values[0x1]	1268811	1			T21	63		T22	55		T23	45
all_pins[19]	transitions[0x0=>0x1]	760250	1			T21	51		T22	20		T23	25
all_pins[19]	transitions[0x1=>0x0]	758962	1			T21	114		T22	34		T23	29
all_pins[20]	values[0x0]	2079335	1			T21	178		T22	63		T23	48
all_pins[20]	values[0x1]	1273909	1			T21	117		T22	45		T23	50
all_pins[20]	transitions[0x0=>0x1]	761857	1			T21	81		T22	23		T23	30
all_pins[20]	transitions[0x1=>0x0]	756759	1			T21	27		T22	33		T23	25
all_pins[21]	values[0x0]	2076945	1			T21	185		T22	59		T23	50
all_pins[21]	values[0x1]	1276299	1			T21	110		T22	49		T23	48
all_pins[21]	transitions[0x0=>0x1]	761255	1			T21	71		T22	27		T23	30
all_pins[21]	transitions[0x1=>0x0]	758865	1			T21	78		T22	23		T23	32
all_pins[22]	values[0x0]	2083252	1			T21	141		T22	48		T23	47
all_pins[22]	values[0x1]	1269992	1			T21	154		T22	60		T23	51
all_pins[22]	transitions[0x0=>0x1]	759429	1			T21	98		T22	34		T23	26
all_pins[22]	transitions[0x1=>0x0]	765736	1			T21	54		T22	23		T23	23
all_pins[23]	values[0x0]	2080601	1			T21	184		T22	62		T23	58
all_pins[23]	values[0x1]	1272643	1			T21	111		T22	46		T23	40
all_pins[23]	transitions[0x0=>0x1]	760731	1			T21	40		T22	20		T23	18
all_pins[23]	transitions[0x1=>0x0]	758080	1			T21	83		T22	34		T23	29
all_pins[24]	values[0x0]	2084791	1			T21	201		T22	54		T23	51
all_pins[24]	values[0x1]	1268453	1			T21	94		T22	54		T23	47
all_pins[24]	transitions[0x0=>0x1]	756749	1			T21	88		T22	32		T23	33
all_pins[24]	transitions[0x1=>0x0]	760939	1			T21	105		T22	24		T23	26
all_pins[25]	values[0x0]	2078044	1			T21	212		T22	59		T23	52
all_pins[25]	values[0x1]	1275200	1			T21	83		T22	49		T23	46
all_pins[25]	transitions[0x0=>0x1]	764822	1			T21	66		T22	30		T23	21
all_pins[25]	transitions[0x1=>0x0]	758075	1			T21	77		T22	35		T23	22
all_pins[26]	values[0x0]	2089224	1			T21	197		T22	55		T23	49
all_pins[26]	values[0x1]	1264020	1			T21	98		T22	53		T23	49
all_pins[26]	transitions[0x0=>0x1]	754864	1			T21	91		T22	24		T23	26
all_pins[26]	transitions[0x1=>0x0]	766044	1			T21	76		T22	20		T23	23
all_pins[27]	values[0x0]	2085196	1			T21	192		T22	54		T23	45
all_pins[27]	values[0x1]	1268048	1			T21	103		T22	54		T23	53
all_pins[27]	transitions[0x0=>0x1]	761117	1			T21	41		T22	27		T23	22
all_pins[27]	transitions[0x1=>0x0]	757089	1			T21	36		T22	26		T23	18
all_pins[28]	values[0x0]	2083997	1			T21	165		T22	64		T23	54
all_pins[28]	values[0x1]	1269247	1			T21	130		T22	44		T23	44
all_pins[28]	transitions[0x0=>0x1]	760546	1			T21	87		T22	26		T23	20
all_pins[28]	transitions[0x1=>0x0]	759347	1			T21	60		T22	36		T23	29
all_pins[29]	values[0x0]	2088001	1			T21	184		T22	60		T23	52
all_pins[29]	values[0x1]	1265243	1			T21	111		T22	48		T23	46
all_pins[29]	transitions[0x0=>0x1]	757714	1			T21	41		T22	25		T23	23
all_pins[29]	transitions[0x1=>0x0]	761718	1			T21	60		T22	21		T23	21
all_pins[30]	values[0x0]	2078738	1			T21	205		T22	60		T23	41
all_pins[30]	values[0x1]	1274506	1			T21	90		T22	48		T23	57
all_pins[30]	transitions[0x0=>0x1]	762394	1			T21	52		T22	25		T23	28
all_pins[30]	transitions[0x1=>0x0]	753131	1			T21	73		T22	25		T23	17
all_pins[31]	values[0x0]	2080607	1			T21	142		T22	58		T23	56
all_pins[31]	values[0x1]	1272637	1			T21	153		T22	50		T23	42
all_pins[31]	transitions[0x0=>0x1]	761210	1			T21	116		T22	22		T23	17
all_pins[31]	transitions[0x1=>0x0]	763079	1			T21	53		T22	20		T23	32