Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[1]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[2]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[3]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[4]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[5]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[6]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[7]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[8]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[9]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[10]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[11]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[12]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[13]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[14]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[15]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[16]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[17]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[18]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[19]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[20]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[21]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[22]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[23]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[24]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[25]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[26]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[27]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[28]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[29]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[30]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[31]	11529999	1			T21	507		T22	54560		T23	1683

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

219153264

1

T21

8147

T22

881223

T23

27045

auto[1]

149806704

1

T21

8077

T22

864697

T23

26811

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298560084

1

T21

16224

T22

174592

T23

53856

auto[1]

70399884

1

T25

4435

T26

1419

T28

6824

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

277879024

1

T21

16224

T22

174592

T23

53856

auto[1]

91080944

1

T25

4338

T26

1601

T28

7017

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4336348	1			T21	235		T22	27988		T23	859
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3237596	1			T21	272		T22	26572		T23	824
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1108689	1			T25	64		T26	22		T28	140
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1405737	1			T25	66		T26	16		T30	193
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	344173	1			T28	73		T43	74		T32	343
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1097456	1			T25	69		T26	23		T28	97
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4343863	1			T21	276		T22	27826		T23	865
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3234689	1			T21	231		T22	26734		T23	818
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1104998	1			T25	70		T26	14		T28	95
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1404416	1			T25	76		T26	22		T30	212
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	342995	1			T28	122		T43	50		T32	384
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1099038	1			T25	91		T26	34		T28	130
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4324409	1			T21	263		T22	27371		T23	865
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3253983	1			T21	244		T22	27189		T23	818
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1106654	1			T25	68		T26	32		T28	113
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1402828	1			T25	67		T26	18		T30	188
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	341593	1			T28	92		T43	46		T32	345
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1100532	1			T25	64		T26	13		T28	123
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4331877	1			T21	247		T22	25089		T23	930
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3246119	1			T21	260		T22	29471		T23	753
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1108260	1			T25	50		T26	20		T28	112
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1402828	1			T25	60		T26	22		T30	204
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	342721	1			T28	118		T43	18		T32	300
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1098194	1			T25	99		T26	29		T28	108
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4332168	1			T21	266		T22	25537		T23	849
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3242252	1			T21	241		T22	29023		T23	834
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1108472	1			T25	42		T26	20		T28	102
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1403936	1			T25	69		T26	23		T30	204
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	345509	1			T28	120		T43	69		T32	315
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1097662	1			T25	66		T26	24		T28	110
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4341429	1			T21	241		T22	25957		T23	868
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3236269	1			T21	266		T22	28603		T23	815
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1105351	1			T25	38		T26	14		T28	112
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1404059	1			T25	104		T26	22		T30	205
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	344047	1			T28	103		T43	48		T32	356
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1098844	1			T25	83		T26	22		T28	100
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4344595	1			T21	250		T22	27330		T23	712
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3237769	1			T21	257		T22	27230		T23	971
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1104518	1			T25	54		T26	27		T28	117
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1403611	1			T25	70		T26	14		T30	168
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	342329	1			T28	91		T43	130		T32	351
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1097177	1			T25	62		T26	22		T28	128
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4325510	1			T21	257		T22	27588		T23	856
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3250915	1			T21	250		T22	26972		T23	827
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1108213	1			T25	55		T26	23		T28	120
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1408318	1			T25	74		T26	22		T30	158
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	341353	1			T28	99		T43	101		T32	350
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1095690	1			T25	74		T26	34		T28	100
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4328522	1			T21	259		T22	28609		T23	866
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3242956	1			T21	248		T22	25951		T23	817
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1110009	1			T25	106		T26	17		T28	84
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1402347	1			T25	34		T26	24		T30	190
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	344665	1			T28	99		T43	22		T32	297
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1101500	1			T25	58		T26	24		T28	107
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4340539	1			T21	251		T22	29260		T23	769
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3237188	1			T21	256		T22	25300		T23	914
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1104729	1			T25	85		T26	29		T28	119
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1405848	1			T25	68		T26	24		T30	208
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	342547	1			T28	103		T43	88		T32	385
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1099148	1			T25	40		T26	16		T28	120
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4334810	1			T21	243		T22	27438		T23	831
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3241462	1			T21	264		T22	27122		T23	852
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1103582	1			T25	79		T26	20		T28	85
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1404102	1			T25	66		T26	34		T30	196
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	345339	1			T28	152		T43	65		T32	383
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1100704	1			T25	58		T26	21		T28	95
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4336835	1			T21	249		T22	27248		T23	791
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3241157	1			T21	258		T22	27312		T23	892
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1106275	1			T25	60		T26	25		T28	94
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1402321	1			T25	62		T26	24		T30	196
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	344345	1			T28	112		T43	3		T32	387
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1099066	1			T25	97		T26	24		T28	118
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4335022	1			T21	268		T22	26841		T23	870
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3243523	1			T21	239		T22	27719		T23	813
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1110421	1			T25	74		T26	16		T28	103
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1403068	1			T25	65		T26	42		T30	158
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	341525	1			T28	117		T43	42		T32	357
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1096440	1			T25	66		T26	13		T28	94
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4328146	1			T21	251		T22	26020		T23	860
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3244386	1			T21	256		T22	28540		T23	823
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1110453	1			T25	78		T26	24		T28	89
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1407834	1			T25	60		T26	31		T30	156
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	345770	1			T28	136		T43	95		T32	360
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1093410	1			T25	87		T26	24		T28	99
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4343111	1			T21	252		T22	27964		T23	800
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3239096	1			T21	255		T22	26596		T23	883
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1108559	1			T25	73		T26	16		T28	70
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1401840	1			T25	64		T26	23		T30	182
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	342489	1			T28	120		T43	53		T32	291
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1094904	1			T25	52		T26	44		T28	146
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4331433	1			T21	254		T22	29684		T23	827
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3245239	1			T21	253		T22	24876		T23	856
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1109680	1			T25	76		T26	14		T28	82
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1401297	1			T25	54		T26	29		T30	190
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	343524	1			T28	117		T43	40		T32	334
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1098826	1			T25	73		T26	26		T28	117
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4328784	1			T21	256		T22	25475		T23	910
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3248173	1			T21	251		T22	29085		T23	773
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1103392	1			T25	63		T26	16		T28	112
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1410288	1			T25	78		T26	30		T30	185
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	345547	1			T28	104		T43	72		T32	353
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1093815	1			T25	58		T26	29		T28	83
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4351390	1			T21	276		T22	28674		T23	834
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3230352	1			T21	231		T22	25886		T23	849
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1103315	1			T25	64		T26	18		T28	109
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1410002	1			T25	70		T26	41		T30	194
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	342849	1			T28	97		T43	57		T32	304
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1092091	1			T25	73		T26	14		T28	122
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4333814	1			T21	256		T22	25864		T23	819
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3244777	1			T21	251		T22	28696		T23	864
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1103372	1			T25	54		T26	14		T28	132
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1408397	1			T25	64		T26	40		T30	172
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	345064	1			T28	90		T43	82		T32	387
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1094575	1			T25	95		T26	27		T28	121
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4329918	1			T21	257		T22	27811		T23	799
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3251350	1			T21	250		T22	26749		T23	884
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1096143	1			T25	52		T26	27		T28	110
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1411334	1			T25	64		T26	18		T30	178
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	346785	1			T28	108		T43	68		T32	371
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1094469	1			T25	84		T26	14		T28	106
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4327650	1			T21	255		T22	28020		T23	857
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3246574	1			T21	252		T22	26540		T23	826
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1102099	1			T25	63		T26	22		T28	110
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1414983	1			T25	54		T26	16		T30	216
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	343927	1			T28	106		T43	58		T32	382
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1094766	1			T25	94		T26	35		T28	109
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4347306	1			T21	274		T22	28056		T23	854
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3234036	1			T21	233		T22	26504		T23	829
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1097982	1			T25	74		T26	22		T28	96
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1409753	1			T25	70		T26	20		T30	179
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	345284	1			T28	122		T43	28		T32	345
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1095638	1			T25	50		T26	39		T28	104
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4336469	1			T21	266		T22	27936		T23	839
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3243772	1			T21	241		T22	26624		T23	844
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1103807	1			T25	103		T26	18		T28	84
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1412212	1			T25	46		T26	21		T30	182
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	342927	1			T28	142		T43	60		T32	357
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1090812	1			T25	46		T26	18		T28	104
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4336704	1			T21	230		T22	28402		T23	925
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3250646	1			T21	277		T22	26158		T23	758
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1099899	1			T25	65		T26	24		T28	112
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1410483	1			T25	48		T26	24		T30	173
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	344350	1			T28	106		T43	84		T32	416
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1087917	1			T25	60		T26	20		T28	124
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4343600	1			T21	244		T22	27896		T23	830
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3232577	1			T21	263		T22	26664		T23	853
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1101900	1			T25	82		T26	14		T28	115
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1412289	1			T25	49		T26	34		T30	186
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	344870	1			T28	110		T43	91		T32	378
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1094763	1			T25	74		T26	14		T28	113
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4339899	1			T21	242		T22	28440		T23	854
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3241657	1			T21	265		T22	26120		T23	829
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1095345	1			T25	62		T26	2		T28	112
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1417894	1			T25	76		T26	41		T30	166
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	343228	1			T28	78		T43	35		T32	354
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1091976	1			T25	71		T26	26		T28	120
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4345179	1			T21	244		T22	28329		T23	821
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3246093	1			T21	263		T22	26231		T23	862
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1105308	1			T25	70		T26	24		T28	101
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1400888	1			T25	58		T26	24		T30	179
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	342575	1			T28	120		T43	66		T32	304
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1089956	1			T25	78		T26	28		T28	88
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4341065	1			T21	246		T22	28096		T23	894
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3242422	1			T21	261		T22	26464		T23	789
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1103237	1			T25	60		T26	19		T28	112
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1405260	1			T25	75		T26	42		T30	162
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	345681	1			T28	90		T43	103		T32	385
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1092334	1			T25	68		T26	18		T28	105
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4329147	1			T21	250		T22	27951		T23	762
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3243284	1			T21	257		T22	26609		T23	921
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1099676	1			T25	76		T26	22		T28	109
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1413765	1			T25	59		T26	20		T30	200
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	344121	1			T28	121		T43	46		T32	412
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1100006	1			T25	64		T26	27		T28	86
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4333972	1			T21	270		T22	26073		T23	880
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3247398	1			T21	237		T22	28487		T23	803
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1102631	1			T25	82		T26	27		T28	78
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1410944	1			T25	53		T26	18		T30	123
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	345409	1			T28	148		T43	25		T32	322
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1089645	1			T25	82		T26	18		T28	86
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4345561	1			T21	270		T22	29312		T23	942
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3236393	1			T21	237		T22	25248		T23	741
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1105376	1			T25	57		T26	34		T28	119
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1410357	1			T25	80		T26	21		T30	200
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	339986	1			T28	104		T43	20		T32	370
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1092326	1			T25	72		T26	22		T28	112
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4348566	1			T21	249		T22	27138		T23	807
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3239820	1			T21	258		T22	27422		T23	876
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1105115	1			T25	70		T26	18		T28	92
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1404924	1			T25	69		T26	36		T30	161
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	342830	1			T28	113		T43	77		T32	400
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1088744	1			T25	58		T26	23		T28	109

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal