Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[1]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[2]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[3]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[4]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[5]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[6]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[7]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[8]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[9]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[10]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[11]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[12]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[13]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[14]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[15]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[16]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[17]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[18]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[19]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[20]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[21]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[22]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[23]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[24]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[25]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[26]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[27]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[28]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[29]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[30]	11529999	1			T21	507		T22	54560		T23	1683
bins_for_gpio_bits[31]	11529999	1			T21	507		T22	54560		T23	1683

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

219153264

1

T21

8147

T22

881223

T23

27045

auto[1]

149806704

1

T21

8077

T22

864697

T23

26811

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

219144318

1

T21

8147

T22

881223

T23

27045

auto[1]

149815650

1

T21

8077

T22

864697

T23

26811

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6653266	1			T21	235		T22	27988		T23	859
bins_for_gpio_bits[0]	auto[0]	auto[1]	197221	1			T25	21		T26	4		T28	32
bins_for_gpio_bits[0]	auto[1]	auto[0]	197508	1			T25	22		T26	5		T28	32
bins_for_gpio_bits[0]	auto[1]	auto[1]	4482004	1			T21	272		T22	26572		T23	824
bins_for_gpio_bits[1]	auto[0]	auto[0]	6656171	1			T21	276		T22	27826		T23	865
bins_for_gpio_bits[1]	auto[0]	auto[1]	196860	1			T25	20		T26	8		T28	23
bins_for_gpio_bits[1]	auto[1]	auto[0]	197106	1			T25	21		T26	8		T28	22
bins_for_gpio_bits[1]	auto[1]	auto[1]	4479862	1			T21	231		T22	26734		T23	818
bins_for_gpio_bits[2]	auto[0]	auto[0]	6636227	1			T21	263		T22	27371		T23	865
bins_for_gpio_bits[2]	auto[0]	auto[1]	197413	1			T25	15		T26	4		T28	26
bins_for_gpio_bits[2]	auto[1]	auto[0]	197664	1			T25	15		T26	5		T28	26
bins_for_gpio_bits[2]	auto[1]	auto[1]	4498695	1			T21	244		T22	27189		T23	818
bins_for_gpio_bits[3]	auto[0]	auto[0]	6646175	1			T21	247		T22	25089		T23	930
bins_for_gpio_bits[3]	auto[0]	auto[1]	196551	1			T25	20		T26	4		T28	28
bins_for_gpio_bits[3]	auto[1]	auto[0]	196790	1			T25	21		T26	5		T28	28
bins_for_gpio_bits[3]	auto[1]	auto[1]	4490483	1			T21	260		T22	29471		T23	753
bins_for_gpio_bits[4]	auto[0]	auto[0]	6647441	1			T21	266		T22	25537		T23	849
bins_for_gpio_bits[4]	auto[0]	auto[1]	196858	1			T25	15		T26	7		T28	22
bins_for_gpio_bits[4]	auto[1]	auto[0]	197135	1			T25	15		T26	7		T28	22
bins_for_gpio_bits[4]	auto[1]	auto[1]	4488565	1			T21	241		T22	29023		T23	834
bins_for_gpio_bits[5]	auto[0]	auto[0]	6653743	1			T21	241		T22	25957		T23	868
bins_for_gpio_bits[5]	auto[0]	auto[1]	196837	1			T25	18		T26	3		T28	30
bins_for_gpio_bits[5]	auto[1]	auto[0]	197096	1			T25	19		T26	3		T28	30
bins_for_gpio_bits[5]	auto[1]	auto[1]	4482323	1			T21	266		T22	28603		T23	815
bins_for_gpio_bits[6]	auto[0]	auto[0]	6655731	1			T21	250		T22	27330		T23	712
bins_for_gpio_bits[6]	auto[0]	auto[1]	196721	1			T25	16		T26	3		T28	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	196993	1			T25	16		T26	3		T28	26
bins_for_gpio_bits[6]	auto[1]	auto[1]	4480554	1			T21	257		T22	27230		T23	971
bins_for_gpio_bits[7]	auto[0]	auto[0]	6645086	1			T21	257		T22	27588		T23	856
bins_for_gpio_bits[7]	auto[0]	auto[1]	196691	1			T25	19		T26	7		T28	27
bins_for_gpio_bits[7]	auto[1]	auto[0]	196955	1			T25	19		T26	7		T28	27
bins_for_gpio_bits[7]	auto[1]	auto[1]	4491267	1			T21	250		T22	26972		T23	827
bins_for_gpio_bits[8]	auto[0]	auto[0]	6643457	1			T21	259		T22	28609		T23	866
bins_for_gpio_bits[8]	auto[0]	auto[1]	197122	1			T25	16		T26	6		T28	27
bins_for_gpio_bits[8]	auto[1]	auto[0]	197421	1			T25	16		T26	6		T28	27
bins_for_gpio_bits[8]	auto[1]	auto[1]	4491999	1			T21	248		T22	25951		T23	817
bins_for_gpio_bits[9]	auto[0]	auto[0]	6654052	1			T21	251		T22	29260		T23	769
bins_for_gpio_bits[9]	auto[0]	auto[1]	196770	1			T25	13		T26	7		T28	31
bins_for_gpio_bits[9]	auto[1]	auto[0]	197064	1			T25	13		T26	7		T28	31
bins_for_gpio_bits[9]	auto[1]	auto[1]	4482113	1			T21	256		T22	25300		T23	914
bins_for_gpio_bits[10]	auto[0]	auto[0]	6644976	1			T21	243		T22	27438		T23	831
bins_for_gpio_bits[10]	auto[0]	auto[1]	197243	1			T25	19		T26	5		T28	23
bins_for_gpio_bits[10]	auto[1]	auto[0]	197518	1			T25	19		T26	6		T28	23
bins_for_gpio_bits[10]	auto[1]	auto[1]	4490262	1			T21	264		T22	27122		T23	852
bins_for_gpio_bits[11]	auto[0]	auto[0]	6647953	1			T21	249		T22	27248		T23	791
bins_for_gpio_bits[11]	auto[0]	auto[1]	197213	1			T25	16		T26	6		T28	30
bins_for_gpio_bits[11]	auto[1]	auto[0]	197478	1			T25	17		T26	6		T28	30
bins_for_gpio_bits[11]	auto[1]	auto[1]	4487355	1			T21	258		T22	27312		T23	892
bins_for_gpio_bits[12]	auto[0]	auto[0]	6651828	1			T21	268		T22	26841		T23	870
bins_for_gpio_bits[12]	auto[0]	auto[1]	196381	1			T25	20		T26	3		T28	25
bins_for_gpio_bits[12]	auto[1]	auto[0]	196683	1			T25	20		T26	4		T28	24
bins_for_gpio_bits[12]	auto[1]	auto[1]	4485107	1			T21	239		T22	27719		T23	813
bins_for_gpio_bits[13]	auto[0]	auto[0]	6649346	1			T21	251		T22	26020		T23	860
bins_for_gpio_bits[13]	auto[0]	auto[1]	196781	1			T25	17		T26	7		T28	23
bins_for_gpio_bits[13]	auto[1]	auto[0]	197087	1			T25	18		T26	7		T28	23
bins_for_gpio_bits[13]	auto[1]	auto[1]	4486785	1			T21	256		T22	28540		T23	823
bins_for_gpio_bits[14]	auto[0]	auto[0]	6656033	1			T21	252		T22	27964		T23	800
bins_for_gpio_bits[14]	auto[0]	auto[1]	197199	1			T25	14		T26	9		T28	20
bins_for_gpio_bits[14]	auto[1]	auto[0]	197477	1			T25	14		T26	9		T28	20
bins_for_gpio_bits[14]	auto[1]	auto[1]	4479290	1			T21	255		T22	26596		T23	883
bins_for_gpio_bits[15]	auto[0]	auto[0]	6644710	1			T21	254		T22	29684		T23	827
bins_for_gpio_bits[15]	auto[0]	auto[1]	197419	1			T25	17		T26	8		T28	25
bins_for_gpio_bits[15]	auto[1]	auto[0]	197700	1			T25	18		T26	8		T28	25
bins_for_gpio_bits[15]	auto[1]	auto[1]	4490170	1			T21	253		T22	24876		T23	856
bins_for_gpio_bits[16]	auto[0]	auto[0]	6645448	1			T21	256		T22	25475		T23	910
bins_for_gpio_bits[16]	auto[0]	auto[1]	196740	1			T25	17		T26	5		T28	27
bins_for_gpio_bits[16]	auto[1]	auto[0]	197016	1			T25	17		T26	6		T28	27
bins_for_gpio_bits[16]	auto[1]	auto[1]	4490795	1			T21	251		T22	29085		T23	773
bins_for_gpio_bits[17]	auto[0]	auto[0]	6667736	1			T21	276		T22	28674		T23	834
bins_for_gpio_bits[17]	auto[0]	auto[1]	196724	1			T25	21		T26	4		T28	28
bins_for_gpio_bits[17]	auto[1]	auto[0]	196971	1			T25	22		T26	4		T28	28
bins_for_gpio_bits[17]	auto[1]	auto[1]	4468568	1			T21	231		T22	25886		T23	849
bins_for_gpio_bits[18]	auto[0]	auto[0]	6648669	1			T21	256		T22	25864		T23	819
bins_for_gpio_bits[18]	auto[0]	auto[1]	196628	1			T25	18		T26	8		T28	28
bins_for_gpio_bits[18]	auto[1]	auto[0]	196914	1			T25	19		T26	9		T28	28
bins_for_gpio_bits[18]	auto[1]	auto[1]	4487788	1			T21	251		T22	28696		T23	864
bins_for_gpio_bits[19]	auto[0]	auto[0]	6640067	1			T21	257		T22	27811		T23	799
bins_for_gpio_bits[19]	auto[0]	auto[1]	197041	1			T25	17		T26	3		T28	27
bins_for_gpio_bits[19]	auto[1]	auto[0]	197328	1			T25	17		T26	3		T28	27
bins_for_gpio_bits[19]	auto[1]	auto[1]	4495563	1			T21	250		T22	26749		T23	884
bins_for_gpio_bits[20]	auto[0]	auto[0]	6647631	1			T21	255		T22	28020		T23	857
bins_for_gpio_bits[20]	auto[0]	auto[1]	196820	1			T25	19		T26	8		T28	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	197101	1			T25	19		T26	9		T28	28
bins_for_gpio_bits[20]	auto[1]	auto[1]	4488447	1			T21	252		T22	26540		T23	826
bins_for_gpio_bits[21]	auto[0]	auto[0]	6657637	1			T21	274		T22	28056		T23	854
bins_for_gpio_bits[21]	auto[0]	auto[1]	197107	1			T25	17		T26	8		T28	28
bins_for_gpio_bits[21]	auto[1]	auto[0]	197404	1			T25	17		T26	9		T28	28
bins_for_gpio_bits[21]	auto[1]	auto[1]	4477851	1			T21	233		T22	26504		T23	829
bins_for_gpio_bits[22]	auto[0]	auto[0]	6655786	1			T21	266		T22	27936		T23	839
bins_for_gpio_bits[22]	auto[0]	auto[1]	196408	1			T25	14		T26	6		T28	22
bins_for_gpio_bits[22]	auto[1]	auto[0]	196702	1			T25	14		T26	6		T28	22
bins_for_gpio_bits[22]	auto[1]	auto[1]	4481103	1			T21	241		T22	26624		T23	844
bins_for_gpio_bits[23]	auto[0]	auto[0]	6650288	1			T21	230		T22	28402		T23	925
bins_for_gpio_bits[23]	auto[0]	auto[1]	196534	1			T25	16		T26	6		T28	25
bins_for_gpio_bits[23]	auto[1]	auto[0]	196798	1			T25	16		T26	6		T28	25
bins_for_gpio_bits[23]	auto[1]	auto[1]	4486379	1			T21	277		T22	26158		T23	758
bins_for_gpio_bits[24]	auto[0]	auto[0]	6660676	1			T21	244		T22	27896		T23	830
bins_for_gpio_bits[24]	auto[0]	auto[1]	196845	1			T25	19		T26	5		T28	23
bins_for_gpio_bits[24]	auto[1]	auto[0]	197113	1			T25	19		T26	5		T28	23
bins_for_gpio_bits[24]	auto[1]	auto[1]	4475365	1			T21	263		T22	26664		T23	853
bins_for_gpio_bits[25]	auto[0]	auto[0]	6655873	1			T21	242		T22	28440		T23	854
bins_for_gpio_bits[25]	auto[0]	auto[1]	196979	1			T25	18		T26	3		T28	27
bins_for_gpio_bits[25]	auto[1]	auto[0]	197265	1			T25	19		T26	3		T28	27
bins_for_gpio_bits[25]	auto[1]	auto[1]	4479882	1			T21	265		T22	26120		T23	829
bins_for_gpio_bits[26]	auto[0]	auto[0]	6655082	1			T21	244		T22	28329		T23	821
bins_for_gpio_bits[26]	auto[0]	auto[1]	196006	1			T25	18		T26	8		T28	28
bins_for_gpio_bits[26]	auto[1]	auto[0]	196293	1			T25	18		T26	8		T28	27
bins_for_gpio_bits[26]	auto[1]	auto[1]	4482618	1			T21	263		T22	26231		T23	862
bins_for_gpio_bits[27]	auto[0]	auto[0]	6652693	1			T21	246		T22	28096		T23	894
bins_for_gpio_bits[27]	auto[0]	auto[1]	196567	1			T25	18		T26	4		T28	32
bins_for_gpio_bits[27]	auto[1]	auto[0]	196869	1			T25	18		T26	4		T28	32
bins_for_gpio_bits[27]	auto[1]	auto[1]	4483870	1			T21	261		T22	26464		T23	789
bins_for_gpio_bits[28]	auto[0]	auto[0]	6644766	1			T21	250		T22	27951		T23	762
bins_for_gpio_bits[28]	auto[0]	auto[1]	197560	1			T25	17		T26	5		T28	26
bins_for_gpio_bits[28]	auto[1]	auto[0]	197822	1			T25	17		T26	6		T28	26
bins_for_gpio_bits[28]	auto[1]	auto[1]	4489851	1			T21	257		T22	26609		T23	921
bins_for_gpio_bits[29]	auto[0]	auto[0]	6651074	1			T21	270		T22	26073		T23	880
bins_for_gpio_bits[29]	auto[0]	auto[1]	196163	1			T25	19		T26	7		T28	25
bins_for_gpio_bits[29]	auto[1]	auto[0]	196473	1			T25	19		T26	7		T28	25
bins_for_gpio_bits[29]	auto[1]	auto[1]	4486289	1			T21	237		T22	28487		T23	803
bins_for_gpio_bits[30]	auto[0]	auto[0]	6664139	1			T21	270		T22	29312		T23	942
bins_for_gpio_bits[30]	auto[0]	auto[1]	196868	1			T25	20		T26	7		T28	32
bins_for_gpio_bits[30]	auto[1]	auto[0]	197155	1			T25	20		T26	7		T28	32
bins_for_gpio_bits[30]	auto[1]	auto[1]	4471837	1			T21	237		T22	25248		T23	741
bins_for_gpio_bits[31]	auto[0]	auto[0]	6661611	1			T21	249		T22	27138		T23	807
bins_for_gpio_bits[31]	auto[0]	auto[1]	196677	1			T25	12		T26	7		T28	27
bins_for_gpio_bits[31]	auto[1]	auto[0]	196994	1			T25	12		T26	8		T28	27
bins_for_gpio_bits[31]	auto[1]	auto[1]	4474717	1			T21	258		T22	27422		T23	876