Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6910110 |
1 |
|
|
T21 |
306 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4799088 |
1 |
|
|
T21 |
374 |
|
T29 |
144 |
|
T31 |
137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11088222 |
1 |
|
|
T21 |
616 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
620976 |
1 |
|
|
T21 |
64 |
|
T29 |
13 |
|
T31 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6902058 |
1 |
|
|
T21 |
319 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4807140 |
1 |
|
|
T21 |
361 |
|
T29 |
186 |
|
T31 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2094714 |
1 |
|
|
T21 |
150 |
|
T29 |
113 |
|
T31 |
37 |
| auto[1] |
auto[0] |
auto[1] |
310811 |
1 |
|
|
T21 |
32 |
|
T29 |
7 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2091450 |
1 |
|
|
T21 |
147 |
|
T29 |
60 |
|
T31 |
72 |
| auto[1] |
auto[1] |
auto[1] |
310165 |
1 |
|
|
T21 |
32 |
|
T29 |
6 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6942951 |
1 |
|
|
T21 |
437 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4766247 |
1 |
|
|
T21 |
243 |
|
T29 |
169 |
|
T31 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11088616 |
1 |
|
|
T21 |
636 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
620582 |
1 |
|
|
T21 |
44 |
|
T29 |
12 |
|
T31 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6901563 |
1 |
|
|
T21 |
430 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4807635 |
1 |
|
|
T21 |
250 |
|
T29 |
193 |
|
T31 |
120 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2112004 |
1 |
|
|
T21 |
134 |
|
T29 |
90 |
|
T31 |
55 |
| auto[1] |
auto[0] |
auto[1] |
313391 |
1 |
|
|
T21 |
29 |
|
T29 |
10 |
|
T31 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2075049 |
1 |
|
|
T21 |
72 |
|
T29 |
91 |
|
T31 |
55 |
| auto[1] |
auto[1] |
auto[1] |
307191 |
1 |
|
|
T21 |
15 |
|
T29 |
2 |
|
T31 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6927266 |
1 |
|
|
T21 |
449 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4781932 |
1 |
|
|
T21 |
231 |
|
T29 |
197 |
|
T31 |
72 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11089386 |
1 |
|
|
T21 |
629 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
619812 |
1 |
|
|
T21 |
51 |
|
T29 |
7 |
|
T31 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6908519 |
1 |
|
|
T21 |
411 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4800679 |
1 |
|
|
T21 |
269 |
|
T29 |
117 |
|
T31 |
134 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2095706 |
1 |
|
|
T21 |
137 |
|
T29 |
41 |
|
T31 |
83 |
| auto[1] |
auto[0] |
auto[1] |
311487 |
1 |
|
|
T21 |
30 |
|
T29 |
4 |
|
T31 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2085161 |
1 |
|
|
T21 |
81 |
|
T29 |
69 |
|
T31 |
43 |
| auto[1] |
auto[1] |
auto[1] |
308325 |
1 |
|
|
T21 |
21 |
|
T29 |
3 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6889104 |
1 |
|
|
T21 |
260 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4820094 |
1 |
|
|
T21 |
420 |
|
T29 |
114 |
|
T31 |
120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11091399 |
1 |
|
|
T21 |
629 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
617799 |
1 |
|
|
T21 |
51 |
|
T29 |
12 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6908150 |
1 |
|
|
T21 |
432 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4801048 |
1 |
|
|
T21 |
248 |
|
T29 |
122 |
|
T31 |
122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2086337 |
1 |
|
|
T21 |
54 |
|
T29 |
60 |
|
T31 |
52 |
| auto[1] |
auto[0] |
auto[1] |
307997 |
1 |
|
|
T21 |
16 |
|
T29 |
6 |
|
T31 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2096912 |
1 |
|
|
T21 |
143 |
|
T29 |
50 |
|
T31 |
64 |
| auto[1] |
auto[1] |
auto[1] |
309802 |
1 |
|
|
T21 |
35 |
|
T29 |
6 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6904444 |
1 |
|
|
T21 |
519 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4804754 |
1 |
|
|
T21 |
161 |
|
T29 |
192 |
|
T31 |
121 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11093113 |
1 |
|
|
T21 |
619 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
616085 |
1 |
|
|
T21 |
61 |
|
T29 |
14 |
|
T31 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6929337 |
1 |
|
|
T21 |
317 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4779861 |
1 |
|
|
T21 |
363 |
|
T29 |
197 |
|
T31 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2073319 |
1 |
|
|
T21 |
225 |
|
T29 |
75 |
|
T31 |
73 |
| auto[1] |
auto[0] |
auto[1] |
305853 |
1 |
|
|
T21 |
51 |
|
T29 |
9 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2090457 |
1 |
|
|
T21 |
77 |
|
T29 |
108 |
|
T31 |
37 |
| auto[1] |
auto[1] |
auto[1] |
310232 |
1 |
|
|
T21 |
10 |
|
T29 |
5 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6896555 |
1 |
|
|
T21 |
340 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4812643 |
1 |
|
|
T21 |
340 |
|
T29 |
203 |
|
T31 |
169 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11092317 |
1 |
|
|
T21 |
602 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
616881 |
1 |
|
|
T21 |
78 |
|
T29 |
7 |
|
T31 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6924268 |
1 |
|
|
T21 |
280 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4784930 |
1 |
|
|
T21 |
400 |
|
T29 |
156 |
|
T31 |
119 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2090990 |
1 |
|
|
T21 |
126 |
|
T29 |
65 |
|
T31 |
33 |
| auto[1] |
auto[0] |
auto[1] |
308937 |
1 |
|
|
T21 |
26 |
|
T29 |
4 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2077059 |
1 |
|
|
T21 |
196 |
|
T29 |
84 |
|
T31 |
79 |
| auto[1] |
auto[1] |
auto[1] |
307944 |
1 |
|
|
T21 |
52 |
|
T29 |
3 |
|
T31 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6907017 |
1 |
|
|
T21 |
329 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4802181 |
1 |
|
|
T21 |
351 |
|
T29 |
223 |
|
T31 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11091482 |
1 |
|
|
T21 |
622 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
617716 |
1 |
|
|
T21 |
58 |
|
T29 |
17 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6921940 |
1 |
|
|
T21 |
356 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4787258 |
1 |
|
|
T21 |
324 |
|
T29 |
229 |
|
T31 |
121 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2076949 |
1 |
|
|
T21 |
149 |
|
T29 |
72 |
|
T31 |
40 |
| auto[1] |
auto[0] |
auto[1] |
307848 |
1 |
|
|
T21 |
29 |
|
T29 |
5 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2092593 |
1 |
|
|
T21 |
117 |
|
T29 |
140 |
|
T31 |
75 |
| auto[1] |
auto[1] |
auto[1] |
309868 |
1 |
|
|
T21 |
29 |
|
T29 |
12 |
|
T31 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6916497 |
1 |
|
|
T21 |
363 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4792701 |
1 |
|
|
T21 |
317 |
|
T29 |
187 |
|
T31 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11086913 |
1 |
|
|
T21 |
581 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
622285 |
1 |
|
|
T21 |
99 |
|
T29 |
8 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6890223 |
1 |
|
|
T21 |
171 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4818975 |
1 |
|
|
T21 |
509 |
|
T29 |
142 |
|
T31 |
125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2095319 |
1 |
|
|
T21 |
214 |
|
T29 |
77 |
|
T31 |
47 |
| auto[1] |
auto[0] |
auto[1] |
310709 |
1 |
|
|
T21 |
50 |
|
T29 |
3 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2101371 |
1 |
|
|
T21 |
196 |
|
T29 |
57 |
|
T31 |
72 |
| auto[1] |
auto[1] |
auto[1] |
311576 |
1 |
|
|
T21 |
49 |
|
T29 |
5 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6888667 |
1 |
|
|
T21 |
366 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4820531 |
1 |
|
|
T21 |
314 |
|
T29 |
219 |
|
T31 |
100 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11099151 |
1 |
|
|
T21 |
630 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
610047 |
1 |
|
|
T21 |
50 |
|
T29 |
14 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6958702 |
1 |
|
|
T21 |
392 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4750496 |
1 |
|
|
T21 |
288 |
|
T29 |
182 |
|
T31 |
132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2057330 |
1 |
|
|
T21 |
148 |
|
T29 |
89 |
|
T31 |
63 |
| auto[1] |
auto[0] |
auto[1] |
302319 |
1 |
|
|
T21 |
30 |
|
T29 |
6 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2083119 |
1 |
|
|
T21 |
90 |
|
T29 |
79 |
|
T31 |
63 |
| auto[1] |
auto[1] |
auto[1] |
307728 |
1 |
|
|
T21 |
20 |
|
T29 |
8 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6927161 |
1 |
|
|
T21 |
462 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4782037 |
1 |
|
|
T21 |
218 |
|
T29 |
185 |
|
T31 |
110 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11092606 |
1 |
|
|
T21 |
609 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
616592 |
1 |
|
|
T21 |
71 |
|
T29 |
15 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6922273 |
1 |
|
|
T21 |
263 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4786925 |
1 |
|
|
T21 |
417 |
|
T29 |
187 |
|
T31 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2091006 |
1 |
|
|
T21 |
271 |
|
T29 |
65 |
|
T31 |
51 |
| auto[1] |
auto[0] |
auto[1] |
308670 |
1 |
|
|
T21 |
60 |
|
T29 |
6 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2079327 |
1 |
|
|
T21 |
75 |
|
T29 |
107 |
|
T31 |
31 |
| auto[1] |
auto[1] |
auto[1] |
307922 |
1 |
|
|
T21 |
11 |
|
T29 |
9 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6914158 |
1 |
|
|
T21 |
345 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4795040 |
1 |
|
|
T21 |
335 |
|
T29 |
139 |
|
T31 |
120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11090482 |
1 |
|
|
T21 |
603 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
618716 |
1 |
|
|
T21 |
77 |
|
T29 |
8 |
|
T31 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6909456 |
1 |
|
|
T21 |
278 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4799742 |
1 |
|
|
T21 |
402 |
|
T29 |
150 |
|
T31 |
134 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2094335 |
1 |
|
|
T21 |
192 |
|
T29 |
86 |
|
T31 |
60 |
| auto[1] |
auto[0] |
auto[1] |
309103 |
1 |
|
|
T21 |
42 |
|
T29 |
5 |
|
T31 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2086691 |
1 |
|
|
T21 |
133 |
|
T29 |
56 |
|
T31 |
65 |
| auto[1] |
auto[1] |
auto[1] |
309613 |
1 |
|
|
T21 |
35 |
|
T29 |
3 |
|
T31 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6917130 |
1 |
|
|
T21 |
474 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4792068 |
1 |
|
|
T21 |
206 |
|
T29 |
141 |
|
T31 |
109 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11090322 |
1 |
|
|
T21 |
625 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
618876 |
1 |
|
|
T21 |
55 |
|
T29 |
18 |
|
T31 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6917929 |
1 |
|
|
T21 |
385 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4791269 |
1 |
|
|
T21 |
295 |
|
T29 |
218 |
|
T31 |
171 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2084455 |
1 |
|
|
T21 |
127 |
|
T29 |
116 |
|
T31 |
68 |
| auto[1] |
auto[0] |
auto[1] |
308652 |
1 |
|
|
T21 |
29 |
|
T29 |
11 |
|
T31 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2087938 |
1 |
|
|
T21 |
113 |
|
T29 |
84 |
|
T31 |
92 |
| auto[1] |
auto[1] |
auto[1] |
310224 |
1 |
|
|
T21 |
26 |
|
T29 |
7 |
|
T31 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6900831 |
1 |
|
|
T21 |
386 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4808367 |
1 |
|
|
T21 |
294 |
|
T29 |
221 |
|
T31 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11090939 |
1 |
|
|
T21 |
617 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
618259 |
1 |
|
|
T21 |
63 |
|
T29 |
12 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6913779 |
1 |
|
|
T21 |
322 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4795419 |
1 |
|
|
T21 |
358 |
|
T29 |
145 |
|
T31 |
107 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2094289 |
1 |
|
|
T21 |
199 |
|
T29 |
45 |
|
T31 |
44 |
| auto[1] |
auto[0] |
auto[1] |
310780 |
1 |
|
|
T21 |
36 |
|
T29 |
4 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2082871 |
1 |
|
|
T21 |
96 |
|
T29 |
88 |
|
T31 |
57 |
| auto[1] |
auto[1] |
auto[1] |
307479 |
1 |
|
|
T21 |
27 |
|
T29 |
8 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6923138 |
1 |
|
|
T21 |
278 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4786060 |
1 |
|
|
T21 |
402 |
|
T29 |
234 |
|
T31 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11092827 |
1 |
|
|
T21 |
619 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
616371 |
1 |
|
|
T21 |
61 |
|
T29 |
10 |
|
T31 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6921155 |
1 |
|
|
T21 |
344 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4788043 |
1 |
|
|
T21 |
336 |
|
T29 |
138 |
|
T31 |
99 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2086905 |
1 |
|
|
T21 |
123 |
|
T29 |
50 |
|
T31 |
46 |
| auto[1] |
auto[0] |
auto[1] |
308396 |
1 |
|
|
T21 |
25 |
|
T29 |
2 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2084767 |
1 |
|
|
T21 |
152 |
|
T29 |
78 |
|
T31 |
44 |
| auto[1] |
auto[1] |
auto[1] |
307975 |
1 |
|
|
T21 |
36 |
|
T29 |
8 |
|
T31 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6891856 |
1 |
|
|
T21 |
349 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4817342 |
1 |
|
|
T21 |
331 |
|
T29 |
170 |
|
T31 |
84 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11090995 |
1 |
|
|
T21 |
639 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
618203 |
1 |
|
|
T21 |
41 |
|
T29 |
16 |
|
T31 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6920526 |
1 |
|
|
T21 |
462 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4788672 |
1 |
|
|
T21 |
218 |
|
T29 |
179 |
|
T31 |
146 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2072753 |
1 |
|
|
T21 |
93 |
|
T29 |
112 |
|
T31 |
90 |
| auto[1] |
auto[0] |
auto[1] |
306823 |
1 |
|
|
T21 |
23 |
|
T29 |
10 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2097716 |
1 |
|
|
T21 |
84 |
|
T29 |
51 |
|
T31 |
47 |
| auto[1] |
auto[1] |
auto[1] |
311380 |
1 |
|
|
T21 |
18 |
|
T29 |
6 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6907504 |
1 |
|
|
T21 |
208 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4801694 |
1 |
|
|
T21 |
472 |
|
T29 |
219 |
|
T31 |
134 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11083236 |
1 |
|
|
T21 |
607 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
625962 |
1 |
|
|
T21 |
73 |
|
T29 |
12 |
|
T31 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6866575 |
1 |
|
|
T21 |
279 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4842623 |
1 |
|
|
T21 |
401 |
|
T29 |
180 |
|
T31 |
127 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2124947 |
1 |
|
|
T21 |
137 |
|
T29 |
52 |
|
T31 |
49 |
| auto[1] |
auto[0] |
auto[1] |
315997 |
1 |
|
|
T21 |
32 |
|
T29 |
4 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2091714 |
1 |
|
|
T21 |
191 |
|
T29 |
116 |
|
T31 |
73 |
| auto[1] |
auto[1] |
auto[1] |
309965 |
1 |
|
|
T21 |
41 |
|
T29 |
8 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6912161 |
1 |
|
|
T21 |
287 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4797037 |
1 |
|
|
T21 |
393 |
|
T29 |
213 |
|
T31 |
140 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11092674 |
1 |
|
|
T21 |
633 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
616524 |
1 |
|
|
T21 |
47 |
|
T29 |
8 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6922889 |
1 |
|
|
T21 |
435 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4786309 |
1 |
|
|
T21 |
245 |
|
T29 |
194 |
|
T31 |
80 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2074886 |
1 |
|
|
T21 |
74 |
|
T29 |
62 |
|
T31 |
22 |
| auto[1] |
auto[0] |
auto[1] |
306661 |
1 |
|
|
T21 |
18 |
|
T29 |
2 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2094899 |
1 |
|
|
T21 |
124 |
|
T29 |
124 |
|
T31 |
52 |
| auto[1] |
auto[1] |
auto[1] |
309863 |
1 |
|
|
T21 |
29 |
|
T29 |
6 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6934299 |
1 |
|
|
T21 |
361 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4774899 |
1 |
|
|
T21 |
319 |
|
T29 |
256 |
|
T31 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11091336 |
1 |
|
|
T21 |
613 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
617862 |
1 |
|
|
T21 |
67 |
|
T29 |
14 |
|
T31 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6910651 |
1 |
|
|
T21 |
345 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4798547 |
1 |
|
|
T21 |
335 |
|
T29 |
189 |
|
T31 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2094462 |
1 |
|
|
T21 |
102 |
|
T29 |
56 |
|
T31 |
63 |
| auto[1] |
auto[0] |
auto[1] |
309266 |
1 |
|
|
T21 |
27 |
|
T29 |
4 |
|
T31 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2086223 |
1 |
|
|
T21 |
166 |
|
T29 |
119 |
|
T31 |
26 |
| auto[1] |
auto[1] |
auto[1] |
308596 |
1 |
|
|
T21 |
40 |
|
T29 |
10 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6927407 |
1 |
|
|
T21 |
421 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4781791 |
1 |
|
|
T21 |
259 |
|
T29 |
243 |
|
T31 |
148 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11093094 |
1 |
|
|
T21 |
631 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
616104 |
1 |
|
|
T21 |
49 |
|
T29 |
9 |
|
T31 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6930834 |
1 |
|
|
T21 |
422 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4778364 |
1 |
|
|
T21 |
258 |
|
T29 |
160 |
|
T31 |
103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2093261 |
1 |
|
|
T21 |
130 |
|
T29 |
60 |
|
T31 |
32 |
| auto[1] |
auto[0] |
auto[1] |
311174 |
1 |
|
|
T21 |
32 |
|
T29 |
2 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2068999 |
1 |
|
|
T21 |
79 |
|
T29 |
91 |
|
T31 |
60 |
| auto[1] |
auto[1] |
auto[1] |
304930 |
1 |
|
|
T21 |
17 |
|
T29 |
7 |
|
T31 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6950475 |
1 |
|
|
T21 |
348 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4758723 |
1 |
|
|
T21 |
332 |
|
T29 |
133 |
|
T31 |
130 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11092811 |
1 |
|
|
T21 |
631 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
616387 |
1 |
|
|
T21 |
49 |
|
T29 |
11 |
|
T31 |
14 |