Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6891717 |
1 |
|
|
T21 |
238 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4817481 |
1 |
|
|
T21 |
442 |
|
T29 |
167 |
|
T31 |
143 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11084494 |
1 |
|
|
T21 |
623 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
624704 |
1 |
|
|
T21 |
57 |
|
T29 |
16 |
|
T31 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870624 |
1 |
|
|
T21 |
395 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4838574 |
1 |
|
|
T21 |
285 |
|
T29 |
170 |
|
T31 |
148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2110394 |
1 |
|
|
T21 |
62 |
|
T29 |
88 |
|
T31 |
49 |
| auto[1] |
auto[0] |
auto[1] |
313120 |
1 |
|
|
T21 |
10 |
|
T29 |
5 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2103476 |
1 |
|
|
T21 |
166 |
|
T29 |
66 |
|
T31 |
89 |
| auto[1] |
auto[1] |
auto[1] |
311584 |
1 |
|
|
T21 |
47 |
|
T29 |
11 |
|
T31 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |