Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6929322 |
1 |
|
|
T21 |
395 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4779876 |
1 |
|
|
T21 |
285 |
|
T29 |
171 |
|
T31 |
144 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11086698 |
1 |
|
|
T21 |
597 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
622500 |
1 |
|
|
T21 |
83 |
|
T29 |
12 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6894502 |
1 |
|
|
T21 |
237 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4814696 |
1 |
|
|
T21 |
443 |
|
T29 |
201 |
|
T31 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2099456 |
1 |
|
|
T21 |
196 |
|
T29 |
111 |
|
T31 |
37 |
| auto[1] |
auto[0] |
auto[1] |
311833 |
1 |
|
|
T21 |
47 |
|
T29 |
8 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2092740 |
1 |
|
|
T21 |
164 |
|
T29 |
78 |
|
T31 |
45 |
| auto[1] |
auto[1] |
auto[1] |
310667 |
1 |
|
|
T21 |
36 |
|
T29 |
4 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |