Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6942951 |
1 |
|
|
T21 |
437 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4766247 |
1 |
|
|
T21 |
243 |
|
T29 |
169 |
|
T31 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9728209 |
1 |
|
|
T21 |
535 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1980989 |
1 |
|
|
T21 |
145 |
|
T29 |
83 |
|
T31 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6928337 |
1 |
|
|
T21 |
387 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4780861 |
1 |
|
|
T21 |
293 |
|
T29 |
198 |
|
T31 |
58 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1415428 |
1 |
|
|
T21 |
97 |
|
T29 |
72 |
|
T31 |
15 |
| auto[1] |
auto[0] |
auto[1] |
999220 |
1 |
|
|
T21 |
74 |
|
T29 |
50 |
|
T31 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1384444 |
1 |
|
|
T21 |
51 |
|
T29 |
43 |
|
T31 |
24 |
| auto[1] |
auto[1] |
auto[1] |
981769 |
1 |
|
|
T21 |
71 |
|
T29 |
33 |
|
T31 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |