Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6889104 |
1 |
|
|
T21 |
260 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4820094 |
1 |
|
|
T21 |
420 |
|
T29 |
114 |
|
T31 |
120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9722832 |
1 |
|
|
T21 |
528 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1986366 |
1 |
|
|
T21 |
152 |
|
T29 |
103 |
|
T31 |
56 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6912705 |
1 |
|
|
T21 |
369 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4796493 |
1 |
|
|
T21 |
311 |
|
T29 |
201 |
|
T31 |
100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1391602 |
1 |
|
|
T21 |
65 |
|
T29 |
70 |
|
T31 |
30 |
| auto[1] |
auto[0] |
auto[1] |
984579 |
1 |
|
|
T21 |
55 |
|
T29 |
69 |
|
T31 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1418525 |
1 |
|
|
T21 |
94 |
|
T29 |
28 |
|
T31 |
14 |
| auto[1] |
auto[1] |
auto[1] |
1001787 |
1 |
|
|
T21 |
97 |
|
T29 |
34 |
|
T31 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |