Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6904444 |
1 |
|
|
T21 |
519 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4804754 |
1 |
|
|
T21 |
161 |
|
T29 |
192 |
|
T31 |
121 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9722992 |
1 |
|
|
T21 |
489 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1986206 |
1 |
|
|
T21 |
191 |
|
T29 |
77 |
|
T31 |
106 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6916866 |
1 |
|
|
T21 |
290 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4792332 |
1 |
|
|
T21 |
390 |
|
T29 |
203 |
|
T31 |
164 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1396117 |
1 |
|
|
T21 |
163 |
|
T29 |
68 |
|
T31 |
25 |
| auto[1] |
auto[0] |
auto[1] |
989359 |
1 |
|
|
T21 |
135 |
|
T29 |
49 |
|
T31 |
66 |
| auto[1] |
auto[1] |
auto[0] |
1410009 |
1 |
|
|
T21 |
36 |
|
T29 |
58 |
|
T31 |
33 |
| auto[1] |
auto[1] |
auto[1] |
996847 |
1 |
|
|
T21 |
56 |
|
T29 |
28 |
|
T31 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |