Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6896555 |
1 |
|
|
T21 |
340 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4812643 |
1 |
|
|
T21 |
340 |
|
T29 |
203 |
|
T31 |
169 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9727082 |
1 |
|
|
T21 |
504 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1982116 |
1 |
|
|
T21 |
176 |
|
T29 |
101 |
|
T31 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6922439 |
1 |
|
|
T21 |
325 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4786759 |
1 |
|
|
T21 |
355 |
|
T29 |
192 |
|
T31 |
100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1399350 |
1 |
|
|
T21 |
78 |
|
T29 |
34 |
|
T31 |
22 |
| auto[1] |
auto[0] |
auto[1] |
988979 |
1 |
|
|
T21 |
70 |
|
T29 |
57 |
|
T31 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1405293 |
1 |
|
|
T21 |
101 |
|
T29 |
57 |
|
T31 |
29 |
| auto[1] |
auto[1] |
auto[1] |
993137 |
1 |
|
|
T21 |
106 |
|
T29 |
44 |
|
T31 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |