Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6916497 |
1 |
|
|
T21 |
363 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4792701 |
1 |
|
|
T21 |
317 |
|
T29 |
187 |
|
T31 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9715094 |
1 |
|
|
T21 |
520 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1994104 |
1 |
|
|
T21 |
160 |
|
T29 |
111 |
|
T31 |
63 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6904725 |
1 |
|
|
T21 |
345 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4804473 |
1 |
|
|
T21 |
335 |
|
T29 |
177 |
|
T31 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1413992 |
1 |
|
|
T21 |
82 |
|
T29 |
30 |
|
T31 |
15 |
| auto[1] |
auto[0] |
auto[1] |
1003838 |
1 |
|
|
T21 |
71 |
|
T29 |
72 |
|
T31 |
34 |
| auto[1] |
auto[1] |
auto[0] |
1396377 |
1 |
|
|
T21 |
93 |
|
T29 |
36 |
|
T31 |
37 |
| auto[1] |
auto[1] |
auto[1] |
990266 |
1 |
|
|
T21 |
89 |
|
T29 |
39 |
|
T31 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |