Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6927161 |
1 |
|
|
T21 |
462 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4782037 |
1 |
|
|
T21 |
218 |
|
T29 |
185 |
|
T31 |
110 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9736466 |
1 |
|
|
T21 |
534 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1972732 |
1 |
|
|
T21 |
146 |
|
T29 |
91 |
|
T31 |
55 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6942784 |
1 |
|
|
T21 |
360 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4766414 |
1 |
|
|
T21 |
320 |
|
T29 |
180 |
|
T31 |
137 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1398224 |
1 |
|
|
T21 |
120 |
|
T29 |
46 |
|
T31 |
53 |
| auto[1] |
auto[0] |
auto[1] |
988934 |
1 |
|
|
T21 |
104 |
|
T29 |
47 |
|
T31 |
33 |
| auto[1] |
auto[1] |
auto[0] |
1395458 |
1 |
|
|
T21 |
54 |
|
T29 |
43 |
|
T31 |
29 |
| auto[1] |
auto[1] |
auto[1] |
983798 |
1 |
|
|
T21 |
42 |
|
T29 |
44 |
|
T31 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |