Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6914158 |
1 |
|
|
T21 |
345 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4795040 |
1 |
|
|
T21 |
335 |
|
T29 |
139 |
|
T31 |
120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9715122 |
1 |
|
|
T21 |
495 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1994076 |
1 |
|
|
T21 |
185 |
|
T29 |
132 |
|
T31 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6882381 |
1 |
|
|
T21 |
323 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4826817 |
1 |
|
|
T21 |
357 |
|
T29 |
258 |
|
T31 |
132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1422508 |
1 |
|
|
T21 |
94 |
|
T29 |
70 |
|
T31 |
62 |
| auto[1] |
auto[0] |
auto[1] |
998695 |
1 |
|
|
T21 |
114 |
|
T29 |
88 |
|
T31 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1410233 |
1 |
|
|
T21 |
78 |
|
T29 |
56 |
|
T31 |
31 |
| auto[1] |
auto[1] |
auto[1] |
995381 |
1 |
|
|
T21 |
71 |
|
T29 |
44 |
|
T31 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |