Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6917130 |
1 |
|
|
T21 |
474 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4792068 |
1 |
|
|
T21 |
206 |
|
T29 |
141 |
|
T31 |
109 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9726497 |
1 |
|
|
T21 |
395 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1982701 |
1 |
|
|
T21 |
285 |
|
T29 |
62 |
|
T31 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6919784 |
1 |
|
|
T21 |
120 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4789414 |
1 |
|
|
T21 |
560 |
|
T29 |
166 |
|
T31 |
122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1405002 |
1 |
|
|
T21 |
186 |
|
T29 |
73 |
|
T31 |
35 |
| auto[1] |
auto[0] |
auto[1] |
996304 |
1 |
|
|
T21 |
209 |
|
T29 |
44 |
|
T31 |
33 |
| auto[1] |
auto[1] |
auto[0] |
1401711 |
1 |
|
|
T21 |
89 |
|
T29 |
31 |
|
T31 |
38 |
| auto[1] |
auto[1] |
auto[1] |
986397 |
1 |
|
|
T21 |
76 |
|
T29 |
18 |
|
T31 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |