Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6900831 |
1 |
|
|
T21 |
386 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4808367 |
1 |
|
|
T21 |
294 |
|
T29 |
221 |
|
T31 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9728010 |
1 |
|
|
T21 |
521 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1981188 |
1 |
|
|
T21 |
159 |
|
T29 |
100 |
|
T31 |
89 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6924333 |
1 |
|
|
T21 |
354 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4784865 |
1 |
|
|
T21 |
326 |
|
T29 |
240 |
|
T31 |
137 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1399969 |
1 |
|
|
T21 |
91 |
|
T29 |
63 |
|
T31 |
24 |
| auto[1] |
auto[0] |
auto[1] |
990360 |
1 |
|
|
T21 |
111 |
|
T29 |
36 |
|
T31 |
49 |
| auto[1] |
auto[1] |
auto[0] |
1403708 |
1 |
|
|
T21 |
76 |
|
T29 |
77 |
|
T31 |
24 |
| auto[1] |
auto[1] |
auto[1] |
990828 |
1 |
|
|
T21 |
48 |
|
T29 |
64 |
|
T31 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |