Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6923138 |
1 |
|
|
T21 |
278 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4786060 |
1 |
|
|
T21 |
402 |
|
T29 |
234 |
|
T31 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9716376 |
1 |
|
|
T21 |
482 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1992822 |
1 |
|
|
T21 |
198 |
|
T29 |
78 |
|
T31 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6902785 |
1 |
|
|
T21 |
291 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4806413 |
1 |
|
|
T21 |
389 |
|
T29 |
150 |
|
T31 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1418883 |
1 |
|
|
T21 |
76 |
|
T29 |
40 |
|
T31 |
37 |
| auto[1] |
auto[0] |
auto[1] |
1002986 |
1 |
|
|
T21 |
74 |
|
T29 |
35 |
|
T31 |
10 |
| auto[1] |
auto[1] |
auto[0] |
1394708 |
1 |
|
|
T21 |
115 |
|
T29 |
32 |
|
T31 |
37 |
| auto[1] |
auto[1] |
auto[1] |
989836 |
1 |
|
|
T21 |
124 |
|
T29 |
43 |
|
T31 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |