Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6891856 |
1 |
|
|
T21 |
349 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4817342 |
1 |
|
|
T21 |
331 |
|
T29 |
170 |
|
T31 |
84 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9731965 |
1 |
|
|
T21 |
547 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1977233 |
1 |
|
|
T21 |
133 |
|
T29 |
96 |
|
T31 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6926290 |
1 |
|
|
T21 |
402 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4782908 |
1 |
|
|
T21 |
278 |
|
T29 |
195 |
|
T31 |
138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1391254 |
1 |
|
|
T21 |
65 |
|
T29 |
72 |
|
T31 |
48 |
| auto[1] |
auto[0] |
auto[1] |
984132 |
1 |
|
|
T21 |
61 |
|
T29 |
43 |
|
T31 |
41 |
| auto[1] |
auto[1] |
auto[0] |
1414421 |
1 |
|
|
T21 |
80 |
|
T29 |
27 |
|
T31 |
41 |
| auto[1] |
auto[1] |
auto[1] |
993101 |
1 |
|
|
T21 |
72 |
|
T29 |
53 |
|
T31 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |