Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6934299 |
1 |
|
|
T21 |
361 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4774899 |
1 |
|
|
T21 |
319 |
|
T29 |
256 |
|
T31 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9711747 |
1 |
|
|
T21 |
492 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
1997451 |
1 |
|
|
T21 |
188 |
|
T29 |
84 |
|
T31 |
48 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6888568 |
1 |
|
|
T21 |
325 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4820630 |
1 |
|
|
T21 |
355 |
|
T29 |
139 |
|
T31 |
104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1420575 |
1 |
|
|
T21 |
98 |
|
T29 |
14 |
|
T31 |
37 |
| auto[1] |
auto[0] |
auto[1] |
1005242 |
1 |
|
|
T21 |
123 |
|
T29 |
37 |
|
T31 |
30 |
| auto[1] |
auto[1] |
auto[0] |
1402604 |
1 |
|
|
T21 |
69 |
|
T29 |
41 |
|
T31 |
19 |
| auto[1] |
auto[1] |
auto[1] |
992209 |
1 |
|
|
T21 |
65 |
|
T29 |
47 |
|
T31 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |