Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6896105 |
1 |
|
|
T21 |
224 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4813093 |
1 |
|
|
T21 |
456 |
|
T29 |
169 |
|
T31 |
154 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11084797 |
1 |
|
|
T21 |
617 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
624401 |
1 |
|
|
T21 |
63 |
|
T29 |
12 |
|
T31 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6877216 |
1 |
|
|
T21 |
354 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4831982 |
1 |
|
|
T21 |
326 |
|
T29 |
178 |
|
T31 |
156 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2104205 |
1 |
|
|
T21 |
73 |
|
T29 |
83 |
|
T31 |
44 |
| auto[1] |
auto[0] |
auto[1] |
312004 |
1 |
|
|
T21 |
20 |
|
T29 |
7 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2103376 |
1 |
|
|
T21 |
190 |
|
T29 |
83 |
|
T31 |
102 |
| auto[1] |
auto[1] |
auto[1] |
312397 |
1 |
|
|
T21 |
43 |
|
T29 |
5 |
|
T31 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |