Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6948441 |
1 |
|
|
T21 |
380 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4760757 |
1 |
|
|
T21 |
300 |
|
T29 |
162 |
|
T31 |
129 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11087872 |
1 |
|
|
T21 |
597 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
621326 |
1 |
|
|
T21 |
83 |
|
T29 |
11 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6897868 |
1 |
|
|
T21 |
249 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4811330 |
1 |
|
|
T21 |
431 |
|
T29 |
150 |
|
T31 |
92 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2120505 |
1 |
|
|
T21 |
237 |
|
T29 |
67 |
|
T31 |
29 |
| auto[1] |
auto[0] |
auto[1] |
315490 |
1 |
|
|
T21 |
55 |
|
T29 |
6 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2069499 |
1 |
|
|
T21 |
111 |
|
T29 |
72 |
|
T31 |
57 |
| auto[1] |
auto[1] |
auto[1] |
305836 |
1 |
|
|
T21 |
28 |
|
T29 |
5 |
|
T31 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |