Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6925977 |
1 |
|
|
T21 |
224 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4783221 |
1 |
|
|
T21 |
456 |
|
T29 |
172 |
|
T31 |
84 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11095141 |
1 |
|
|
T21 |
595 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
614057 |
1 |
|
|
T21 |
85 |
|
T29 |
10 |
|
T31 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6947565 |
1 |
|
|
T21 |
253 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4761633 |
1 |
|
|
T21 |
427 |
|
T29 |
168 |
|
T31 |
124 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2086427 |
1 |
|
|
T21 |
129 |
|
T29 |
69 |
|
T31 |
78 |
| auto[1] |
auto[0] |
auto[1] |
309879 |
1 |
|
|
T21 |
36 |
|
T29 |
6 |
|
T31 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2061149 |
1 |
|
|
T21 |
213 |
|
T29 |
89 |
|
T31 |
36 |
| auto[1] |
auto[1] |
auto[1] |
304178 |
1 |
|
|
T21 |
49 |
|
T29 |
4 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |