Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6914668 |
1 |
|
|
T21 |
366 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4794530 |
1 |
|
|
T21 |
314 |
|
T29 |
191 |
|
T31 |
138 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11087194 |
1 |
|
|
T21 |
613 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
622004 |
1 |
|
|
T21 |
67 |
|
T29 |
10 |
|
T31 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6894107 |
1 |
|
|
T21 |
334 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4815091 |
1 |
|
|
T21 |
346 |
|
T29 |
138 |
|
T31 |
110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2101791 |
1 |
|
|
T21 |
149 |
|
T29 |
63 |
|
T31 |
41 |
| auto[1] |
auto[0] |
auto[1] |
311517 |
1 |
|
|
T21 |
33 |
|
T29 |
6 |
|
T31 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2091296 |
1 |
|
|
T21 |
130 |
|
T29 |
65 |
|
T31 |
60 |
| auto[1] |
auto[1] |
auto[1] |
310487 |
1 |
|
|
T21 |
34 |
|
T29 |
4 |
|
T31 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |