Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6910342 |
1 |
|
|
T21 |
397 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4798856 |
1 |
|
|
T21 |
283 |
|
T29 |
158 |
|
T31 |
120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11089706 |
1 |
|
|
T21 |
629 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
619492 |
1 |
|
|
T21 |
51 |
|
T29 |
15 |
|
T31 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6908167 |
1 |
|
|
T21 |
397 |
|
T22 |
54560 |
|
T23 |
1683 |
| auto[1] |
4801031 |
1 |
|
|
T21 |
283 |
|
T29 |
164 |
|
T31 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2092813 |
1 |
|
|
T21 |
128 |
|
T29 |
90 |
|
T31 |
48 |
| auto[1] |
auto[0] |
auto[1] |
309733 |
1 |
|
|
T21 |
32 |
|
T29 |
9 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2088726 |
1 |
|
|
T21 |
104 |
|
T29 |
59 |
|
T31 |
49 |
| auto[1] |
auto[1] |
auto[1] |
309759 |
1 |
|
|
T21 |
19 |
|
T29 |
6 |
|
T31 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |