Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T764 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2650176374 Jul 16 04:54:07 PM PDT 24 Jul 16 04:54:08 PM PDT 24 48883540 ps
T107 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3301628328 Jul 16 04:53:49 PM PDT 24 Jul 16 04:53:51 PM PDT 24 15313037 ps
T108 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.888649025 Jul 16 04:53:54 PM PDT 24 Jul 16 04:53:55 PM PDT 24 33806750 ps
T765 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3211138257 Jul 16 04:54:07 PM PDT 24 Jul 16 04:54:09 PM PDT 24 48645139 ps
T766 /workspace/coverage/cover_reg_top/24.gpio_intr_test.996513418 Jul 16 04:54:13 PM PDT 24 Jul 16 04:54:15 PM PDT 24 64521681 ps
T767 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1791587148 Jul 16 04:53:44 PM PDT 24 Jul 16 04:53:46 PM PDT 24 13754490 ps
T768 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.554322351 Jul 16 04:53:50 PM PDT 24 Jul 16 04:53:52 PM PDT 24 31700724 ps
T769 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2405499569 Jul 16 04:54:08 PM PDT 24 Jul 16 04:54:09 PM PDT 24 41735577 ps
T770 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1041365086 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:13 PM PDT 24 19493834 ps
T771 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1026340771 Jul 16 04:53:55 PM PDT 24 Jul 16 04:53:56 PM PDT 24 77778385 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4132928788 Jul 16 04:53:45 PM PDT 24 Jul 16 04:53:50 PM PDT 24 340192023 ps
T773 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.524229311 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:03 PM PDT 24 84183617 ps
T49 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.84119324 Jul 16 04:53:45 PM PDT 24 Jul 16 04:53:47 PM PDT 24 84862040 ps
T774 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1859508310 Jul 16 04:54:22 PM PDT 24 Jul 16 04:54:23 PM PDT 24 22886980 ps
T775 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2684087415 Jul 16 04:54:10 PM PDT 24 Jul 16 04:54:11 PM PDT 24 11643215 ps
T776 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2551992635 Jul 16 04:54:05 PM PDT 24 Jul 16 04:54:07 PM PDT 24 66596088 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_intr_test.45928401 Jul 16 04:54:07 PM PDT 24 Jul 16 04:54:09 PM PDT 24 55062742 ps
T778 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3559728145 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:17 PM PDT 24 22373642 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3533754736 Jul 16 04:53:42 PM PDT 24 Jul 16 04:53:44 PM PDT 24 17170899 ps
T779 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2801779617 Jul 16 04:53:46 PM PDT 24 Jul 16 04:53:48 PM PDT 24 41692638 ps
T780 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2814083374 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:16 PM PDT 24 38871775 ps
T781 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1016928388 Jul 16 04:53:55 PM PDT 24 Jul 16 04:53:56 PM PDT 24 36674809 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.520914778 Jul 16 04:53:47 PM PDT 24 Jul 16 04:53:49 PM PDT 24 23239801 ps
T783 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3757119568 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:13 PM PDT 24 30767207 ps
T784 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1630138948 Jul 16 04:53:56 PM PDT 24 Jul 16 04:54:00 PM PDT 24 224287634 ps
T785 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4211911808 Jul 16 04:53:58 PM PDT 24 Jul 16 04:54:01 PM PDT 24 49408774 ps
T786 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2782791687 Jul 16 04:54:09 PM PDT 24 Jul 16 04:54:11 PM PDT 24 32495186 ps
T787 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1986026671 Jul 16 04:53:53 PM PDT 24 Jul 16 04:53:54 PM PDT 24 34733959 ps
T788 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1392405448 Jul 16 04:54:07 PM PDT 24 Jul 16 04:54:09 PM PDT 24 13266514 ps
T789 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3703681330 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:13 PM PDT 24 17474524 ps
T790 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3993837004 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:16 PM PDT 24 67139696 ps
T791 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1508497514 Jul 16 04:53:45 PM PDT 24 Jul 16 04:53:47 PM PDT 24 50538915 ps
T792 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3611459356 Jul 16 04:54:13 PM PDT 24 Jul 16 04:54:16 PM PDT 24 13198554 ps
T793 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2089323263 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:03 PM PDT 24 59365105 ps
T794 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2992176813 Jul 16 04:54:06 PM PDT 24 Jul 16 04:54:08 PM PDT 24 173587347 ps
T93 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.492736601 Jul 16 04:54:01 PM PDT 24 Jul 16 04:54:04 PM PDT 24 37771971 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4050846240 Jul 16 04:53:46 PM PDT 24 Jul 16 04:53:48 PM PDT 24 16435419 ps
T795 /workspace/coverage/cover_reg_top/45.gpio_intr_test.649545472 Jul 16 04:54:13 PM PDT 24 Jul 16 04:54:15 PM PDT 24 49389407 ps
T796 /workspace/coverage/cover_reg_top/7.gpio_intr_test.912632977 Jul 16 04:53:53 PM PDT 24 Jul 16 04:53:54 PM PDT 24 19207747 ps
T797 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2072791826 Jul 16 04:54:01 PM PDT 24 Jul 16 04:54:04 PM PDT 24 28979047 ps
T798 /workspace/coverage/cover_reg_top/28.gpio_intr_test.911992835 Jul 16 04:54:11 PM PDT 24 Jul 16 04:54:12 PM PDT 24 17603152 ps
T799 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3842734392 Jul 16 04:53:56 PM PDT 24 Jul 16 04:53:57 PM PDT 24 31307036 ps
T800 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3123809758 Jul 16 04:53:56 PM PDT 24 Jul 16 04:53:58 PM PDT 24 40541022 ps
T801 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1209062744 Jul 16 04:53:45 PM PDT 24 Jul 16 04:53:47 PM PDT 24 70739297 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3431760236 Jul 16 04:54:07 PM PDT 24 Jul 16 04:54:09 PM PDT 24 32326851 ps
T98 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.906279702 Jul 16 04:53:42 PM PDT 24 Jul 16 04:53:45 PM PDT 24 13340864 ps
T802 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2840260101 Jul 16 04:53:55 PM PDT 24 Jul 16 04:53:56 PM PDT 24 48664323 ps
T803 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2588138419 Jul 16 04:53:57 PM PDT 24 Jul 16 04:54:02 PM PDT 24 184239658 ps
T804 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3381704783 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:03 PM PDT 24 113431872 ps
T805 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3174961468 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:02 PM PDT 24 155096635 ps
T806 /workspace/coverage/cover_reg_top/49.gpio_intr_test.745476915 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:13 PM PDT 24 35599990 ps
T112 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2120132365 Jul 16 04:54:07 PM PDT 24 Jul 16 04:54:10 PM PDT 24 334385497 ps
T807 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2454278141 Jul 16 04:53:47 PM PDT 24 Jul 16 04:53:51 PM PDT 24 64499761 ps
T808 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3683673675 Jul 16 04:53:58 PM PDT 24 Jul 16 04:54:01 PM PDT 24 14772154 ps
T809 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4238140126 Jul 16 04:54:08 PM PDT 24 Jul 16 04:54:09 PM PDT 24 24167792 ps
T810 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3400046735 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:02 PM PDT 24 67341696 ps
T811 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1901417848 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:02 PM PDT 24 60748977 ps
T812 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2958462045 Jul 16 04:54:10 PM PDT 24 Jul 16 04:54:11 PM PDT 24 42317961 ps
T813 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2546851241 Jul 16 04:54:13 PM PDT 24 Jul 16 04:54:15 PM PDT 24 25378183 ps
T96 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2986043948 Jul 16 04:54:01 PM PDT 24 Jul 16 04:54:06 PM PDT 24 81946246 ps
T814 /workspace/coverage/cover_reg_top/26.gpio_intr_test.4196686929 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:17 PM PDT 24 48812402 ps
T815 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.830858045 Jul 16 04:53:44 PM PDT 24 Jul 16 04:53:46 PM PDT 24 49588961 ps
T816 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2561564967 Jul 16 04:53:40 PM PDT 24 Jul 16 04:53:43 PM PDT 24 51571188 ps
T817 /workspace/coverage/cover_reg_top/10.gpio_intr_test.734789166 Jul 16 04:53:56 PM PDT 24 Jul 16 04:53:58 PM PDT 24 13362270 ps
T818 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.730495379 Jul 16 04:53:56 PM PDT 24 Jul 16 04:53:57 PM PDT 24 83302909 ps
T819 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3190269088 Jul 16 04:53:43 PM PDT 24 Jul 16 04:53:48 PM PDT 24 261680074 ps
T820 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4158885399 Jul 16 04:53:46 PM PDT 24 Jul 16 04:53:48 PM PDT 24 17740284 ps
T821 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.606429422 Jul 16 04:53:57 PM PDT 24 Jul 16 04:54:00 PM PDT 24 152471025 ps
T822 /workspace/coverage/cover_reg_top/13.gpio_intr_test.331236817 Jul 16 04:54:04 PM PDT 24 Jul 16 04:54:05 PM PDT 24 15633409 ps
T823 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.253972691 Jul 16 04:53:58 PM PDT 24 Jul 16 04:54:02 PM PDT 24 134163330 ps
T97 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1461303976 Jul 16 04:53:56 PM PDT 24 Jul 16 04:53:57 PM PDT 24 67987598 ps
T824 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2234913141 Jul 16 04:53:58 PM PDT 24 Jul 16 04:54:03 PM PDT 24 1038728656 ps
T825 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.629600200 Jul 16 04:53:57 PM PDT 24 Jul 16 04:54:00 PM PDT 24 73156497 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2010109861 Jul 16 04:53:45 PM PDT 24 Jul 16 04:53:47 PM PDT 24 13412555 ps
T827 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2535077413 Jul 16 04:53:46 PM PDT 24 Jul 16 04:53:50 PM PDT 24 170702041 ps
T828 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3033188519 Jul 16 04:54:06 PM PDT 24 Jul 16 04:54:10 PM PDT 24 2500248392 ps
T829 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2882524900 Jul 16 04:53:42 PM PDT 24 Jul 16 04:53:45 PM PDT 24 15048356 ps
T830 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2621759208 Jul 16 04:53:57 PM PDT 24 Jul 16 04:54:00 PM PDT 24 92389926 ps
T831 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2662912482 Jul 16 04:53:46 PM PDT 24 Jul 16 04:53:48 PM PDT 24 22066974 ps
T832 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3138577701 Jul 16 04:54:24 PM PDT 24 Jul 16 04:54:25 PM PDT 24 44812117 ps
T833 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1630911013 Jul 16 04:53:47 PM PDT 24 Jul 16 04:53:49 PM PDT 24 13956428 ps
T99 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.475634542 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:02 PM PDT 24 11615934 ps
T834 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3932401577 Jul 16 04:54:01 PM PDT 24 Jul 16 04:54:04 PM PDT 24 21432217 ps
T835 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2676187780 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:02 PM PDT 24 84104411 ps
T836 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2859911719 Jul 16 04:53:46 PM PDT 24 Jul 16 04:53:49 PM PDT 24 35032337 ps
T837 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.442001250 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:02 PM PDT 24 476476942 ps
T100 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.559740166 Jul 16 04:53:59 PM PDT 24 Jul 16 04:54:02 PM PDT 24 45993389 ps
T838 /workspace/coverage/cover_reg_top/8.gpio_intr_test.648752830 Jul 16 04:54:01 PM PDT 24 Jul 16 04:54:04 PM PDT 24 32020006 ps
T839 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1011820718 Jul 16 05:29:07 PM PDT 24 Jul 16 05:29:09 PM PDT 24 46495672 ps
T840 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3197295350 Jul 16 05:29:12 PM PDT 24 Jul 16 05:29:14 PM PDT 24 72846475 ps
T841 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.239720154 Jul 16 05:29:21 PM PDT 24 Jul 16 05:29:23 PM PDT 24 60349874 ps
T842 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3215889257 Jul 16 05:29:12 PM PDT 24 Jul 16 05:29:13 PM PDT 24 29018025 ps
T843 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3584521112 Jul 16 05:29:11 PM PDT 24 Jul 16 05:29:12 PM PDT 24 50947417 ps
T844 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2258126271 Jul 16 05:28:57 PM PDT 24 Jul 16 05:29:03 PM PDT 24 48644677 ps
T845 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.707626516 Jul 16 05:32:31 PM PDT 24 Jul 16 05:32:33 PM PDT 24 101954950 ps
T846 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2324585093 Jul 16 05:29:09 PM PDT 24 Jul 16 05:29:10 PM PDT 24 40049470 ps
T847 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2254198985 Jul 16 05:29:25 PM PDT 24 Jul 16 05:29:27 PM PDT 24 92574015 ps
T848 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1095107153 Jul 16 05:29:09 PM PDT 24 Jul 16 05:29:11 PM PDT 24 151059868 ps
T849 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4258809775 Jul 16 05:36:09 PM PDT 24 Jul 16 05:36:10 PM PDT 24 220209428 ps
T850 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1344491278 Jul 16 05:28:54 PM PDT 24 Jul 16 05:28:59 PM PDT 24 37609632 ps
T851 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3953013436 Jul 16 05:29:12 PM PDT 24 Jul 16 05:29:13 PM PDT 24 32120216 ps
T852 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.618460940 Jul 16 05:34:11 PM PDT 24 Jul 16 05:34:13 PM PDT 24 294630785 ps
T853 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.552181497 Jul 16 05:32:31 PM PDT 24 Jul 16 05:32:33 PM PDT 24 69210830 ps
T854 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2058748218 Jul 16 05:29:05 PM PDT 24 Jul 16 05:29:06 PM PDT 24 170630364 ps
T855 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604096411 Jul 16 05:29:22 PM PDT 24 Jul 16 05:29:24 PM PDT 24 93046914 ps
T856 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3576097021 Jul 16 05:29:09 PM PDT 24 Jul 16 05:29:11 PM PDT 24 51193096 ps
T857 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3217671209 Jul 16 05:36:52 PM PDT 24 Jul 16 05:36:54 PM PDT 24 30375854 ps
T858 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.686977207 Jul 16 05:29:11 PM PDT 24 Jul 16 05:29:13 PM PDT 24 99174874 ps
T859 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2444047179 Jul 16 05:29:07 PM PDT 24 Jul 16 05:29:08 PM PDT 24 242305643 ps
T860 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.913241608 Jul 16 05:29:08 PM PDT 24 Jul 16 05:29:09 PM PDT 24 124671927 ps
T861 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.114282938 Jul 16 05:28:58 PM PDT 24 Jul 16 05:29:03 PM PDT 24 83380933 ps
T862 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.128994583 Jul 16 05:32:35 PM PDT 24 Jul 16 05:32:37 PM PDT 24 35351764 ps
T863 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.854671864 Jul 16 05:28:47 PM PDT 24 Jul 16 05:28:49 PM PDT 24 254309986 ps
T864 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.163407630 Jul 16 05:29:07 PM PDT 24 Jul 16 05:29:09 PM PDT 24 668474198 ps
T865 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.592394297 Jul 16 05:29:19 PM PDT 24 Jul 16 05:29:20 PM PDT 24 155642597 ps
T866 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1154221422 Jul 16 05:29:12 PM PDT 24 Jul 16 05:29:14 PM PDT 24 189896698 ps
T867 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2571238446 Jul 16 05:36:24 PM PDT 24 Jul 16 05:36:25 PM PDT 24 27614605 ps
T868 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3655539942 Jul 16 05:33:54 PM PDT 24 Jul 16 05:33:55 PM PDT 24 191166699 ps
T869 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2608776879 Jul 16 05:28:59 PM PDT 24 Jul 16 05:29:03 PM PDT 24 64153537 ps
T870 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1875031795 Jul 16 05:28:47 PM PDT 24 Jul 16 05:28:49 PM PDT 24 154681999 ps
T871 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2958243901 Jul 16 05:36:08 PM PDT 24 Jul 16 05:36:10 PM PDT 24 288265173 ps
T872 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2469382405 Jul 16 05:29:05 PM PDT 24 Jul 16 05:29:07 PM PDT 24 106162191 ps
T873 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3337550450 Jul 16 05:36:53 PM PDT 24 Jul 16 05:36:56 PM PDT 24 141136281 ps
T874 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3882130212 Jul 16 05:29:18 PM PDT 24 Jul 16 05:29:19 PM PDT 24 32398087 ps
T875 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.408476794 Jul 16 05:28:42 PM PDT 24 Jul 16 05:28:44 PM PDT 24 96395435 ps
T876 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3615948884 Jul 16 05:28:54 PM PDT 24 Jul 16 05:29:02 PM PDT 24 507933541 ps
T877 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3106720492 Jul 16 05:36:24 PM PDT 24 Jul 16 05:36:26 PM PDT 24 127880819 ps
T878 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.633902180 Jul 16 05:28:49 PM PDT 24 Jul 16 05:28:52 PM PDT 24 121588881 ps
T879 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1061817501 Jul 16 05:29:20 PM PDT 24 Jul 16 05:29:22 PM PDT 24 224036296 ps
T880 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3029822186 Jul 16 05:32:41 PM PDT 24 Jul 16 05:32:43 PM PDT 24 194963892 ps
T881 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.221947003 Jul 16 05:28:47 PM PDT 24 Jul 16 05:28:49 PM PDT 24 113112515 ps
T882 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1549486503 Jul 16 05:36:52 PM PDT 24 Jul 16 05:36:54 PM PDT 24 58564168 ps
T883 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2115995140 Jul 16 05:28:58 PM PDT 24 Jul 16 05:29:04 PM PDT 24 76991811 ps
T884 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3217752844 Jul 16 05:28:58 PM PDT 24 Jul 16 05:29:04 PM PDT 24 180108129 ps
T885 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1995878652 Jul 16 05:32:35 PM PDT 24 Jul 16 05:32:37 PM PDT 24 65473966 ps
T886 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.833768588 Jul 16 05:31:20 PM PDT 24 Jul 16 05:31:22 PM PDT 24 316438356 ps
T887 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2193978773 Jul 16 05:28:54 PM PDT 24 Jul 16 05:29:02 PM PDT 24 54934008 ps
T888 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2191284456 Jul 16 05:28:56 PM PDT 24 Jul 16 05:29:03 PM PDT 24 326285698 ps
T889 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2216498684 Jul 16 05:29:07 PM PDT 24 Jul 16 05:29:08 PM PDT 24 193062922 ps
T890 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2798468478 Jul 16 05:28:58 PM PDT 24 Jul 16 05:29:04 PM PDT 24 35881983 ps
T891 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3554635384 Jul 16 05:35:51 PM PDT 24 Jul 16 05:35:52 PM PDT 24 50501534 ps
T892 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319656063 Jul 16 05:28:54 PM PDT 24 Jul 16 05:29:01 PM PDT 24 43929255 ps
T893 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1507168715 Jul 16 05:34:11 PM PDT 24 Jul 16 05:34:13 PM PDT 24 47917635 ps
T894 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.992511004 Jul 16 05:28:46 PM PDT 24 Jul 16 05:28:48 PM PDT 24 136025579 ps
T895 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2824693897 Jul 16 05:28:54 PM PDT 24 Jul 16 05:28:57 PM PDT 24 85556890 ps
T896 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.456159466 Jul 16 05:29:09 PM PDT 24 Jul 16 05:29:11 PM PDT 24 101731490 ps
T897 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1148337212 Jul 16 05:28:53 PM PDT 24 Jul 16 05:28:55 PM PDT 24 93629762 ps
T898 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2005077459 Jul 16 05:29:23 PM PDT 24 Jul 16 05:29:25 PM PDT 24 520963971 ps
T899 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574210605 Jul 16 05:32:30 PM PDT 24 Jul 16 05:32:32 PM PDT 24 43920385 ps
T900 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1614548767 Jul 16 05:36:52 PM PDT 24 Jul 16 05:36:54 PM PDT 24 97189369 ps
T901 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2942181634 Jul 16 05:28:55 PM PDT 24 Jul 16 05:29:03 PM PDT 24 76729261 ps
T902 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1691354664 Jul 16 05:29:12 PM PDT 24 Jul 16 05:29:14 PM PDT 24 949348853 ps
T903 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3506685037 Jul 16 05:32:29 PM PDT 24 Jul 16 05:32:32 PM PDT 24 149593667 ps
T904 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.28344554 Jul 16 05:28:43 PM PDT 24 Jul 16 05:28:45 PM PDT 24 41880393 ps
T905 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2828644813 Jul 16 05:31:18 PM PDT 24 Jul 16 05:31:21 PM PDT 24 53017733 ps
T906 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3766633420 Jul 16 05:29:11 PM PDT 24 Jul 16 05:29:13 PM PDT 24 32828779 ps
T907 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3989243984 Jul 16 05:28:57 PM PDT 24 Jul 16 05:29:03 PM PDT 24 146984394 ps
T908 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3748111639 Jul 16 05:29:22 PM PDT 24 Jul 16 05:29:24 PM PDT 24 209111954 ps
T909 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.117721361 Jul 16 05:28:47 PM PDT 24 Jul 16 05:28:50 PM PDT 24 47615745 ps
T910 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1901985609 Jul 16 05:36:34 PM PDT 24 Jul 16 05:36:36 PM PDT 24 73197166 ps
T911 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603709471 Jul 16 05:28:49 PM PDT 24 Jul 16 05:28:52 PM PDT 24 61398642 ps
T912 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2655451891 Jul 16 05:28:54 PM PDT 24 Jul 16 05:29:01 PM PDT 24 236922090 ps
T913 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975300405 Jul 16 05:28:58 PM PDT 24 Jul 16 05:29:04 PM PDT 24 210208261 ps
T914 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2677996422 Jul 16 05:28:55 PM PDT 24 Jul 16 05:29:03 PM PDT 24 185938602 ps
T915 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3430980777 Jul 16 05:28:54 PM PDT 24 Jul 16 05:28:56 PM PDT 24 230064217 ps
T916 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4092901598 Jul 16 05:28:47 PM PDT 24 Jul 16 05:28:49 PM PDT 24 85140547 ps
T917 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.898452693 Jul 16 05:35:51 PM PDT 24 Jul 16 05:35:52 PM PDT 24 58003068 ps
T918 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2850760324 Jul 16 05:34:03 PM PDT 24 Jul 16 05:34:05 PM PDT 24 45517574 ps
T919 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1327686009 Jul 16 05:32:24 PM PDT 24 Jul 16 05:32:27 PM PDT 24 139010037 ps
T920 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918278497 Jul 16 05:29:24 PM PDT 24 Jul 16 05:29:26 PM PDT 24 84662337 ps
T921 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.836910126 Jul 16 05:36:34 PM PDT 24 Jul 16 05:36:37 PM PDT 24 75310673 ps
T922 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.123786655 Jul 16 05:29:13 PM PDT 24 Jul 16 05:29:14 PM PDT 24 472112816 ps
T923 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3391766636 Jul 16 05:32:13 PM PDT 24 Jul 16 05:32:14 PM PDT 24 97292544 ps
T924 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.434758601 Jul 16 05:36:51 PM PDT 24 Jul 16 05:36:54 PM PDT 24 57598331 ps
T925 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4014617281 Jul 16 05:28:54 PM PDT 24 Jul 16 05:29:01 PM PDT 24 554946073 ps
T926 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2051241656 Jul 16 05:28:46 PM PDT 24 Jul 16 05:28:48 PM PDT 24 47813948 ps
T927 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2306410076 Jul 16 05:28:54 PM PDT 24 Jul 16 05:28:58 PM PDT 24 440580541 ps
T928 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3511617539 Jul 16 05:28:54 PM PDT 24 Jul 16 05:29:01 PM PDT 24 280051897 ps
T929 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3119642741 Jul 16 05:28:57 PM PDT 24 Jul 16 05:29:04 PM PDT 24 71027422 ps
T930 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1254645084 Jul 16 05:28:57 PM PDT 24 Jul 16 05:29:03 PM PDT 24 30153991 ps
T931 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2659216197 Jul 16 05:34:13 PM PDT 24 Jul 16 05:34:15 PM PDT 24 144556666 ps
T932 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3843183138 Jul 16 05:36:40 PM PDT 24 Jul 16 05:36:43 PM PDT 24 124414460 ps
T933 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4102578479 Jul 16 05:29:07 PM PDT 24 Jul 16 05:29:09 PM PDT 24 73691563 ps
T934 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1106366485 Jul 16 05:28:56 PM PDT 24 Jul 16 05:29:03 PM PDT 24 42054033 ps
T935 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3472752185 Jul 16 05:28:43 PM PDT 24 Jul 16 05:28:45 PM PDT 24 84652110 ps
T936 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2997437297 Jul 16 05:29:08 PM PDT 24 Jul 16 05:29:10 PM PDT 24 95874430 ps
T937 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1430012667 Jul 16 05:36:53 PM PDT 24 Jul 16 05:36:55 PM PDT 24 197846864 ps
T938 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3984516271 Jul 16 05:28:53 PM PDT 24 Jul 16 05:28:55 PM PDT 24 184597284 ps

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3479335554
Short name T27
Test name
Test status
Simulation time 64890788 ps
CPU time 0.97 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:43 PM PDT 24
Peak memory 197408 kb
Host smart-18b2ea03-8b20-47c0-9065-b2d932511774
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479335554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3479335554
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2805668884
Short name T32
Test name
Test status
Simulation time 15381803107 ps
CPU time 57.43 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 198608 kb
Host smart-321eb6b7-45be-400d-9674-2cf453ee80d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805668884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2805668884
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.880145152
Short name T61
Test name
Test status
Simulation time 173636351142 ps
CPU time 1095.75 seconds
Started Jul 16 04:55:23 PM PDT 24
Finished Jul 16 05:13:40 PM PDT 24
Peak memory 198884 kb
Host smart-341ee8f1-59c1-44da-90fb-2b74999450b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=880145152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.880145152
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.395418244
Short name T40
Test name
Test status
Simulation time 209634164 ps
CPU time 0.99 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:56 PM PDT 24
Peak memory 215224 kb
Host smart-f224a7e0-b9e5-45fe-a6fe-14dec73802a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395418244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.395418244
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1066821811
Short name T1
Test name
Test status
Simulation time 119925646 ps
CPU time 1.95 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 198620 kb
Host smart-6e495a12-847d-4760-b58e-64202ae5a9b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066821811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1066821811
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3799117119
Short name T22
Test name
Test status
Simulation time 5260814018 ps
CPU time 26.96 seconds
Started Jul 16 04:55:18 PM PDT 24
Finished Jul 16 04:55:46 PM PDT 24
Peak memory 197516 kb
Host smart-4007645e-f4be-46c5-96cb-8e887dd93027
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799117119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3799117119
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2988480690
Short name T48
Test name
Test status
Simulation time 86680980 ps
CPU time 1.25 seconds
Started Jul 16 04:53:58 PM PDT 24
Finished Jul 16 04:54:01 PM PDT 24
Peak memory 198492 kb
Host smart-8fcb7ae0-1da1-4a0c-adaa-0132fed88425
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988480690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2988480690
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3210736243
Short name T46
Test name
Test status
Simulation time 50509668 ps
CPU time 0.55 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 195152 kb
Host smart-8c3018c5-8afc-47cb-8ff4-75e330ead778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210736243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3210736243
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1517522932
Short name T87
Test name
Test status
Simulation time 15699741 ps
CPU time 0.73 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:45 PM PDT 24
Peak memory 196324 kb
Host smart-3575c127-52ad-4cd3-8c31-cbe162e6fe2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517522932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1517522932
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4211043989
Short name T104
Test name
Test status
Simulation time 14518310 ps
CPU time 0.67 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 195544 kb
Host smart-10338227-d8d3-4aa6-9433-df68f795f65f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211043989 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.4211043989
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1102827722
Short name T55
Test name
Test status
Simulation time 252466158 ps
CPU time 1.09 seconds
Started Jul 16 04:54:03 PM PDT 24
Finished Jul 16 04:54:05 PM PDT 24
Peak memory 198436 kb
Host smart-f4da9312-0b1a-41a6-aecc-4a1a0e90fa8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102827722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1102827722
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2476201330
Short name T51
Test name
Test status
Simulation time 45996323 ps
CPU time 0.85 seconds
Started Jul 16 04:54:10 PM PDT 24
Finished Jul 16 04:54:12 PM PDT 24
Peak memory 197992 kb
Host smart-65f1fd5a-8876-4156-bbb4-2f1e0725f6d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476201330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2476201330
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3455941367
Short name T119
Test name
Test status
Simulation time 28005202 ps
CPU time 1.28 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 196944 kb
Host smart-d926de55-fdad-4f97-94ec-ef3640378f09
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455941367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3455941367
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2986043948
Short name T96
Test name
Test status
Simulation time 81946246 ps
CPU time 2.84 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:06 PM PDT 24
Peak memory 196624 kb
Host smart-f3d67d8a-ed0d-4265-a9ca-06cd4cd563a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986043948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2986043948
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3128828175
Short name T739
Test name
Test status
Simulation time 17173746 ps
CPU time 0.64 seconds
Started Jul 16 04:53:50 PM PDT 24
Finished Jul 16 04:53:51 PM PDT 24
Peak memory 196020 kb
Host smart-8341716a-a2f1-459c-bef8-d04ccb12381b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128828175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3128828175
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2859911719
Short name T836
Test name
Test status
Simulation time 35032337 ps
CPU time 1.69 seconds
Started Jul 16 04:53:46 PM PDT 24
Finished Jul 16 04:53:49 PM PDT 24
Peak memory 198560 kb
Host smart-f3826e35-d11c-4142-961a-d2b7e23e94c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859911719 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2859911719
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2874778533
Short name T110
Test name
Test status
Simulation time 26633535 ps
CPU time 0.6 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 195252 kb
Host smart-85ae686f-3a3c-4d07-a1ce-aeca22aaf2d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874778533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2874778533
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2882524900
Short name T829
Test name
Test status
Simulation time 15048356 ps
CPU time 0.61 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:45 PM PDT 24
Peak memory 194236 kb
Host smart-80465416-3c30-42b4-8f6d-dcfa935e6185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882524900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2882524900
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2535077413
Short name T827
Test name
Test status
Simulation time 170702041 ps
CPU time 2.56 seconds
Started Jul 16 04:53:46 PM PDT 24
Finished Jul 16 04:53:50 PM PDT 24
Peak memory 198512 kb
Host smart-cede364a-bf04-4bd6-a35d-d585bfd523da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535077413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2535077413
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.84119324
Short name T49
Test name
Test status
Simulation time 84862040 ps
CPU time 0.92 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 197716 kb
Host smart-195098be-fd08-47da-bb9f-cf5f6cd86202
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84119324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_tl_intg_err.84119324
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.11413948
Short name T744
Test name
Test status
Simulation time 25582442 ps
CPU time 0.77 seconds
Started Jul 16 04:54:04 PM PDT 24
Finished Jul 16 04:54:06 PM PDT 24
Peak memory 196824 kb
Host smart-72c6fa53-4cdc-405a-96d6-01b96426aa5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
gpio_csr_aliasing.11413948
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2060942749
Short name T86
Test name
Test status
Simulation time 340727132 ps
CPU time 3.43 seconds
Started Jul 16 04:53:41 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 198508 kb
Host smart-3ed0e922-251f-4be4-a52b-f155cbbf78b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060942749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2060942749
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4050846240
Short name T94
Test name
Test status
Simulation time 16435419 ps
CPU time 0.72 seconds
Started Jul 16 04:53:46 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 195308 kb
Host smart-e2e28262-93bb-4f73-8483-ebeb859ce320
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050846240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4050846240
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1116392149
Short name T737
Test name
Test status
Simulation time 105789855 ps
CPU time 0.86 seconds
Started Jul 16 04:53:43 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 198424 kb
Host smart-0d31c2b7-5673-4336-b301-d20e222e2bda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116392149 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1116392149
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3533754736
Short name T92
Test name
Test status
Simulation time 17170899 ps
CPU time 0.61 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 195376 kb
Host smart-341f3f03-94d0-407b-9470-d7f5ca6458a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533754736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3533754736
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2072791826
Short name T797
Test name
Test status
Simulation time 28979047 ps
CPU time 0.61 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:04 PM PDT 24
Peak memory 194108 kb
Host smart-0515ccd6-dca5-42cf-b376-cd087716c980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072791826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2072791826
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4089945596
Short name T106
Test name
Test status
Simulation time 65920290 ps
CPU time 0.7 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 195348 kb
Host smart-6e07ffc1-70a8-45af-8be5-ffcfa8e11850
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089945596 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.4089945596
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.274269532
Short name T759
Test name
Test status
Simulation time 53201327 ps
CPU time 1.14 seconds
Started Jul 16 04:53:51 PM PDT 24
Finished Jul 16 04:53:58 PM PDT 24
Peak memory 198528 kb
Host smart-650f6464-e6b7-43b9-b953-8864b59dcef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274269532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.274269532
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.543578499
Short name T38
Test name
Test status
Simulation time 116297773 ps
CPU time 1.46 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 198536 kb
Host smart-20f2028d-687e-4f19-889c-1ae40193e18b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543578499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.543578499
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.925792450
Short name T757
Test name
Test status
Simulation time 74063106 ps
CPU time 0.97 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 198476 kb
Host smart-2b891f7f-c181-4a32-9833-01d3a3f72419
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925792450 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.925792450
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.475634542
Short name T99
Test name
Test status
Simulation time 11615934 ps
CPU time 0.64 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 195328 kb
Host smart-7593089f-0919-47bf-8c0f-2ab1abf634fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475634542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.475634542
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.734789166
Short name T817
Test name
Test status
Simulation time 13362270 ps
CPU time 0.66 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:58 PM PDT 24
Peak memory 194884 kb
Host smart-0d30bf62-af05-4525-be6d-20eb6be8aca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734789166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.734789166
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1901417848
Short name T811
Test name
Test status
Simulation time 60748977 ps
CPU time 0.75 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 196184 kb
Host smart-db83876a-0b24-4a90-a0a4-b0ddc84be348
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901417848 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1901417848
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2234913141
Short name T824
Test name
Test status
Simulation time 1038728656 ps
CPU time 2.47 seconds
Started Jul 16 04:53:58 PM PDT 24
Finished Jul 16 04:54:03 PM PDT 24
Peak memory 198528 kb
Host smart-105d74bd-b68c-41b3-8619-92c065db2830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234913141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2234913141
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1595720977
Short name T730
Test name
Test status
Simulation time 23280319 ps
CPU time 0.92 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 198384 kb
Host smart-b05d7bfe-bdf6-4186-87ca-c65e2ac7a366
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595720977 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1595720977
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.959212983
Short name T747
Test name
Test status
Simulation time 26965047 ps
CPU time 0.63 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 195104 kb
Host smart-e8215e15-2d48-4aa0-9343-6e91ce34885c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959212983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.959212983
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1986026671
Short name T787
Test name
Test status
Simulation time 34733959 ps
CPU time 0.58 seconds
Started Jul 16 04:53:53 PM PDT 24
Finished Jul 16 04:53:54 PM PDT 24
Peak memory 194228 kb
Host smart-0e0c4690-ce13-4e4c-8a5b-b72eccb9eff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986026671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1986026671
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.446127328
Short name T85
Test name
Test status
Simulation time 52752302 ps
CPU time 0.74 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:57 PM PDT 24
Peak memory 195484 kb
Host smart-47c268b2-39ea-45b9-a0b2-b5bae44da170
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446127328 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.446127328
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.253972691
Short name T823
Test name
Test status
Simulation time 134163330 ps
CPU time 1.52 seconds
Started Jul 16 04:53:58 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 198620 kb
Host smart-222dfe82-7dfa-4f79-9c1a-aa5b3d0ffd66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253972691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.253972691
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2120931367
Short name T39
Test name
Test status
Simulation time 138106555 ps
CPU time 0.91 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:53:59 PM PDT 24
Peak memory 198208 kb
Host smart-93d03f25-bf9a-494f-a648-36133473c91c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120931367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2120931367
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.730495379
Short name T818
Test name
Test status
Simulation time 83302909 ps
CPU time 1.1 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:57 PM PDT 24
Peak memory 198340 kb
Host smart-08bb0fb5-f1c3-4717-adb0-80bd6c36b64f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730495379 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.730495379
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2684087415
Short name T775
Test name
Test status
Simulation time 11643215 ps
CPU time 0.62 seconds
Started Jul 16 04:54:10 PM PDT 24
Finished Jul 16 04:54:11 PM PDT 24
Peak memory 194336 kb
Host smart-2a354512-ee0f-4512-ab79-4c158c7dc7cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684087415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2684087415
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3863387964
Short name T750
Test name
Test status
Simulation time 37329627 ps
CPU time 0.6 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:53:59 PM PDT 24
Peak memory 194156 kb
Host smart-22c79820-53f7-402b-ad20-8f9222edfcb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863387964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3863387964
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.888649025
Short name T108
Test name
Test status
Simulation time 33806750 ps
CPU time 0.62 seconds
Started Jul 16 04:53:54 PM PDT 24
Finished Jul 16 04:53:55 PM PDT 24
Peak memory 195752 kb
Host smart-1589c395-cb07-437a-8061-04a3e768c1e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888649025 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.888649025
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1630138948
Short name T784
Test name
Test status
Simulation time 224287634 ps
CPU time 2.83 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 198524 kb
Host smart-ea57e285-063d-4c86-8756-d7beb785a683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630138948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1630138948
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3837265437
Short name T37
Test name
Test status
Simulation time 217342646 ps
CPU time 1.38 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:58 PM PDT 24
Peak memory 198484 kb
Host smart-2682d447-8bc3-4079-a852-5a73887f9752
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837265437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3837265437
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2621759208
Short name T830
Test name
Test status
Simulation time 92389926 ps
CPU time 1.29 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 198536 kb
Host smart-f5cdeba2-1a3a-49aa-b813-d919a271ef3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621759208 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2621759208
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4203119164
Short name T90
Test name
Test status
Simulation time 60236354 ps
CPU time 0.65 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 195396 kb
Host smart-55efa0f2-8f8e-4ff1-9898-1aee7761b472
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203119164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4203119164
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.331236817
Short name T822
Test name
Test status
Simulation time 15633409 ps
CPU time 0.59 seconds
Started Jul 16 04:54:04 PM PDT 24
Finished Jul 16 04:54:05 PM PDT 24
Peak memory 194836 kb
Host smart-3d92acb7-aef7-4b5c-8e44-ff873c425421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331236817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.331236817
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3842734392
Short name T799
Test name
Test status
Simulation time 31307036 ps
CPU time 0.66 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:57 PM PDT 24
Peak memory 195700 kb
Host smart-7be7a70e-0b5f-4ed7-88aa-f6500ba2be80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842734392 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3842734392
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2588138419
Short name T803
Test name
Test status
Simulation time 184239658 ps
CPU time 2.47 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 198588 kb
Host smart-2d20faf7-e15a-4d5f-a05e-9c4497fe888e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588138419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2588138419
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2676187780
Short name T835
Test name
Test status
Simulation time 84104411 ps
CPU time 0.85 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 198336 kb
Host smart-37dfe7bd-89fe-43a7-817a-ea9e3298cbb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676187780 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2676187780
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.559740166
Short name T100
Test name
Test status
Simulation time 45993389 ps
CPU time 0.66 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 195364 kb
Host smart-4d6a8f7f-4f91-4ba1-b467-370b93e0f893
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559740166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.559740166
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3256490457
Short name T719
Test name
Test status
Simulation time 24907027 ps
CPU time 0.64 seconds
Started Jul 16 04:53:58 PM PDT 24
Finished Jul 16 04:54:01 PM PDT 24
Peak memory 194140 kb
Host smart-63f41837-682c-462e-8ea7-8b418836bb3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256490457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3256490457
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.130347851
Short name T105
Test name
Test status
Simulation time 16191431 ps
CPU time 0.8 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:04 PM PDT 24
Peak memory 197120 kb
Host smart-e49b4efc-1d1f-4299-9c4c-4f2ac4b908f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130347851 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.130347851
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2641705711
Short name T746
Test name
Test status
Simulation time 270539220 ps
CPU time 1.75 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:05 PM PDT 24
Peak memory 198392 kb
Host smart-ad31599b-b8da-4aac-ab3d-3977dec93405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641705711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2641705711
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3648982171
Short name T758
Test name
Test status
Simulation time 43496374 ps
CPU time 1.2 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 198524 kb
Host smart-b98713b8-3bdd-4929-93b0-99ca5efd3562
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648982171 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3648982171
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1461303976
Short name T97
Test name
Test status
Simulation time 67987598 ps
CPU time 0.61 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:57 PM PDT 24
Peak memory 195312 kb
Host smart-95e028fb-6073-48e8-8d80-eeba31196ac2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461303976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1461303976
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4211911808
Short name T785
Test name
Test status
Simulation time 49408774 ps
CPU time 0.62 seconds
Started Jul 16 04:53:58 PM PDT 24
Finished Jul 16 04:54:01 PM PDT 24
Peak memory 194100 kb
Host smart-e61c225c-b4ce-40fe-988c-e7778ec80201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211911808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4211911808
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2405499569
Short name T769
Test name
Test status
Simulation time 41735577 ps
CPU time 0.65 seconds
Started Jul 16 04:54:08 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 195176 kb
Host smart-0f26dcdf-44a5-47f1-80f1-9bc76ee42b14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405499569 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2405499569
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.524229311
Short name T773
Test name
Test status
Simulation time 84183617 ps
CPU time 1.81 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:03 PM PDT 24
Peak memory 198604 kb
Host smart-df16c5fb-af37-4ed0-950b-38b16ffd0540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524229311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.524229311
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2992176813
Short name T794
Test name
Test status
Simulation time 173587347 ps
CPU time 1.16 seconds
Started Jul 16 04:54:06 PM PDT 24
Finished Jul 16 04:54:08 PM PDT 24
Peak memory 198548 kb
Host smart-d88c35aa-59ed-4a68-aadb-e4de54f9e689
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992176813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2992176813
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2958462045
Short name T812
Test name
Test status
Simulation time 42317961 ps
CPU time 1.17 seconds
Started Jul 16 04:54:10 PM PDT 24
Finished Jul 16 04:54:11 PM PDT 24
Peak memory 198516 kb
Host smart-efd3195b-d9b9-4e67-944e-1af15c03556c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958462045 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2958462045
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4238140126
Short name T809
Test name
Test status
Simulation time 24167792 ps
CPU time 0.6 seconds
Started Jul 16 04:54:08 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 194984 kb
Host smart-363207b7-0bf8-4da2-8403-39e2bc5e308a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238140126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4238140126
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.4034681358
Short name T745
Test name
Test status
Simulation time 30052453 ps
CPU time 0.64 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 194828 kb
Host smart-2af81934-a4c9-4e46-9855-f420d3cdf84a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034681358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.4034681358
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1026340771
Short name T771
Test name
Test status
Simulation time 77778385 ps
CPU time 0.63 seconds
Started Jul 16 04:53:55 PM PDT 24
Finished Jul 16 04:53:56 PM PDT 24
Peak memory 195440 kb
Host smart-847f62b6-6555-4f98-b342-18c42c06b39d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026340771 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1026340771
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3492055604
Short name T720
Test name
Test status
Simulation time 331253652 ps
CPU time 1.58 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:03 PM PDT 24
Peak memory 198416 kb
Host smart-203c12c3-fbd2-4f0f-9042-f04fa00d38d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492055604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3492055604
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.636448505
Short name T53
Test name
Test status
Simulation time 350873498 ps
CPU time 1.67 seconds
Started Jul 16 04:54:00 PM PDT 24
Finished Jul 16 04:54:04 PM PDT 24
Peak memory 198628 kb
Host smart-cd297def-5ba2-4fef-b2ee-f9a46ff8e9f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636448505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.636448505
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3328735311
Short name T734
Test name
Test status
Simulation time 70670379 ps
CPU time 1.21 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 198568 kb
Host smart-91f1723c-7f95-40e4-9bff-963a391a1a31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328735311 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3328735311
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3118031631
Short name T89
Test name
Test status
Simulation time 25040998 ps
CPU time 0.63 seconds
Started Jul 16 04:53:58 PM PDT 24
Finished Jul 16 04:54:01 PM PDT 24
Peak memory 194584 kb
Host smart-c4734c2d-e403-4727-8814-73c55c22a5ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118031631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3118031631
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1011224443
Short name T723
Test name
Test status
Simulation time 14436493 ps
CPU time 0.66 seconds
Started Jul 16 04:54:00 PM PDT 24
Finished Jul 16 04:54:03 PM PDT 24
Peak memory 194240 kb
Host smart-a9175558-39f7-478f-a09c-84e37fd7aa91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011224443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1011224443
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3400046735
Short name T810
Test name
Test status
Simulation time 67341696 ps
CPU time 0.64 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 195056 kb
Host smart-08493d85-e0d7-42da-b4f9-61f4a99ab503
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400046735 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3400046735
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3033188519
Short name T828
Test name
Test status
Simulation time 2500248392 ps
CPU time 3.14 seconds
Started Jul 16 04:54:06 PM PDT 24
Finished Jul 16 04:54:10 PM PDT 24
Peak memory 198568 kb
Host smart-4e97fbba-1981-4d2f-8fbb-d154f225f1f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033188519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3033188519
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3381704783
Short name T804
Test name
Test status
Simulation time 113431872 ps
CPU time 1.46 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:03 PM PDT 24
Peak memory 198440 kb
Host smart-5e7877aa-b82d-429a-a126-39a086ca9475
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381704783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3381704783
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2864007095
Short name T722
Test name
Test status
Simulation time 386874747 ps
CPU time 1.43 seconds
Started Jul 16 04:54:04 PM PDT 24
Finished Jul 16 04:54:06 PM PDT 24
Peak memory 198624 kb
Host smart-80b472fc-cd10-4921-88ed-0a43fc5090d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864007095 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2864007095
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3683673675
Short name T808
Test name
Test status
Simulation time 14772154 ps
CPU time 0.69 seconds
Started Jul 16 04:53:58 PM PDT 24
Finished Jul 16 04:54:01 PM PDT 24
Peak memory 195444 kb
Host smart-c98c3657-5468-49de-8f99-3a28ed4245e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683673675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3683673675
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2505693121
Short name T740
Test name
Test status
Simulation time 59015674 ps
CPU time 0.61 seconds
Started Jul 16 04:54:06 PM PDT 24
Finished Jul 16 04:54:08 PM PDT 24
Peak memory 193816 kb
Host smart-747be563-ecde-4f6a-9015-ab6b7b5eadea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505693121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2505693121
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4159402282
Short name T103
Test name
Test status
Simulation time 48951565 ps
CPU time 0.66 seconds
Started Jul 16 04:54:00 PM PDT 24
Finished Jul 16 04:54:03 PM PDT 24
Peak memory 195572 kb
Host smart-833f2fb8-cb42-498f-9944-a168a27f70cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159402282 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4159402282
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2530583762
Short name T741
Test name
Test status
Simulation time 53185768 ps
CPU time 1.48 seconds
Started Jul 16 04:54:06 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 198240 kb
Host smart-1b83ae9e-f869-4d81-bb94-a3eb1374ce39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530583762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2530583762
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2662528577
Short name T47
Test name
Test status
Simulation time 220822893 ps
CPU time 1.52 seconds
Started Jul 16 04:54:06 PM PDT 24
Finished Jul 16 04:54:08 PM PDT 24
Peak memory 198492 kb
Host smart-ffa14687-56b9-446f-a910-00d371dff189
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662528577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2662528577
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4199696002
Short name T749
Test name
Test status
Simulation time 31879188 ps
CPU time 1.28 seconds
Started Jul 16 04:53:55 PM PDT 24
Finished Jul 16 04:53:57 PM PDT 24
Peak memory 198540 kb
Host smart-65f5de52-e696-4a5a-b303-e82cca3b4df5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199696002 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.4199696002
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1016928388
Short name T781
Test name
Test status
Simulation time 36674809 ps
CPU time 0.59 seconds
Started Jul 16 04:53:55 PM PDT 24
Finished Jul 16 04:53:56 PM PDT 24
Peak memory 195868 kb
Host smart-ed862cd2-9521-4190-8466-51e228ff40fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016928388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1016928388
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.603379394
Short name T760
Test name
Test status
Simulation time 30130941 ps
CPU time 0.6 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 194216 kb
Host smart-df099019-cb9b-4d95-bafd-96e882c48429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603379394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.603379394
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2551992635
Short name T776
Test name
Test status
Simulation time 66596088 ps
CPU time 0.86 seconds
Started Jul 16 04:54:05 PM PDT 24
Finished Jul 16 04:54:07 PM PDT 24
Peak memory 197352 kb
Host smart-54395646-045c-432b-ba20-a3132fd1dead
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551992635 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2551992635
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3393714669
Short name T718
Test name
Test status
Simulation time 56094158 ps
CPU time 1.41 seconds
Started Jul 16 04:54:20 PM PDT 24
Finished Jul 16 04:54:22 PM PDT 24
Peak memory 198488 kb
Host smart-713d86dd-4383-48dc-b17b-3446bf31b1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393714669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3393714669
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3733342218
Short name T754
Test name
Test status
Simulation time 1822763805 ps
CPU time 1.38 seconds
Started Jul 16 04:54:31 PM PDT 24
Finished Jul 16 04:54:33 PM PDT 24
Peak memory 198516 kb
Host smart-6a720fe8-f052-420d-8436-d4fc193ceec8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733342218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3733342218
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1441140363
Short name T88
Test name
Test status
Simulation time 21064068 ps
CPU time 0.65 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 195216 kb
Host smart-fc5c6fd3-da5c-4560-9c41-11382cc9df55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441140363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1441140363
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4132928788
Short name T772
Test name
Test status
Simulation time 340192023 ps
CPU time 3.38 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:50 PM PDT 24
Peak memory 198488 kb
Host smart-3568233b-e292-498a-aeeb-2de07f93b3bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132928788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4132928788
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4158885399
Short name T820
Test name
Test status
Simulation time 17740284 ps
CPU time 0.66 seconds
Started Jul 16 04:53:46 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 195768 kb
Host smart-cb668ddb-a7ce-4b35-b5e9-69e3e177421f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158885399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.4158885399
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1784734966
Short name T735
Test name
Test status
Simulation time 108903760 ps
CPU time 1.39 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:10 PM PDT 24
Peak memory 198404 kb
Host smart-7ed0a8bd-600b-4eec-a9e3-06d42aea628d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784734966 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1784734966
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1630911013
Short name T833
Test name
Test status
Simulation time 13956428 ps
CPU time 0.63 seconds
Started Jul 16 04:53:47 PM PDT 24
Finished Jul 16 04:53:49 PM PDT 24
Peak memory 195436 kb
Host smart-14b3b799-d3cc-446c-852a-de1951a0b985
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630911013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1630911013
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.45928401
Short name T777
Test name
Test status
Simulation time 55062742 ps
CPU time 0.64 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 193976 kb
Host smart-eea41251-63f0-48fc-870d-9b5c0e2045d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45928401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.45928401
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.595369472
Short name T101
Test name
Test status
Simulation time 48484305 ps
CPU time 0.88 seconds
Started Jul 16 04:53:47 PM PDT 24
Finished Jul 16 04:53:49 PM PDT 24
Peak memory 196892 kb
Host smart-13924746-2b90-43ad-92a0-461cc4e1b703
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595369472 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.595369472
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3190269088
Short name T819
Test name
Test status
Simulation time 261680074 ps
CPU time 2.78 seconds
Started Jul 16 04:53:43 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 198504 kb
Host smart-78e589c9-25ff-497c-b578-583feaf96095
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190269088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3190269088
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1257266298
Short name T54
Test name
Test status
Simulation time 410612761 ps
CPU time 1.5 seconds
Started Jul 16 04:53:43 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 198528 kb
Host smart-045cba95-be1d-4d21-89df-a436509d70fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257266298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1257266298
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3703681330
Short name T789
Test name
Test status
Simulation time 17474524 ps
CPU time 0.65 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:13 PM PDT 24
Peak memory 194204 kb
Host smart-39e02606-6561-41d7-b040-c9b9136c254d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703681330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3703681330
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3611459356
Short name T792
Test name
Test status
Simulation time 13198554 ps
CPU time 0.58 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 194072 kb
Host smart-31775ceb-911b-43aa-9687-3235260e38d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611459356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3611459356
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3376404661
Short name T752
Test name
Test status
Simulation time 66425166 ps
CPU time 0.59 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:14 PM PDT 24
Peak memory 194164 kb
Host smart-76abb75b-32bb-4812-9dab-f77b3de5e2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376404661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3376404661
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2546851241
Short name T813
Test name
Test status
Simulation time 25378183 ps
CPU time 0.58 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:15 PM PDT 24
Peak memory 194824 kb
Host smart-8facd20d-d47c-40c5-85fb-09259cfbebda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546851241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2546851241
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.996513418
Short name T766
Test name
Test status
Simulation time 64521681 ps
CPU time 0.66 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:15 PM PDT 24
Peak memory 194180 kb
Host smart-a355f578-3d71-4fc7-9a15-fe81cdfa0283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996513418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.996513418
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2814083374
Short name T780
Test name
Test status
Simulation time 38871775 ps
CPU time 0.58 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 193996 kb
Host smart-27d55dd2-eebd-4a20-8dab-40460220f08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814083374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2814083374
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.4196686929
Short name T814
Test name
Test status
Simulation time 48812402 ps
CPU time 0.64 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:17 PM PDT 24
Peak memory 194156 kb
Host smart-c463dfcc-32c7-4ecf-9e0a-3c84d2296a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196686929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.4196686929
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1859508310
Short name T774
Test name
Test status
Simulation time 22886980 ps
CPU time 0.61 seconds
Started Jul 16 04:54:22 PM PDT 24
Finished Jul 16 04:54:23 PM PDT 24
Peak memory 194900 kb
Host smart-0a649344-0c09-41d1-9867-4ff8a0a3a858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859508310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1859508310
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.911992835
Short name T798
Test name
Test status
Simulation time 17603152 ps
CPU time 0.6 seconds
Started Jul 16 04:54:11 PM PDT 24
Finished Jul 16 04:54:12 PM PDT 24
Peak memory 194076 kb
Host smart-bde7ce41-a129-4d4c-b995-78e9576f6e03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911992835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.911992835
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2782791687
Short name T786
Test name
Test status
Simulation time 32495186 ps
CPU time 0.61 seconds
Started Jul 16 04:54:09 PM PDT 24
Finished Jul 16 04:54:11 PM PDT 24
Peak memory 194804 kb
Host smart-b6fcc0b3-8c1f-4cda-95ee-9a2548b0d005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782791687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2782791687
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1209062744
Short name T801
Test name
Test status
Simulation time 70739297 ps
CPU time 0.67 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 194988 kb
Host smart-8ff8de25-cf66-4aab-abf4-f762c773f7ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209062744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1209062744
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2528454348
Short name T111
Test name
Test status
Simulation time 252781853 ps
CPU time 3.31 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:49 PM PDT 24
Peak memory 198424 kb
Host smart-501eeb55-ad2a-4ff8-ab48-3bf85f8580fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528454348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2528454348
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.418582896
Short name T83
Test name
Test status
Simulation time 52894827 ps
CPU time 0.67 seconds
Started Jul 16 04:53:47 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 196160 kb
Host smart-77e739c7-72fb-424a-a8bb-35c5a5c49888
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418582896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.418582896
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3767521916
Short name T721
Test name
Test status
Simulation time 104980281 ps
CPU time 1.01 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:04 PM PDT 24
Peak memory 198240 kb
Host smart-19459fe1-e36b-4e6a-880d-278dd8d5dfc6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767521916 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3767521916
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.492736601
Short name T93
Test name
Test status
Simulation time 37771971 ps
CPU time 0.59 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:04 PM PDT 24
Peak memory 193492 kb
Host smart-f68cf511-1e4b-4581-a0db-23041ac128ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492736601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.492736601
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1791587148
Short name T767
Test name
Test status
Simulation time 13754490 ps
CPU time 0.59 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 194188 kb
Host smart-a0e39fb4-41d6-4b39-b80b-d5c6f47cc11b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791587148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1791587148
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1392405448
Short name T788
Test name
Test status
Simulation time 13266514 ps
CPU time 0.68 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 195196 kb
Host smart-622f0bc3-d25a-443a-9021-4e6122935445
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392405448 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1392405448
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.520914778
Short name T782
Test name
Test status
Simulation time 23239801 ps
CPU time 1.2 seconds
Started Jul 16 04:53:47 PM PDT 24
Finished Jul 16 04:53:49 PM PDT 24
Peak memory 198564 kb
Host smart-b8332d30-8099-4e06-926c-3421b37268f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520914778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.520914778
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3211138257
Short name T765
Test name
Test status
Simulation time 48645139 ps
CPU time 0.9 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 198200 kb
Host smart-2938aa5d-e944-4e70-990c-2278e9d40bd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211138257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3211138257
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.922412380
Short name T755
Test name
Test status
Simulation time 21853081 ps
CPU time 0.63 seconds
Started Jul 16 04:54:11 PM PDT 24
Finished Jul 16 04:54:12 PM PDT 24
Peak memory 194756 kb
Host smart-1f2dd0ac-5bec-46fa-99f9-736b77376fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922412380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.922412380
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3993837004
Short name T790
Test name
Test status
Simulation time 67139696 ps
CPU time 0.59 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 193960 kb
Host smart-9c8e68c6-1d1e-4255-9b53-68d1cbf660c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993837004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3993837004
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3136569275
Short name T733
Test name
Test status
Simulation time 17118441 ps
CPU time 0.6 seconds
Started Jul 16 04:54:21 PM PDT 24
Finished Jul 16 04:54:22 PM PDT 24
Peak memory 194984 kb
Host smart-716f916a-7e80-4e84-ae06-0d76f1dd71d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136569275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3136569275
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3757119568
Short name T783
Test name
Test status
Simulation time 30767207 ps
CPU time 0.64 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:13 PM PDT 24
Peak memory 194860 kb
Host smart-80725be8-9424-4e5b-914e-537de27fc892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757119568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3757119568
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2204560404
Short name T716
Test name
Test status
Simulation time 80396557 ps
CPU time 0.62 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 194968 kb
Host smart-1b1e05ad-b4a9-4100-b89b-6ec22473a911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204560404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2204560404
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2504131457
Short name T762
Test name
Test status
Simulation time 46616088 ps
CPU time 0.59 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:13 PM PDT 24
Peak memory 194096 kb
Host smart-056ca4af-1864-46e8-b775-92fefc76a798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504131457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2504131457
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3559728145
Short name T778
Test name
Test status
Simulation time 22373642 ps
CPU time 0.64 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:17 PM PDT 24
Peak memory 194880 kb
Host smart-d6f89f10-e62e-4a0b-98da-16a32bbd5574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559728145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3559728145
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1041365086
Short name T770
Test name
Test status
Simulation time 19493834 ps
CPU time 0.64 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:13 PM PDT 24
Peak memory 194196 kb
Host smart-205131fa-3ac7-4465-84e3-dc4a9fad7556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041365086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1041365086
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1463353568
Short name T763
Test name
Test status
Simulation time 31203461 ps
CPU time 0.59 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:15 PM PDT 24
Peak memory 194116 kb
Host smart-cec5563a-d8f4-4c23-b6ea-d1aaee5bd0dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463353568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1463353568
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.4253552203
Short name T748
Test name
Test status
Simulation time 112973974 ps
CPU time 0.58 seconds
Started Jul 16 04:54:24 PM PDT 24
Finished Jul 16 04:54:25 PM PDT 24
Peak memory 194240 kb
Host smart-db5c9f31-804d-441c-b8e8-d25b8405ebe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253552203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.4253552203
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1846421759
Short name T91
Test name
Test status
Simulation time 16215598 ps
CPU time 0.74 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 196776 kb
Host smart-9ad466c5-e599-41a8-817c-0c7c8c4c20a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846421759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1846421759
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1568483895
Short name T82
Test name
Test status
Simulation time 62961341 ps
CPU time 2.22 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 198468 kb
Host smart-7a136375-a679-4b51-9e62-d93db37fc851
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568483895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1568483895
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.509489420
Short name T756
Test name
Test status
Simulation time 118771792 ps
CPU time 0.64 seconds
Started Jul 16 04:53:43 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 195160 kb
Host smart-dd20ef86-e9c2-40f9-bae2-f85edfdb3d96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509489420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.509489420
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3434236436
Short name T736
Test name
Test status
Simulation time 38747064 ps
CPU time 0.99 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 198404 kb
Host smart-f161f3f6-6c4a-418b-877f-07f222569394
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434236436 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3434236436
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3431760236
Short name T95
Test name
Test status
Simulation time 32326851 ps
CPU time 0.58 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:09 PM PDT 24
Peak memory 193712 kb
Host smart-ed25f748-b32d-4ac2-ac50-a50474372470
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431760236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3431760236
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1158037840
Short name T732
Test name
Test status
Simulation time 55490712 ps
CPU time 0.65 seconds
Started Jul 16 04:53:51 PM PDT 24
Finished Jul 16 04:53:52 PM PDT 24
Peak memory 194196 kb
Host smart-9a0170b4-a1be-4588-81d6-56a2bf65b4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158037840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1158037840
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2561564967
Short name T816
Test name
Test status
Simulation time 51571188 ps
CPU time 0.75 seconds
Started Jul 16 04:53:40 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 196184 kb
Host smart-211a6624-c8b6-4182-a247-5ddd0120153f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561564967 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2561564967
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1836835614
Short name T727
Test name
Test status
Simulation time 31947767 ps
CPU time 1.65 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 198476 kb
Host smart-319c342f-39f5-4dbc-9aaa-a9df0d37d3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836835614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1836835614
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.830858045
Short name T815
Test name
Test status
Simulation time 49588961 ps
CPU time 0.82 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 197772 kb
Host smart-7f6e0268-4d22-4992-bd64-a24505f6cc7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830858045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.830858045
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3138577701
Short name T832
Test name
Test status
Simulation time 44812117 ps
CPU time 0.59 seconds
Started Jul 16 04:54:24 PM PDT 24
Finished Jul 16 04:54:25 PM PDT 24
Peak memory 194232 kb
Host smart-0906d792-2a63-4e19-b371-3cea3703edbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138577701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3138577701
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1314097619
Short name T726
Test name
Test status
Simulation time 50646596 ps
CPU time 0.62 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 194316 kb
Host smart-599257fb-902c-40ba-83a7-a97513c78024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314097619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1314097619
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1591838675
Short name T751
Test name
Test status
Simulation time 15096920 ps
CPU time 0.6 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 194860 kb
Host smart-8102972d-6cd6-464c-b02d-b4221921bdb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591838675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1591838675
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2879905600
Short name T724
Test name
Test status
Simulation time 14459173 ps
CPU time 0.64 seconds
Started Jul 16 04:54:17 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 194292 kb
Host smart-87c7b034-19d3-4f55-95c1-f28e0fe47e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879905600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2879905600
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2218883349
Short name T731
Test name
Test status
Simulation time 31625705 ps
CPU time 0.63 seconds
Started Jul 16 04:54:27 PM PDT 24
Finished Jul 16 04:54:29 PM PDT 24
Peak memory 194160 kb
Host smart-c9aa73ab-abc5-44fa-a510-3bf0546d481f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218883349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2218883349
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.649545472
Short name T795
Test name
Test status
Simulation time 49389407 ps
CPU time 0.6 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:15 PM PDT 24
Peak memory 194192 kb
Host smart-3601a970-0db4-4154-913e-bc0b405e003c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649545472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.649545472
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2406059106
Short name T753
Test name
Test status
Simulation time 14657865 ps
CPU time 0.63 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:13 PM PDT 24
Peak memory 194156 kb
Host smart-bac3b747-72eb-47f7-91f2-44ad51cfb7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406059106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2406059106
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.78188365
Short name T743
Test name
Test status
Simulation time 25257677 ps
CPU time 0.64 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:15 PM PDT 24
Peak memory 194812 kb
Host smart-d2576be8-b9e3-4648-8ccf-6dea7223bee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78188365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.78188365
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3803148009
Short name T729
Test name
Test status
Simulation time 119833554 ps
CPU time 0.68 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:13 PM PDT 24
Peak memory 194308 kb
Host smart-605cacb8-3893-4b8f-9319-644865a0b716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803148009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3803148009
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.745476915
Short name T806
Test name
Test status
Simulation time 35599990 ps
CPU time 0.59 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:13 PM PDT 24
Peak memory 194296 kb
Host smart-887c2aa8-d4aa-4e0f-822c-2f004e648a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745476915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.745476915
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1508497514
Short name T791
Test name
Test status
Simulation time 50538915 ps
CPU time 0.76 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 198328 kb
Host smart-95834d1f-8242-4fd4-af24-ddc3da88af9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508497514 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1508497514
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.554322351
Short name T768
Test name
Test status
Simulation time 31700724 ps
CPU time 0.61 seconds
Started Jul 16 04:53:50 PM PDT 24
Finished Jul 16 04:53:52 PM PDT 24
Peak memory 195852 kb
Host smart-9351ff05-9f68-41e0-915f-a18870d2fe40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554322351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.554322351
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3972286825
Short name T725
Test name
Test status
Simulation time 19356649 ps
CPU time 0.65 seconds
Started Jul 16 04:53:44 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 194940 kb
Host smart-e1584a43-3891-4d1c-8768-04d664db29f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972286825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3972286825
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1001089698
Short name T102
Test name
Test status
Simulation time 40238751 ps
CPU time 0.85 seconds
Started Jul 16 04:53:46 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 197852 kb
Host smart-f8da60f3-c211-4513-aa04-1de527659429
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001089698 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1001089698
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3124776344
Short name T715
Test name
Test status
Simulation time 365791417 ps
CPU time 1.62 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 198492 kb
Host smart-8f945819-f413-40d9-91c4-2738c6aae8ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124776344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3124776344
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2120132365
Short name T112
Test name
Test status
Simulation time 334385497 ps
CPU time 1.16 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:10 PM PDT 24
Peak memory 198064 kb
Host smart-8e3d1b9b-53b9-46fb-a237-bf2d7177f83a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120132365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2120132365
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3932401577
Short name T834
Test name
Test status
Simulation time 21432217 ps
CPU time 0.77 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:04 PM PDT 24
Peak memory 198184 kb
Host smart-514565be-b57a-421a-8807-7e84c6ef9872
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932401577 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3932401577
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.906279702
Short name T98
Test name
Test status
Simulation time 13340864 ps
CPU time 0.58 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:45 PM PDT 24
Peak memory 194140 kb
Host smart-2eaea1cd-53bd-4cf2-950f-8a626bf48574
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906279702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.906279702
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2801779617
Short name T779
Test name
Test status
Simulation time 41692638 ps
CPU time 0.64 seconds
Started Jul 16 04:53:46 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 194872 kb
Host smart-96993406-63cc-4bf5-a670-1a48de35a260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801779617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2801779617
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3301628328
Short name T107
Test name
Test status
Simulation time 15313037 ps
CPU time 0.69 seconds
Started Jul 16 04:53:49 PM PDT 24
Finished Jul 16 04:53:51 PM PDT 24
Peak memory 195160 kb
Host smart-98c374e7-48e5-4e6d-be43-a1054734f820
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301628328 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3301628328
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2454278141
Short name T807
Test name
Test status
Simulation time 64499761 ps
CPU time 3.43 seconds
Started Jul 16 04:53:47 PM PDT 24
Finished Jul 16 04:53:51 PM PDT 24
Peak memory 198512 kb
Host smart-62504ee7-4149-4b9c-91e0-72082cc35ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454278141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2454278141
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3865157524
Short name T738
Test name
Test status
Simulation time 467498767 ps
CPU time 1.4 seconds
Started Jul 16 04:53:43 PM PDT 24
Finished Jul 16 04:53:46 PM PDT 24
Peak memory 198560 kb
Host smart-89b197bf-e2e2-442b-bd1b-1be37e360baf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865157524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3865157524
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4064944473
Short name T728
Test name
Test status
Simulation time 247395777 ps
CPU time 1.23 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:15 PM PDT 24
Peak memory 198560 kb
Host smart-c0c7e77a-be52-4e5a-a670-7d39a86089a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064944473 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4064944473
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2662912482
Short name T831
Test name
Test status
Simulation time 22066974 ps
CPU time 0.58 seconds
Started Jul 16 04:53:46 PM PDT 24
Finished Jul 16 04:53:48 PM PDT 24
Peak memory 195144 kb
Host smart-a05bd617-7b47-4096-9cd1-516b155194e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662912482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2662912482
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.912632977
Short name T796
Test name
Test status
Simulation time 19207747 ps
CPU time 0.6 seconds
Started Jul 16 04:53:53 PM PDT 24
Finished Jul 16 04:53:54 PM PDT 24
Peak memory 194620 kb
Host smart-359e0e31-0b14-4b9a-882b-fe85fd9d15fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912632977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.912632977
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2010109861
Short name T826
Test name
Test status
Simulation time 13412555 ps
CPU time 0.66 seconds
Started Jul 16 04:53:45 PM PDT 24
Finished Jul 16 04:53:47 PM PDT 24
Peak memory 195472 kb
Host smart-1b0b142d-3923-4723-966e-ead3a54ff9a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010109861 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2010109861
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2089323263
Short name T793
Test name
Test status
Simulation time 59365105 ps
CPU time 1.61 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:03 PM PDT 24
Peak memory 198580 kb
Host smart-a5bbf8f0-3183-4fa7-9de1-f88d5182dec3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089323263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2089323263
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.442001250
Short name T837
Test name
Test status
Simulation time 476476942 ps
CPU time 1.4 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 198500 kb
Host smart-8e275738-0751-4ee4-ae78-21fe1915cfc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442001250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.442001250
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2941521734
Short name T761
Test name
Test status
Simulation time 204747461 ps
CPU time 0.71 seconds
Started Jul 16 04:53:54 PM PDT 24
Finished Jul 16 04:53:55 PM PDT 24
Peak memory 198344 kb
Host smart-e2878b5c-0799-4e3f-905d-cbc92dfc6c49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941521734 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2941521734
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2650176374
Short name T764
Test name
Test status
Simulation time 48883540 ps
CPU time 0.61 seconds
Started Jul 16 04:54:07 PM PDT 24
Finished Jul 16 04:54:08 PM PDT 24
Peak memory 195380 kb
Host smart-2aaa6330-b11a-4ec7-b870-ce6f7eb9cd97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650176374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2650176374
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.648752830
Short name T838
Test name
Test status
Simulation time 32020006 ps
CPU time 0.61 seconds
Started Jul 16 04:54:01 PM PDT 24
Finished Jul 16 04:54:04 PM PDT 24
Peak memory 194328 kb
Host smart-b17307ac-2cae-4ef4-8aa8-2c56be3674d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648752830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.648752830
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3174961468
Short name T805
Test name
Test status
Simulation time 155096635 ps
CPU time 0.84 seconds
Started Jul 16 04:53:59 PM PDT 24
Finished Jul 16 04:54:02 PM PDT 24
Peak memory 196776 kb
Host smart-518121b1-d745-4b5f-b453-f1bcf6991425
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174961468 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3174961468
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2840260101
Short name T802
Test name
Test status
Simulation time 48664323 ps
CPU time 1.16 seconds
Started Jul 16 04:53:55 PM PDT 24
Finished Jul 16 04:53:56 PM PDT 24
Peak memory 198560 kb
Host smart-2ecc05b5-c6fa-4f81-9756-03d1577059be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840260101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2840260101
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2781709880
Short name T52
Test name
Test status
Simulation time 419190804 ps
CPU time 1.8 seconds
Started Jul 16 04:53:55 PM PDT 24
Finished Jul 16 04:53:58 PM PDT 24
Peak memory 198520 kb
Host smart-8b289c81-0547-4072-87d9-e1ec8afd62a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781709880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2781709880
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.629600200
Short name T825
Test name
Test status
Simulation time 73156497 ps
CPU time 0.76 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 198384 kb
Host smart-ab16e99a-eb54-4af1-8e7e-a3e8414f977a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629600200 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.629600200
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3123809758
Short name T800
Test name
Test status
Simulation time 40541022 ps
CPU time 0.62 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:58 PM PDT 24
Peak memory 195736 kb
Host smart-eb0e29ff-ff4d-436b-9c14-ae738d6d6e05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123809758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3123809758
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2933408213
Short name T717
Test name
Test status
Simulation time 11995702 ps
CPU time 0.59 seconds
Started Jul 16 04:54:06 PM PDT 24
Finished Jul 16 04:54:08 PM PDT 24
Peak memory 194104 kb
Host smart-0c3b16f6-27d8-4a38-846d-2e4210793a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933408213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2933408213
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4049253906
Short name T84
Test name
Test status
Simulation time 19067659 ps
CPU time 0.68 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:53:59 PM PDT 24
Peak memory 195792 kb
Host smart-2618708c-9baa-4688-a789-f7ea6e4265f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049253906 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4049253906
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2766685180
Short name T742
Test name
Test status
Simulation time 52174675 ps
CPU time 2.53 seconds
Started Jul 16 04:53:56 PM PDT 24
Finished Jul 16 04:53:59 PM PDT 24
Peak memory 198500 kb
Host smart-5c6523df-7022-4685-b00c-b60c05901898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766685180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2766685180
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.606429422
Short name T821
Test name
Test status
Simulation time 152471025 ps
CPU time 1.13 seconds
Started Jul 16 04:53:57 PM PDT 24
Finished Jul 16 04:54:00 PM PDT 24
Peak memory 198560 kb
Host smart-abd1b6ac-6e4e-43b1-bc4e-cc83c152bf51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606429422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.606429422
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3364496546
Short name T658
Test name
Test status
Simulation time 28749368 ps
CPU time 0.58 seconds
Started Jul 16 04:54:49 PM PDT 24
Finished Jul 16 04:54:51 PM PDT 24
Peak memory 195296 kb
Host smart-49a86cf4-1f3a-4956-bd5c-d45bba0e9853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364496546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3364496546
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3622862039
Short name T457
Test name
Test status
Simulation time 27123846 ps
CPU time 0.7 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 194616 kb
Host smart-d0d2cdbc-30c7-4054-813f-8fe5ad35b42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622862039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3622862039
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.368216924
Short name T18
Test name
Test status
Simulation time 710749896 ps
CPU time 23.2 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 198456 kb
Host smart-d94fca4c-8adc-44ca-90fa-0f4f54a2d2cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368216924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.368216924
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.565154695
Short name T162
Test name
Test status
Simulation time 803381027 ps
CPU time 0.9 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 197808 kb
Host smart-c59515bd-7d7e-44b4-bc71-556b1a5455bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565154695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.565154695
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1612403366
Short name T539
Test name
Test status
Simulation time 321350522 ps
CPU time 1.3 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:54:59 PM PDT 24
Peak memory 197688 kb
Host smart-7255367e-d839-4235-abc4-a796d75a94af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612403366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1612403366
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2382592564
Short name T459
Test name
Test status
Simulation time 81862277 ps
CPU time 2.24 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:46 PM PDT 24
Peak memory 198588 kb
Host smart-17855d9a-f828-4f47-b7ba-939208d5e014
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382592564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2382592564
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.121411684
Short name T299
Test name
Test status
Simulation time 654415631 ps
CPU time 3.46 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 198564 kb
Host smart-4e9a3b70-c509-4474-9757-87f9ed15377c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121411684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.121411684
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.251062972
Short name T619
Test name
Test status
Simulation time 87005792 ps
CPU time 0.9 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:46 PM PDT 24
Peak memory 197044 kb
Host smart-175639ff-2a43-41be-bb41-01b0b37a4371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251062972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.251062972
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4015384243
Short name T453
Test name
Test status
Simulation time 66245302 ps
CPU time 1.22 seconds
Started Jul 16 04:54:42 PM PDT 24
Finished Jul 16 04:54:44 PM PDT 24
Peak memory 197596 kb
Host smart-67d4a9f0-ec74-46d5-aa92-5c5f1cb29145
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015384243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4015384243
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2702269994
Short name T254
Test name
Test status
Simulation time 241724035 ps
CPU time 2.85 seconds
Started Jul 16 04:54:41 PM PDT 24
Finished Jul 16 04:54:45 PM PDT 24
Peak memory 198468 kb
Host smart-0e1a7ae3-63ba-4da1-81e6-e2ce48854f98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702269994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2702269994
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2994429282
Short name T41
Test name
Test status
Simulation time 32180356 ps
CPU time 0.76 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 214140 kb
Host smart-f92d3db2-6072-48a2-adfe-a960fe18d17f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994429282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2994429282
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1149048669
Short name T566
Test name
Test status
Simulation time 737195967 ps
CPU time 0.94 seconds
Started Jul 16 04:54:40 PM PDT 24
Finished Jul 16 04:54:42 PM PDT 24
Peak memory 196592 kb
Host smart-629b1701-790e-4f6c-9339-1e7196b469d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149048669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1149048669
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.179857879
Short name T243
Test name
Test status
Simulation time 51942709 ps
CPU time 1.05 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:54:38 PM PDT 24
Peak memory 196312 kb
Host smart-02436961-f174-4169-8b20-d4deda3fac89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179857879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.179857879
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3899485069
Short name T33
Test name
Test status
Simulation time 7374801390 ps
CPU time 130.93 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:56:42 PM PDT 24
Peak memory 198572 kb
Host smart-c5b71bfd-5d33-44cb-946e-ea7651e3a034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899485069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3899485069
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3962918141
Short name T574
Test name
Test status
Simulation time 28943322076 ps
CPU time 627.89 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 05:05:08 PM PDT 24
Peak memory 198892 kb
Host smart-cf9b9740-b281-4872-9114-b86ee5992858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3962918141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3962918141
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3682233607
Short name T203
Test name
Test status
Simulation time 13354955 ps
CPU time 0.55 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:56 PM PDT 24
Peak memory 194052 kb
Host smart-86aab5f2-6196-43da-b565-d2a6a15c4ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682233607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3682233607
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.706270032
Short name T461
Test name
Test status
Simulation time 389949289 ps
CPU time 0.68 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 194584 kb
Host smart-7159b1f9-965e-4ecc-8c3e-5ea27852c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706270032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.706270032
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3191314157
Short name T75
Test name
Test status
Simulation time 998378328 ps
CPU time 27.97 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:54:59 PM PDT 24
Peak memory 197468 kb
Host smart-0f9b4e8f-d311-41c3-9b44-2404ecce258c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191314157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3191314157
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1167968314
Short name T191
Test name
Test status
Simulation time 345946330 ps
CPU time 1.01 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 196988 kb
Host smart-916450af-962d-43bd-ac87-94aad2381723
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167968314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1167968314
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3820909016
Short name T142
Test name
Test status
Simulation time 29020184 ps
CPU time 0.81 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:44 PM PDT 24
Peak memory 195624 kb
Host smart-31818470-c0e6-41b1-809a-c4286a3fbdc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820909016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3820909016
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2478133229
Short name T333
Test name
Test status
Simulation time 33886831 ps
CPU time 1.35 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:37 PM PDT 24
Peak memory 196784 kb
Host smart-3d3f914c-f0e3-44ca-a2d8-01bc8e19630c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478133229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2478133229
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1237146521
Short name T694
Test name
Test status
Simulation time 420020413 ps
CPU time 1.37 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:46 PM PDT 24
Peak memory 196588 kb
Host smart-7d0aa4ed-3639-4bc8-a6cb-619b36aa22b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237146521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1237146521
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.54809560
Short name T253
Test name
Test status
Simulation time 189458596 ps
CPU time 1.21 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:27 PM PDT 24
Peak memory 196308 kb
Host smart-9fe6f614-d838-43e9-8a19-2779b62b02b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54809560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.54809560
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.222511500
Short name T352
Test name
Test status
Simulation time 533022942 ps
CPU time 0.88 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:54:40 PM PDT 24
Peak memory 196508 kb
Host smart-e446dcf1-c4ad-4074-ad71-c0fafe49f429
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222511500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.222511500
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.445076824
Short name T216
Test name
Test status
Simulation time 121683960 ps
CPU time 3.39 seconds
Started Jul 16 04:54:40 PM PDT 24
Finished Jul 16 04:54:45 PM PDT 24
Peak memory 198164 kb
Host smart-9ffebf9b-98cd-49a9-b11e-ebf60952bc9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445076824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.445076824
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2565830519
Short name T42
Test name
Test status
Simulation time 172437330 ps
CPU time 0.79 seconds
Started Jul 16 04:54:48 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 214100 kb
Host smart-b20ce0f7-feda-40c0-8359-95cd0e707175
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565830519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2565830519
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.238637115
Short name T337
Test name
Test status
Simulation time 105551415 ps
CPU time 0.94 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:33 PM PDT 24
Peak memory 196260 kb
Host smart-ef963921-6caf-4302-af76-6e13f5686348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238637115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.238637115
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4101319630
Short name T376
Test name
Test status
Simulation time 175298495 ps
CPU time 0.89 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 196952 kb
Host smart-6ff20543-f167-4bc1-9613-1a336b3f56bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101319630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4101319630
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2177371286
Short name T255
Test name
Test status
Simulation time 6525835702 ps
CPU time 22.97 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 198572 kb
Host smart-19a02b34-eb08-44a0-9a2e-777f84a7dbd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177371286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2177371286
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2912872294
Short name T196
Test name
Test status
Simulation time 13206341 ps
CPU time 0.6 seconds
Started Jul 16 04:55:03 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 194524 kb
Host smart-75923d31-c551-4a0e-8094-29c5ca1323b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912872294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2912872294
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2431921009
Short name T278
Test name
Test status
Simulation time 127388718 ps
CPU time 0.74 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 195696 kb
Host smart-6065c756-e56b-49dd-804f-c83186dc63a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431921009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2431921009
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3431905871
Short name T541
Test name
Test status
Simulation time 557306607 ps
CPU time 18.74 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 196076 kb
Host smart-9cf6ab0f-9822-4316-b1dd-53c9b92c9c44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431905871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3431905871
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.4074722949
Short name T399
Test name
Test status
Simulation time 124910429 ps
CPU time 0.86 seconds
Started Jul 16 04:55:06 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 196600 kb
Host smart-39de9f73-697f-4483-8a82-1cc7a77b8ae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074722949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.4074722949
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4137397200
Short name T627
Test name
Test status
Simulation time 128912180 ps
CPU time 0.96 seconds
Started Jul 16 04:55:18 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 196400 kb
Host smart-b9f0424e-0e11-49a1-bff5-2aee07f0f0ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137397200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4137397200
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2321900059
Short name T143
Test name
Test status
Simulation time 144001524 ps
CPU time 2.86 seconds
Started Jul 16 04:55:10 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 197680 kb
Host smart-c407449f-f1ab-461f-a3fb-bdafed4d409e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321900059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2321900059
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.130471419
Short name T222
Test name
Test status
Simulation time 21325440 ps
CPU time 0.83 seconds
Started Jul 16 04:55:05 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 196048 kb
Host smart-59478928-3ed7-4dca-8bb9-14e3b28b5f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130471419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.130471419
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1396062704
Short name T670
Test name
Test status
Simulation time 166682882 ps
CPU time 0.71 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 196000 kb
Host smart-ebd318a2-9a2b-4545-920b-c8590e1223ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396062704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1396062704
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_smoke.3881832580
Short name T348
Test name
Test status
Simulation time 105717850 ps
CPU time 0.92 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 196080 kb
Host smart-970d79f2-1ce4-4f7c-8dd9-c93739f48592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881832580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3881832580
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1442135016
Short name T288
Test name
Test status
Simulation time 75599355 ps
CPU time 1.12 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 196272 kb
Host smart-8a7455b3-c5cc-4fef-a74b-a4c4bd85e49d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442135016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1442135016
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1850739533
Short name T578
Test name
Test status
Simulation time 3477748279 ps
CPU time 82.57 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:56:28 PM PDT 24
Peak memory 198668 kb
Host smart-4667dcb6-df8d-4315-b26c-d1a27400cc80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850739533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1850739533
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3618840927
Short name T44
Test name
Test status
Simulation time 11181192 ps
CPU time 0.59 seconds
Started Jul 16 04:55:06 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 194556 kb
Host smart-aa2e08b7-81f6-459b-9cca-863c91f06707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618840927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3618840927
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2431958581
Short name T542
Test name
Test status
Simulation time 29551109 ps
CPU time 0.75 seconds
Started Jul 16 04:55:15 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 196516 kb
Host smart-c248ae9f-c542-48c0-8295-44adcd324d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431958581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2431958581
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2324939693
Short name T600
Test name
Test status
Simulation time 447722872 ps
CPU time 4.13 seconds
Started Jul 16 04:55:09 PM PDT 24
Finished Jul 16 04:55:15 PM PDT 24
Peak memory 196016 kb
Host smart-85925f31-7a1d-4264-a966-068f238ce16a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324939693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2324939693
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.747588504
Short name T714
Test name
Test status
Simulation time 106651558 ps
CPU time 0.77 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 197048 kb
Host smart-4468f11b-bd4f-4eb8-8ea7-318113648b23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747588504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.747588504
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.4042789753
Short name T167
Test name
Test status
Simulation time 41758528 ps
CPU time 1.17 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 196664 kb
Host smart-851b6959-a0e2-41fa-84ee-fdf797013a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042789753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.4042789753
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.71762866
Short name T23
Test name
Test status
Simulation time 379363421 ps
CPU time 3.58 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:09 PM PDT 24
Peak memory 197008 kb
Host smart-b9957510-f338-42d8-9b6f-306bd2c68060
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71762866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.gpio_intr_with_filter_rand_intr_event.71762866
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2331150775
Short name T289
Test name
Test status
Simulation time 360855498 ps
CPU time 2.76 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 197096 kb
Host smart-d188fc35-c2df-43af-90dd-08df9ca52dee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331150775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2331150775
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2788999780
Short name T672
Test name
Test status
Simulation time 69078370 ps
CPU time 1.27 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 197564 kb
Host smart-8a72a77f-dfd4-4564-96c7-70a46685787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788999780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2788999780
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3534574874
Short name T606
Test name
Test status
Simulation time 17438744 ps
CPU time 0.75 seconds
Started Jul 16 04:55:14 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 195872 kb
Host smart-ce1b9ad3-94f3-413c-b4c8-a2b795ead07f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534574874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3534574874
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.795838394
Short name T490
Test name
Test status
Simulation time 313588018 ps
CPU time 4.99 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 198416 kb
Host smart-2211694c-80f8-4bcd-874d-05e23151f23c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795838394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.795838394
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.535963800
Short name T711
Test name
Test status
Simulation time 163374220 ps
CPU time 1.18 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 196036 kb
Host smart-f9653048-7ea3-4c11-a5da-fb537d7bb0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535963800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.535963800
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1414659190
Short name T567
Test name
Test status
Simulation time 467388502 ps
CPU time 1.28 seconds
Started Jul 16 04:55:15 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 197200 kb
Host smart-21d86b0b-db0e-4006-bd3d-5cd5e7721d54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414659190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1414659190
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1959168130
Short name T379
Test name
Test status
Simulation time 12395633520 ps
CPU time 167.02 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:57:45 PM PDT 24
Peak memory 198632 kb
Host smart-c4045722-d836-4184-b1da-29b3da548fd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959168130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1959168130
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1768749462
Short name T407
Test name
Test status
Simulation time 39665380 ps
CPU time 0.55 seconds
Started Jul 16 04:54:51 PM PDT 24
Finished Jul 16 04:54:53 PM PDT 24
Peak memory 193288 kb
Host smart-1a2a705c-81ad-4d18-b790-157352d53944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768749462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1768749462
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2570525374
Short name T234
Test name
Test status
Simulation time 106357375 ps
CPU time 0.92 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 197096 kb
Host smart-66d9792f-4712-42f3-bdaa-4aac71402dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570525374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2570525374
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1378076904
Short name T504
Test name
Test status
Simulation time 706672146 ps
CPU time 22.49 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:35 PM PDT 24
Peak memory 197684 kb
Host smart-295b0c00-cb81-4705-b26f-b95b4e159fd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378076904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1378076904
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.184546489
Short name T10
Test name
Test status
Simulation time 384288856 ps
CPU time 1.02 seconds
Started Jul 16 04:55:09 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 197004 kb
Host smart-ae4356b3-700e-4ed5-b92d-37d45758bd32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184546489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.184546489
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3504282062
Short name T208
Test name
Test status
Simulation time 180067929 ps
CPU time 1.23 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 196276 kb
Host smart-1a96dbb6-32bf-4bf3-9631-68c58c6ab24b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504282062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3504282062
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.831501126
Short name T295
Test name
Test status
Simulation time 207725801 ps
CPU time 2.17 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 196824 kb
Host smart-be603570-0182-460d-b9ba-f4fd990ca5d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831501126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.831501126
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3348045961
Short name T517
Test name
Test status
Simulation time 81616525 ps
CPU time 1.35 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 196284 kb
Host smart-7f6ce755-a81f-483d-8d41-e24db1371bd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348045961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3348045961
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3514180608
Short name T485
Test name
Test status
Simulation time 84427204 ps
CPU time 1.11 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 196544 kb
Host smart-c7e1f0ec-eb81-4d7d-afe0-9f25035bc693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514180608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3514180608
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.685355778
Short name T449
Test name
Test status
Simulation time 81884426 ps
CPU time 1.07 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 196588 kb
Host smart-1beefe7d-cf84-40da-b392-2c532b8170a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685355778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.685355778
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.910281577
Short name T636
Test name
Test status
Simulation time 235264912 ps
CPU time 1.6 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 198512 kb
Host smart-19e0bf3a-86d3-4943-af38-7cb55ed95955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910281577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.910281577
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2324409528
Short name T596
Test name
Test status
Simulation time 81975420 ps
CPU time 1.38 seconds
Started Jul 16 04:55:09 PM PDT 24
Finished Jul 16 04:55:13 PM PDT 24
Peak memory 198568 kb
Host smart-7a93205e-be6e-4820-af0e-2601ed7d26c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324409528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2324409528
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3597287187
Short name T344
Test name
Test status
Simulation time 26603206 ps
CPU time 0.86 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 197532 kb
Host smart-7b1bfcb5-e099-4964-9f44-326b91ca524e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597287187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3597287187
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.104139466
Short name T296
Test name
Test status
Simulation time 19931477122 ps
CPU time 132.8 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:57:25 PM PDT 24
Peak memory 198524 kb
Host smart-dcabcaa9-6801-4077-a01a-eee2059c2a69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104139466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.104139466
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.219878236
Short name T684
Test name
Test status
Simulation time 174008068 ps
CPU time 0.57 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 195468 kb
Host smart-8a8c2eea-9108-4695-a733-d53b1987be53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219878236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.219878236
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2007644373
Short name T178
Test name
Test status
Simulation time 146212198 ps
CPU time 0.74 seconds
Started Jul 16 04:55:09 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 196440 kb
Host smart-96128650-6874-4997-bf40-390af52ed7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007644373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2007644373
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1241611900
Short name T385
Test name
Test status
Simulation time 1463527782 ps
CPU time 4.6 seconds
Started Jul 16 04:55:25 PM PDT 24
Finished Jul 16 04:55:31 PM PDT 24
Peak memory 196420 kb
Host smart-8ed835a5-509e-4354-80d5-577225d034f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241611900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1241611900
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2748829106
Short name T483
Test name
Test status
Simulation time 63767750 ps
CPU time 0.7 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 195872 kb
Host smart-a039f287-b60e-4e20-b7f8-86acf8e0954c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748829106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2748829106
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3680389212
Short name T430
Test name
Test status
Simulation time 79588889 ps
CPU time 1.19 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 196628 kb
Host smart-bdfb5174-60ce-4f34-9432-963bea637c47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680389212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3680389212
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1014435526
Short name T384
Test name
Test status
Simulation time 583531630 ps
CPU time 2.85 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 198556 kb
Host smart-43117d2b-53cc-4c1b-8101-ad7af85ac1a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014435526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1014435526
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.946377913
Short name T706
Test name
Test status
Simulation time 641249623 ps
CPU time 3.01 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 197780 kb
Host smart-00036533-61a7-48e1-a563-033abf55b111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946377913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
946377913
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2654006527
Short name T365
Test name
Test status
Simulation time 66401792 ps
CPU time 0.83 seconds
Started Jul 16 04:55:16 PM PDT 24
Finished Jul 16 04:55:22 PM PDT 24
Peak memory 197632 kb
Host smart-620e0aa6-d704-4a36-b7b6-ac37d4e27ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654006527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2654006527
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.4239766266
Short name T495
Test name
Test status
Simulation time 37388012 ps
CPU time 0.94 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 197284 kb
Host smart-840e8709-93f8-4ea7-83b3-2f2d4b242324
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239766266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.4239766266
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2595381250
Short name T204
Test name
Test status
Simulation time 354776623 ps
CPU time 3.04 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 198544 kb
Host smart-fceb4a5e-d8ba-4ad1-ba87-c9435a078da3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595381250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2595381250
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2891693219
Short name T535
Test name
Test status
Simulation time 446634375 ps
CPU time 0.96 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 197648 kb
Host smart-28541345-4b53-4caa-bed4-4ae012fa4567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891693219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2891693219
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1204200557
Short name T146
Test name
Test status
Simulation time 249016793 ps
CPU time 1.11 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 196432 kb
Host smart-2222a5e1-57ff-4821-bc5e-782d21f61a9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204200557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1204200557
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2841143547
Short name T687
Test name
Test status
Simulation time 18187472780 ps
CPU time 42.47 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:55:40 PM PDT 24
Peak memory 198636 kb
Host smart-e6e3baba-f093-46c8-a04c-cb1dfbaa2291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841143547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2841143547
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3743897629
Short name T60
Test name
Test status
Simulation time 27384281839 ps
CPU time 385.69 seconds
Started Jul 16 04:55:25 PM PDT 24
Finished Jul 16 05:01:51 PM PDT 24
Peak memory 198784 kb
Host smart-14d95017-ecf0-4d65-bca5-4596790dc0a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3743897629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3743897629
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1327341581
Short name T372
Test name
Test status
Simulation time 33656185 ps
CPU time 0.61 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 194636 kb
Host smart-a93399ef-a993-4608-9280-5776a168b517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327341581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1327341581
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1572097734
Short name T11
Test name
Test status
Simulation time 26901818 ps
CPU time 0.62 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 195232 kb
Host smart-197c5a32-0eb1-4975-b067-0969b1a2d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572097734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1572097734
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2634554466
Short name T524
Test name
Test status
Simulation time 648368358 ps
CPU time 11.5 seconds
Started Jul 16 04:55:14 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 198476 kb
Host smart-30356922-5132-4661-a53a-2fb7057e28d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634554466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2634554466
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1190625186
Short name T2
Test name
Test status
Simulation time 92326462 ps
CPU time 0.98 seconds
Started Jul 16 04:55:01 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 198368 kb
Host smart-af725e47-4c64-4a91-b46b-b680c0962ee2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190625186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1190625186
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1247941943
Short name T499
Test name
Test status
Simulation time 43026801 ps
CPU time 1.28 seconds
Started Jul 16 04:55:03 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 197460 kb
Host smart-9b81247e-005f-4d2e-9ce4-623724fae988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247941943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1247941943
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3096648816
Short name T357
Test name
Test status
Simulation time 122839608 ps
CPU time 2.5 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:13 PM PDT 24
Peak memory 198580 kb
Host smart-0788fe1e-7da4-44a1-9204-9984c6eaeed9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096648816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3096648816
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1625020772
Short name T264
Test name
Test status
Simulation time 47900719 ps
CPU time 1.25 seconds
Started Jul 16 04:55:05 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 197244 kb
Host smart-97cd140c-658d-4f05-84b1-90493f569ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625020772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1625020772
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3467454512
Short name T540
Test name
Test status
Simulation time 141424300 ps
CPU time 1.2 seconds
Started Jul 16 04:55:05 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 197516 kb
Host smart-c3de2fec-3828-476b-9c21-958f802d8feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467454512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3467454512
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2509662704
Short name T329
Test name
Test status
Simulation time 46641583 ps
CPU time 0.93 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 196536 kb
Host smart-207dc26f-193d-4180-a3ba-21925ef97d1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509662704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2509662704
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3432827044
Short name T226
Test name
Test status
Simulation time 29812748 ps
CPU time 1.42 seconds
Started Jul 16 04:55:01 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 198420 kb
Host smart-00cae6ee-922a-4179-8fa7-6f807d1c4cad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432827044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3432827044
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3276280452
Short name T317
Test name
Test status
Simulation time 262998701 ps
CPU time 1.31 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 196704 kb
Host smart-59581c4d-f5a4-40e1-b1d7-efc4b209976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276280452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3276280452
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3513902223
Short name T639
Test name
Test status
Simulation time 846622521 ps
CPU time 1.17 seconds
Started Jul 16 04:55:06 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 197000 kb
Host smart-194476a4-8846-458a-87ef-1fdf70e12231
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513902223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3513902223
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2857219364
Short name T528
Test name
Test status
Simulation time 3910393122 ps
CPU time 102.81 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:56:47 PM PDT 24
Peak memory 198612 kb
Host smart-86a25071-bb9a-4002-82a7-bc523118e6a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857219364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2857219364
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3503346775
Short name T63
Test name
Test status
Simulation time 113368248205 ps
CPU time 1572.96 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 05:21:15 PM PDT 24
Peak memory 198796 kb
Host smart-994c76b1-0588-4378-8f7b-0c8b0efcbe1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3503346775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3503346775
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3797605800
Short name T508
Test name
Test status
Simulation time 93028896 ps
CPU time 0.94 seconds
Started Jul 16 04:55:06 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 196488 kb
Host smart-4e92408e-c721-49a6-a68e-908b5df74022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797605800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3797605800
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2812023417
Short name T650
Test name
Test status
Simulation time 904328355 ps
CPU time 23.95 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:25 PM PDT 24
Peak memory 198260 kb
Host smart-ae668cdd-bd6d-4567-b6ee-9a84bc67ec75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812023417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2812023417
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.299161483
Short name T681
Test name
Test status
Simulation time 151396918 ps
CPU time 1 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 198176 kb
Host smart-357ca0cf-3e7f-494a-9a4d-dacb859172af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299161483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.299161483
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2114987446
Short name T151
Test name
Test status
Simulation time 27526950 ps
CPU time 0.9 seconds
Started Jul 16 04:55:19 PM PDT 24
Finished Jul 16 04:55:21 PM PDT 24
Peak memory 196316 kb
Host smart-d94e15e6-abf5-49fc-a66c-4106a381d8be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114987446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2114987446
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3902649429
Short name T114
Test name
Test status
Simulation time 299891498 ps
CPU time 2.89 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 198496 kb
Host smart-41d8de0b-b1b0-4022-b450-a639ed2e58bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902649429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3902649429
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1204714341
Short name T477
Test name
Test status
Simulation time 220812917 ps
CPU time 3.26 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 196332 kb
Host smart-7b3bdbb7-d305-470b-986b-d3baf1f38927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204714341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1204714341
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1920781751
Short name T113
Test name
Test status
Simulation time 65380556 ps
CPU time 0.82 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 197104 kb
Host smart-edc4141b-69a2-4800-8c33-ab19c9170e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920781751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1920781751
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1149102783
Short name T81
Test name
Test status
Simulation time 48980405 ps
CPU time 0.89 seconds
Started Jul 16 04:55:10 PM PDT 24
Finished Jul 16 04:55:13 PM PDT 24
Peak memory 197264 kb
Host smart-b1751f33-2e56-4d14-9f4e-d2c4ae1e118d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149102783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1149102783
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.874319584
Short name T387
Test name
Test status
Simulation time 494403522 ps
CPU time 5.42 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 198468 kb
Host smart-f4036ecc-1df0-4a89-9c9a-6c08d4d0a29c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874319584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.874319584
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1026873088
Short name T308
Test name
Test status
Simulation time 151988037 ps
CPU time 0.92 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 196744 kb
Host smart-035a7c97-6868-4a5c-867b-ec4b55ffa631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026873088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1026873088
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2114786715
Short name T26
Test name
Test status
Simulation time 253255488 ps
CPU time 0.91 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 195648 kb
Host smart-8e925907-5fac-4c56-ba71-148f1eb1f025
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114786715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2114786715
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1312965834
Short name T653
Test name
Test status
Simulation time 68448940152 ps
CPU time 125.58 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:57:23 PM PDT 24
Peak memory 198768 kb
Host smart-48bc0e6d-2a3a-4b6e-8c7b-146de907e15d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312965834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1312965834
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.460106215
Short name T368
Test name
Test status
Simulation time 48274901 ps
CPU time 0.6 seconds
Started Jul 16 04:55:04 PM PDT 24
Finished Jul 16 04:55:09 PM PDT 24
Peak memory 195312 kb
Host smart-fd665bae-d5be-4759-8ed0-883afe2186ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460106215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.460106215
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2109067507
Short name T580
Test name
Test status
Simulation time 17809996 ps
CPU time 0.64 seconds
Started Jul 16 04:55:25 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 195216 kb
Host smart-c8258a50-53ff-4b94-92cc-e599296fa654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109067507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2109067507
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.506840648
Short name T705
Test name
Test status
Simulation time 125899871 ps
CPU time 4.01 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 197020 kb
Host smart-3bf22d40-d871-4458-a07f-3e6f766057c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506840648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.506840648
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.61319011
Short name T266
Test name
Test status
Simulation time 393080099 ps
CPU time 0.92 seconds
Started Jul 16 04:55:18 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 197596 kb
Host smart-d1729b9a-91bb-4de2-b2a3-d1748d1def44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61319011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.61319011
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.4167651311
Short name T342
Test name
Test status
Simulation time 54298193 ps
CPU time 0.77 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 195016 kb
Host smart-f0c0e7ff-48ce-422a-b081-8ebb8ec9ab6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167651311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.4167651311
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.544387233
Short name T544
Test name
Test status
Simulation time 60675347 ps
CPU time 1.22 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 197316 kb
Host smart-6a1fface-a75d-4bd1-a09a-8daedebce4cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544387233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.544387233
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3793569340
Short name T547
Test name
Test status
Simulation time 87910853 ps
CPU time 2.45 seconds
Started Jul 16 04:55:04 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 198592 kb
Host smart-b0547075-e130-4057-ab9b-ac9b113b31bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793569340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3793569340
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3927386033
Short name T287
Test name
Test status
Simulation time 448017547 ps
CPU time 0.94 seconds
Started Jul 16 04:55:27 PM PDT 24
Finished Jul 16 04:55:28 PM PDT 24
Peak memory 197072 kb
Host smart-99cba510-c28e-4b78-a973-c59e532e1d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927386033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3927386033
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1037841728
Short name T590
Test name
Test status
Simulation time 44109014 ps
CPU time 1.01 seconds
Started Jul 16 04:55:04 PM PDT 24
Finished Jul 16 04:55:18 PM PDT 24
Peak memory 196292 kb
Host smart-3fd51420-657b-4129-a9ac-37d9d5c5b257
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037841728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1037841728
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2039082992
Short name T608
Test name
Test status
Simulation time 1219109763 ps
CPU time 5.31 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 198492 kb
Host smart-3c1617f3-06ff-4add-9f64-60f14a617bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039082992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2039082992
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1284549611
Short name T300
Test name
Test status
Simulation time 211937632 ps
CPU time 1 seconds
Started Jul 16 04:55:27 PM PDT 24
Finished Jul 16 04:55:29 PM PDT 24
Peak memory 197020 kb
Host smart-e9c310b5-9bc5-4864-be0a-58161f62cd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284549611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1284549611
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1352494972
Short name T30
Test name
Test status
Simulation time 44173953 ps
CPU time 1.16 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:43 PM PDT 24
Peak memory 197076 kb
Host smart-652a8797-7031-4259-ab34-d791046f195f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352494972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1352494972
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3589716237
Short name T265
Test name
Test status
Simulation time 39577506146 ps
CPU time 75.42 seconds
Started Jul 16 04:55:01 PM PDT 24
Finished Jul 16 04:56:21 PM PDT 24
Peak memory 198584 kb
Host smart-9ff29f82-4e21-4f5c-bff0-514b19d43f06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589716237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3589716237
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3197246890
Short name T70
Test name
Test status
Simulation time 36727600 ps
CPU time 0.59 seconds
Started Jul 16 04:55:04 PM PDT 24
Finished Jul 16 04:55:09 PM PDT 24
Peak memory 195344 kb
Host smart-955b1c35-ded0-450a-97fe-685fbad4e298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197246890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3197246890
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3108318181
Short name T325
Test name
Test status
Simulation time 66791246 ps
CPU time 0.69 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 194800 kb
Host smart-ce4d4a56-ddc1-4509-add7-88bf4c61b811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108318181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3108318181
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1864431804
Short name T117
Test name
Test status
Simulation time 782326361 ps
CPU time 10.68 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:17 PM PDT 24
Peak memory 196020 kb
Host smart-81143b03-d5f7-444f-b722-c3298ba9537f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864431804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1864431804
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3652942603
Short name T520
Test name
Test status
Simulation time 134155241 ps
CPU time 0.7 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:18 PM PDT 24
Peak memory 195172 kb
Host smart-c68351f2-9e0e-4d42-9198-f7ef04c42ad0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652942603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3652942603
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1120480843
Short name T500
Test name
Test status
Simulation time 99349403 ps
CPU time 0.92 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 197104 kb
Host smart-d4caed59-d502-4f92-aea8-e9b2b2f7f8ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120480843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1120480843
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3472158996
Short name T434
Test name
Test status
Simulation time 37606203 ps
CPU time 1.47 seconds
Started Jul 16 04:55:35 PM PDT 24
Finished Jul 16 04:55:37 PM PDT 24
Peak memory 197152 kb
Host smart-5497cdcc-eb79-4ad1-abc5-77351e03165f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472158996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3472158996
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1550191001
Short name T591
Test name
Test status
Simulation time 588233588 ps
CPU time 3.29 seconds
Started Jul 16 04:55:03 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 197532 kb
Host smart-7deffddb-5da7-4289-8ef8-1c1b0376689c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550191001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1550191001
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3781136205
Short name T481
Test name
Test status
Simulation time 19652153 ps
CPU time 0.71 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 195936 kb
Host smart-8b28ec11-6057-47e2-bf01-b32ed2b963d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781136205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3781136205
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3333364300
Short name T268
Test name
Test status
Simulation time 65634580 ps
CPU time 1.2 seconds
Started Jul 16 04:55:06 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 196316 kb
Host smart-b40ab48b-c8f3-4fb1-82a1-7e233d8e3f3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333364300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3333364300
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1188409065
Short name T601
Test name
Test status
Simulation time 506721264 ps
CPU time 5.61 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 04:55:42 PM PDT 24
Peak memory 198416 kb
Host smart-277b9d73-6de6-4b07-aa71-83dbc095298d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188409065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1188409065
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.4139866881
Short name T227
Test name
Test status
Simulation time 162936205 ps
CPU time 0.9 seconds
Started Jul 16 04:55:23 PM PDT 24
Finished Jul 16 04:55:29 PM PDT 24
Peak memory 196740 kb
Host smart-2d52b837-fb18-4c91-ae0d-fffe1f25f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139866881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.4139866881
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1462007941
Short name T159
Test name
Test status
Simulation time 217946237 ps
CPU time 1.41 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 196040 kb
Host smart-ce7555a6-e02f-433c-8def-c3e40769c8a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462007941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1462007941
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.258357786
Short name T382
Test name
Test status
Simulation time 5417707040 ps
CPU time 126.18 seconds
Started Jul 16 04:55:11 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 198624 kb
Host smart-8ae1ee63-315f-4f80-ab3b-ef6888c33665
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258357786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.258357786
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3766882270
Short name T545
Test name
Test status
Simulation time 22387489 ps
CPU time 0.6 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 194536 kb
Host smart-a9425884-d977-4648-b362-b6753968e395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766882270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3766882270
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3909822115
Short name T19
Test name
Test status
Simulation time 90286364 ps
CPU time 0.86 seconds
Started Jul 16 04:55:03 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 197364 kb
Host smart-36272b3d-f602-4a3b-bfcf-5d3f4e41933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909822115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3909822115
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2079574585
Short name T685
Test name
Test status
Simulation time 362025381 ps
CPU time 6.08 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 197436 kb
Host smart-cb0352fa-abbf-444d-818c-3c5b7cb79f24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079574585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2079574585
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2107128955
Short name T273
Test name
Test status
Simulation time 256121257 ps
CPU time 0.9 seconds
Started Jul 16 04:55:24 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 196584 kb
Host smart-feab78bd-d7c1-4a02-b03d-552adff78d6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107128955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2107128955
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2139871627
Short name T223
Test name
Test status
Simulation time 98711934 ps
CPU time 0.9 seconds
Started Jul 16 04:55:29 PM PDT 24
Finished Jul 16 04:55:31 PM PDT 24
Peak memory 197212 kb
Host smart-baf7fa19-f63c-435b-be80-7b06e0c68bf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139871627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2139871627
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.254974154
Short name T136
Test name
Test status
Simulation time 86525762 ps
CPU time 3.2 seconds
Started Jul 16 04:55:15 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 198556 kb
Host smart-54dbdfa0-bfe3-43a6-a9a3-ee83451cd9c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254974154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.254974154
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2909879487
Short name T626
Test name
Test status
Simulation time 158283577 ps
CPU time 1.97 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 196592 kb
Host smart-4c2dc25b-bf25-422d-9329-d753fe9a67ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909879487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2909879487
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3038384595
Short name T206
Test name
Test status
Simulation time 60537089 ps
CPU time 0.77 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 195680 kb
Host smart-cb8f2c70-323d-4251-b4a2-df00cb9d4982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038384595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3038384595
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.325224185
Short name T171
Test name
Test status
Simulation time 124092503 ps
CPU time 1.17 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 197832 kb
Host smart-03b1ba6b-0052-437f-acbc-676d52bde88b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325224185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.325224185
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3761119638
Short name T279
Test name
Test status
Simulation time 383025417 ps
CPU time 4.84 seconds
Started Jul 16 04:55:04 PM PDT 24
Finished Jul 16 04:55:13 PM PDT 24
Peak memory 198504 kb
Host smart-8b4d0d6e-4e73-4f35-9d8b-f6487587a187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761119638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3761119638
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.977130386
Short name T375
Test name
Test status
Simulation time 166415038 ps
CPU time 1.41 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 197356 kb
Host smart-d81f65fe-f7ef-4c09-bcf2-e32e7f876299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977130386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.977130386
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3059672835
Short name T174
Test name
Test status
Simulation time 28129064 ps
CPU time 0.76 seconds
Started Jul 16 04:55:09 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 196420 kb
Host smart-3fff7499-2ab2-429d-9240-4d60cd0af1a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059672835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3059672835
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1599474817
Short name T599
Test name
Test status
Simulation time 12042827684 ps
CPU time 127.03 seconds
Started Jul 16 04:55:15 PM PDT 24
Finished Jul 16 04:57:23 PM PDT 24
Peak memory 198556 kb
Host smart-80dbd970-8b29-4810-ab0e-e0b8d0d89b84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599474817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1599474817
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1271747030
Short name T701
Test name
Test status
Simulation time 26845197749 ps
CPU time 702.99 seconds
Started Jul 16 04:55:03 PM PDT 24
Finished Jul 16 05:06:51 PM PDT 24
Peak memory 198744 kb
Host smart-e4406bd3-0af9-40f5-bfcd-2ea78441571f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1271747030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1271747030
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1298189908
Short name T157
Test name
Test status
Simulation time 13225717 ps
CPU time 0.57 seconds
Started Jul 16 04:55:25 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 194520 kb
Host smart-ef909e74-e51b-489f-b6b9-979043bd3250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298189908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1298189908
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3872340888
Short name T312
Test name
Test status
Simulation time 37323792 ps
CPU time 0.77 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 195848 kb
Host smart-2b9453fc-175e-4ab7-b6f0-1f9495795d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872340888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3872340888
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.998942017
Short name T554
Test name
Test status
Simulation time 246133658 ps
CPU time 8.44 seconds
Started Jul 16 04:55:15 PM PDT 24
Finished Jul 16 04:55:24 PM PDT 24
Peak memory 196052 kb
Host smart-4c122e27-811e-45af-a9e1-51a8289f6c42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998942017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.998942017
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2752474526
Short name T682
Test name
Test status
Simulation time 973209576 ps
CPU time 1.04 seconds
Started Jul 16 04:55:10 PM PDT 24
Finished Jul 16 04:55:13 PM PDT 24
Peak memory 196996 kb
Host smart-348e4b2b-b9cb-43c7-9f22-16ca7d55c828
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752474526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2752474526
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.91707676
Short name T177
Test name
Test status
Simulation time 183956114 ps
CPU time 1.12 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 197240 kb
Host smart-78ec5efb-028b-46cf-8180-70ce2f12d29e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91707676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.91707676
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1158848628
Short name T562
Test name
Test status
Simulation time 41116873 ps
CPU time 1.66 seconds
Started Jul 16 04:55:06 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 198596 kb
Host smart-1448bfb7-b965-4141-ba10-5078913b7455
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158848628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1158848628
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1596753433
Short name T339
Test name
Test status
Simulation time 127192666 ps
CPU time 3.55 seconds
Started Jul 16 04:55:04 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 197724 kb
Host smart-7fe5bfe7-751a-478d-9daa-9f7a7762747d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596753433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1596753433
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2470475327
Short name T669
Test name
Test status
Simulation time 41404917 ps
CPU time 0.92 seconds
Started Jul 16 04:55:04 PM PDT 24
Finished Jul 16 04:55:09 PM PDT 24
Peak memory 196312 kb
Host smart-eefc2dee-d5e4-4e55-886a-3182b2a4412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470475327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2470475327
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.348175941
Short name T316
Test name
Test status
Simulation time 66751329 ps
CPU time 1.33 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 198280 kb
Host smart-d01bb1f7-cd25-4768-a89c-851cd3c36985
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348175941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.348175941
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1082630115
Short name T536
Test name
Test status
Simulation time 348716527 ps
CPU time 2.83 seconds
Started Jul 16 04:55:15 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 198492 kb
Host smart-525ab0ac-8e45-470a-bd82-d3d772ff09b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082630115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1082630115
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1848218441
Short name T704
Test name
Test status
Simulation time 28585591 ps
CPU time 0.83 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 195736 kb
Host smart-5b84cc9d-6ec0-4b47-9b3b-e27ee1bf0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848218441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1848218441
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1994685548
Short name T303
Test name
Test status
Simulation time 29185081 ps
CPU time 0.76 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 195696 kb
Host smart-bc868a32-7162-4fbe-b005-7a79977be3fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994685548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1994685548
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2691929420
Short name T20
Test name
Test status
Simulation time 46493298115 ps
CPU time 131.85 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:57:54 PM PDT 24
Peak memory 198600 kb
Host smart-6ee8ed18-d277-4e38-9d7c-e795677b5c46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691929420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2691929420
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.182549878
Short name T36
Test name
Test status
Simulation time 33069717589 ps
CPU time 459.31 seconds
Started Jul 16 04:55:30 PM PDT 24
Finished Jul 16 05:03:10 PM PDT 24
Peak memory 198764 kb
Host smart-50d301c3-c33a-42e0-a3d3-3b28f22dadca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=182549878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.182549878
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.515839950
Short name T306
Test name
Test status
Simulation time 21715342 ps
CPU time 0.58 seconds
Started Jul 16 04:54:50 PM PDT 24
Finished Jul 16 04:54:52 PM PDT 24
Peak memory 194576 kb
Host smart-e00c4acd-86e9-4a45-bae7-c4f88e391155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515839950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.515839950
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2547601823
Short name T225
Test name
Test status
Simulation time 158026760 ps
CPU time 0.88 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:46 PM PDT 24
Peak memory 197116 kb
Host smart-e6f08c37-cdf3-47e4-978e-695e1132d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547601823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2547601823
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2036021136
Short name T276
Test name
Test status
Simulation time 754228894 ps
CPU time 17.19 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 196880 kb
Host smart-63f635b1-607c-4c0a-bf5c-06755fed4c73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036021136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2036021136
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.27318509
Short name T356
Test name
Test status
Simulation time 49958920 ps
CPU time 0.84 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 197300 kb
Host smart-0161a1d1-d30a-4b52-9bcd-d0724ee0d52f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.27318509
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2447891040
Short name T657
Test name
Test status
Simulation time 70032958 ps
CPU time 1.22 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 196628 kb
Host smart-3fdf48cc-332a-4a11-8085-2e203e2d9557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447891040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2447891040
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3238097107
Short name T609
Test name
Test status
Simulation time 29822321 ps
CPU time 1.28 seconds
Started Jul 16 04:54:41 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 197252 kb
Host smart-8ce19af7-918b-426c-9969-2196b8c3243c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238097107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3238097107
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.4084989974
Short name T713
Test name
Test status
Simulation time 821139262 ps
CPU time 2.21 seconds
Started Jul 16 04:54:45 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 198592 kb
Host smart-95b44b49-bd6a-4c31-bbce-44f52fd28afc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084989974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
4084989974
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2360290593
Short name T588
Test name
Test status
Simulation time 44129718 ps
CPU time 1.11 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 196968 kb
Host smart-ed308eee-b6d6-46b6-93c4-e308079ccda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360290593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2360290593
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4116136991
Short name T674
Test name
Test status
Simulation time 245356017 ps
CPU time 0.99 seconds
Started Jul 16 04:54:48 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 197204 kb
Host smart-7303cda9-b5e3-48a0-a46c-e42e4802c627
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116136991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4116136991
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2455414756
Short name T577
Test name
Test status
Simulation time 78697396 ps
CPU time 3.69 seconds
Started Jul 16 04:54:49 PM PDT 24
Finished Jul 16 04:54:54 PM PDT 24
Peak memory 198412 kb
Host smart-5d8ded10-8658-46f7-85bc-1c0d580b70e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455414756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2455414756
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.401849879
Short name T58
Test name
Test status
Simulation time 133232554 ps
CPU time 0.8 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 214048 kb
Host smart-c7bce29d-74cb-4cee-b697-d5b22d9ec884
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401849879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.401849879
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2893907350
Short name T350
Test name
Test status
Simulation time 26718974 ps
CPU time 0.91 seconds
Started Jul 16 04:54:45 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 196192 kb
Host smart-ee06dba8-fe87-4e1b-bb74-feae1c9178c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893907350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2893907350
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.675250635
Short name T437
Test name
Test status
Simulation time 147250181 ps
CPU time 1.15 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 196336 kb
Host smart-3f60fcaa-0cd5-4e7a-b417-5337d3f2ccec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675250635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.675250635
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1106913464
Short name T197
Test name
Test status
Simulation time 3382558113 ps
CPU time 34.81 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 198524 kb
Host smart-e17e1fe8-9ee0-4087-a58b-e2dc3a037f03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106913464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1106913464
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1418868051
Short name T212
Test name
Test status
Simulation time 11382859 ps
CPU time 0.57 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:32 PM PDT 24
Peak memory 194480 kb
Host smart-3991a259-b0c7-474d-943c-dae20086c502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418868051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1418868051
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2225268210
Short name T691
Test name
Test status
Simulation time 47306501 ps
CPU time 0.71 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 194628 kb
Host smart-36e7c572-21c1-4d13-98a1-3c0441c184b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225268210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2225268210
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1599064846
Short name T176
Test name
Test status
Simulation time 5312218705 ps
CPU time 16.53 seconds
Started Jul 16 04:55:19 PM PDT 24
Finished Jul 16 04:55:36 PM PDT 24
Peak memory 198068 kb
Host smart-78711908-5935-4acf-8158-6036f9045919
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599064846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1599064846
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.828337936
Short name T414
Test name
Test status
Simulation time 63192531 ps
CPU time 0.9 seconds
Started Jul 16 04:55:16 PM PDT 24
Finished Jul 16 04:55:17 PM PDT 24
Peak memory 198452 kb
Host smart-b173345b-f380-4d50-ac24-e47be9dbfad0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828337936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.828337936
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1106708126
Short name T311
Test name
Test status
Simulation time 151476247 ps
CPU time 1.12 seconds
Started Jul 16 04:55:22 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 196696 kb
Host smart-d209dd72-20f7-4ca8-8fea-438d38219371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106708126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1106708126
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3957600728
Short name T605
Test name
Test status
Simulation time 42869740 ps
CPU time 1.72 seconds
Started Jul 16 04:55:32 PM PDT 24
Finished Jul 16 04:55:34 PM PDT 24
Peak memory 197376 kb
Host smart-7d4ac112-ddc7-40ea-bc2d-cbfb6096cf81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957600728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3957600728
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2193304839
Short name T482
Test name
Test status
Simulation time 127189032 ps
CPU time 2.34 seconds
Started Jul 16 04:55:23 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 196348 kb
Host smart-5e3531dc-4de4-4aa0-aa52-dae71e1cfbbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193304839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2193304839
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.344315941
Short name T438
Test name
Test status
Simulation time 98665784 ps
CPU time 0.75 seconds
Started Jul 16 04:55:10 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 195876 kb
Host smart-ab6d99c9-51a5-445b-bf9a-2412411b8df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344315941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.344315941
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1942777177
Short name T454
Test name
Test status
Simulation time 20558859 ps
CPU time 0.67 seconds
Started Jul 16 04:55:22 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 194876 kb
Host smart-4518a8b7-97bc-4082-8c24-56446af85dca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942777177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1942777177
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2115955403
Short name T651
Test name
Test status
Simulation time 60288217 ps
CPU time 3.13 seconds
Started Jul 16 04:55:29 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 198480 kb
Host smart-1cb70d39-30fd-40b9-a467-304739d4e2b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115955403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2115955403
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.413016211
Short name T587
Test name
Test status
Simulation time 125220984 ps
CPU time 0.86 seconds
Started Jul 16 04:55:37 PM PDT 24
Finished Jul 16 04:55:39 PM PDT 24
Peak memory 195876 kb
Host smart-4fb7dd9c-062d-4f85-980c-538100b5a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413016211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.413016211
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4286748670
Short name T386
Test name
Test status
Simulation time 577268998 ps
CPU time 1.12 seconds
Started Jul 16 04:55:28 PM PDT 24
Finished Jul 16 04:55:30 PM PDT 24
Peak memory 196076 kb
Host smart-14a7ad64-3601-47a5-a169-a3cf80043f16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286748670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4286748670
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2110620103
Short name T700
Test name
Test status
Simulation time 3579099807 ps
CPU time 42.85 seconds
Started Jul 16 04:55:21 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 198568 kb
Host smart-005b0b96-5420-41a8-801e-65f30592bd1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110620103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2110620103
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1142409522
Short name T68
Test name
Test status
Simulation time 65897904 ps
CPU time 0.57 seconds
Started Jul 16 04:55:24 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 194524 kb
Host smart-633f0887-d6da-4824-9599-258dc23c5eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142409522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1142409522
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.861226087
Short name T564
Test name
Test status
Simulation time 748889196 ps
CPU time 0.95 seconds
Started Jul 16 04:55:20 PM PDT 24
Finished Jul 16 04:55:22 PM PDT 24
Peak memory 196428 kb
Host smart-7be41051-e24f-4f44-9099-adbfd758cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861226087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.861226087
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3132008330
Short name T79
Test name
Test status
Simulation time 734386148 ps
CPU time 21.85 seconds
Started Jul 16 04:55:14 PM PDT 24
Finished Jul 16 04:55:36 PM PDT 24
Peak memory 197480 kb
Host smart-2ba8670c-95b6-4294-bc44-14a08bebb4c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132008330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3132008330
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.218019521
Short name T133
Test name
Test status
Simulation time 92478756 ps
CPU time 0.87 seconds
Started Jul 16 04:55:29 PM PDT 24
Finished Jul 16 04:55:31 PM PDT 24
Peak memory 197176 kb
Host smart-d7e304bc-e942-4124-baa6-6e3aa78a7474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218019521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.218019521
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.376739033
Short name T211
Test name
Test status
Simulation time 93332430 ps
CPU time 0.94 seconds
Started Jul 16 04:55:26 PM PDT 24
Finished Jul 16 04:55:27 PM PDT 24
Peak memory 197276 kb
Host smart-f41947fe-38ab-4e13-a8bf-c7b88aacb038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376739033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.376739033
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3060559814
Short name T277
Test name
Test status
Simulation time 135162254 ps
CPU time 2.07 seconds
Started Jul 16 04:55:20 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 198592 kb
Host smart-ba786ee5-5d01-4000-800c-0d3bbeeaf988
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060559814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3060559814
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3257822968
Short name T231
Test name
Test status
Simulation time 43130087 ps
CPU time 1.29 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 196596 kb
Host smart-b47da49c-d61c-4d23-81b3-00f1ac84bb8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257822968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3257822968
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3632355719
Short name T501
Test name
Test status
Simulation time 28110016 ps
CPU time 0.96 seconds
Started Jul 16 04:55:08 PM PDT 24
Finished Jul 16 04:55:12 PM PDT 24
Peak memory 197064 kb
Host smart-1d3812bd-4163-4f6a-9a7f-ea45fdc4caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632355719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3632355719
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2997323814
Short name T420
Test name
Test status
Simulation time 18403667 ps
CPU time 0.72 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 195888 kb
Host smart-35ea9ddc-f75c-44b0-880f-dfbe78566a41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997323814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2997323814
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3128651190
Short name T13
Test name
Test status
Simulation time 1943011855 ps
CPU time 5.69 seconds
Started Jul 16 04:55:34 PM PDT 24
Finished Jul 16 04:55:41 PM PDT 24
Peak memory 198576 kb
Host smart-8c875fc4-ef9d-493c-98e6-f14c266af28a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128651190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3128651190
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.218690935
Short name T184
Test name
Test status
Simulation time 241658012 ps
CPU time 1.19 seconds
Started Jul 16 04:55:16 PM PDT 24
Finished Jul 16 04:55:18 PM PDT 24
Peak memory 198556 kb
Host smart-e93afdef-6cee-461a-a132-ea81cc504cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218690935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.218690935
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.611535680
Short name T569
Test name
Test status
Simulation time 124165855 ps
CPU time 1.09 seconds
Started Jul 16 04:55:24 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 197372 kb
Host smart-2181c100-3042-4751-97b0-ac91a63385c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611535680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.611535680
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.712620869
Short name T527
Test name
Test status
Simulation time 11445202921 ps
CPU time 75.22 seconds
Started Jul 16 04:55:21 PM PDT 24
Finished Jul 16 04:56:37 PM PDT 24
Peak memory 198656 kb
Host smart-ae9defcc-58bb-44f2-a542-49b54bdb9a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712620869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.712620869
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4284155331
Short name T688
Test name
Test status
Simulation time 15344930 ps
CPU time 0.58 seconds
Started Jul 16 04:55:24 PM PDT 24
Finished Jul 16 04:55:25 PM PDT 24
Peak memory 195220 kb
Host smart-dbde62aa-c2f7-4730-b5a8-abe1e0dc1528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284155331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4284155331
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.107889248
Short name T150
Test name
Test status
Simulation time 413175483 ps
CPU time 0.77 seconds
Started Jul 16 04:55:27 PM PDT 24
Finished Jul 16 04:55:29 PM PDT 24
Peak memory 195736 kb
Host smart-87fac716-9bb9-4d09-aab7-af9d9110af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107889248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.107889248
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2738401229
Short name T484
Test name
Test status
Simulation time 3557550565 ps
CPU time 23.7 seconds
Started Jul 16 04:55:33 PM PDT 24
Finished Jul 16 04:55:57 PM PDT 24
Peak memory 197464 kb
Host smart-e889ba34-bfac-42b4-bb56-ff097b8dc8e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738401229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2738401229
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.4269913582
Short name T551
Test name
Test status
Simulation time 186943529 ps
CPU time 0.81 seconds
Started Jul 16 04:55:28 PM PDT 24
Finished Jul 16 04:55:30 PM PDT 24
Peak memory 196376 kb
Host smart-09e0f1f8-1041-4118-817e-56c4fb813624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269913582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4269913582
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1817636175
Short name T173
Test name
Test status
Simulation time 205293310 ps
CPU time 1.3 seconds
Started Jul 16 04:55:20 PM PDT 24
Finished Jul 16 04:55:22 PM PDT 24
Peak memory 197716 kb
Host smart-dd398d76-59b6-41a5-898a-0f6092895657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817636175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1817636175
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2643101245
Short name T634
Test name
Test status
Simulation time 71776818 ps
CPU time 1.44 seconds
Started Jul 16 04:55:21 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 197248 kb
Host smart-93b55ce9-11ac-422a-8011-cd743ea6d4ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643101245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2643101245
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.960831263
Short name T12
Test name
Test status
Simulation time 609468995 ps
CPU time 3.15 seconds
Started Jul 16 04:55:16 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 196992 kb
Host smart-d42f100f-b30e-4205-b643-fb1bb8eeef20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960831263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
960831263
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.646860611
Short name T565
Test name
Test status
Simulation time 289043490 ps
CPU time 1.24 seconds
Started Jul 16 04:55:28 PM PDT 24
Finished Jul 16 04:55:30 PM PDT 24
Peak memory 197468 kb
Host smart-be11be35-57da-4abe-a4c3-043dfbe111b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646860611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.646860611
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1303507276
Short name T507
Test name
Test status
Simulation time 42140049 ps
CPU time 0.87 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 196468 kb
Host smart-bff77046-3352-4a62-9186-54dd52e35d04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303507276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1303507276
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4062563759
Short name T487
Test name
Test status
Simulation time 508016771 ps
CPU time 2 seconds
Started Jul 16 04:55:18 PM PDT 24
Finished Jul 16 04:55:21 PM PDT 24
Peak memory 198468 kb
Host smart-b354e220-5373-4649-9271-4fb4383d099b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062563759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4062563759
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.171946770
Short name T249
Test name
Test status
Simulation time 66705991 ps
CPU time 1.16 seconds
Started Jul 16 04:55:21 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 196244 kb
Host smart-0fa0ca5a-7e5b-4f4f-bd92-f416648fb9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171946770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.171946770
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1495152775
Short name T455
Test name
Test status
Simulation time 53122243 ps
CPU time 1.11 seconds
Started Jul 16 04:55:29 PM PDT 24
Finished Jul 16 04:55:31 PM PDT 24
Peak memory 196404 kb
Host smart-d6c894e7-6553-41fa-96a0-89de6f1708b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495152775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1495152775
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2404503752
Short name T4
Test name
Test status
Simulation time 17163977399 ps
CPU time 88.52 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 04:57:05 PM PDT 24
Peak memory 198572 kb
Host smart-efee80a9-899b-4361-a6bc-9f4785214131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404503752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2404503752
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3926052119
Short name T267
Test name
Test status
Simulation time 15297642 ps
CPU time 0.61 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 194744 kb
Host smart-7951eb85-a405-4207-993f-aedf61c7d4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926052119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3926052119
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.532544830
Short name T571
Test name
Test status
Simulation time 42688365 ps
CPU time 0.64 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 194524 kb
Host smart-78ecc13a-c721-4325-9b1b-7114151a712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532544830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.532544830
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2277818249
Short name T393
Test name
Test status
Simulation time 1062260548 ps
CPU time 17.79 seconds
Started Jul 16 04:55:19 PM PDT 24
Finished Jul 16 04:55:37 PM PDT 24
Peak memory 198476 kb
Host smart-472a0e1a-0108-4085-8e88-f7a46da9cfdc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277818249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2277818249
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2536780228
Short name T390
Test name
Test status
Simulation time 76034350 ps
CPU time 1.07 seconds
Started Jul 16 04:55:33 PM PDT 24
Finished Jul 16 04:55:35 PM PDT 24
Peak memory 197312 kb
Host smart-79b07585-c8dd-4426-b332-4fa3b089bbfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536780228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2536780228
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.247648315
Short name T318
Test name
Test status
Simulation time 291309267 ps
CPU time 1.24 seconds
Started Jul 16 04:55:18 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 196328 kb
Host smart-be587b77-97bd-4f52-b0c4-1481ee7231af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247648315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.247648315
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3059705760
Short name T513
Test name
Test status
Simulation time 41184422 ps
CPU time 1.53 seconds
Started Jul 16 04:55:18 PM PDT 24
Finished Jul 16 04:55:21 PM PDT 24
Peak memory 197396 kb
Host smart-caa17578-1a4e-4213-a687-e4ec10e982af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059705760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3059705760
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1963510905
Short name T472
Test name
Test status
Simulation time 252906152 ps
CPU time 3.56 seconds
Started Jul 16 04:55:22 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 197668 kb
Host smart-024536f9-afc7-475f-bad2-d59720a74913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963510905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1963510905
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.527147380
Short name T270
Test name
Test status
Simulation time 54618360 ps
CPU time 1.18 seconds
Started Jul 16 04:55:18 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 196436 kb
Host smart-a4e67700-5284-4292-8e4c-d5262bbeda4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527147380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.527147380
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1554258122
Short name T363
Test name
Test status
Simulation time 32310572 ps
CPU time 1.18 seconds
Started Jul 16 04:55:23 PM PDT 24
Finished Jul 16 04:55:24 PM PDT 24
Peak memory 197764 kb
Host smart-124fef6e-f2ed-4d40-8b78-e41d36818926
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554258122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1554258122
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1004225176
Short name T381
Test name
Test status
Simulation time 3318989943 ps
CPU time 4.24 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:50 PM PDT 24
Peak memory 198540 kb
Host smart-a189df15-fe8c-4e2b-b7c1-e0b980c46c36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004225176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1004225176
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3683575390
Short name T361
Test name
Test status
Simulation time 114696004 ps
CPU time 1.17 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 196860 kb
Host smart-321cb64b-6837-4c5e-b546-516b5fdb0b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683575390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3683575390
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.530430940
Short name T338
Test name
Test status
Simulation time 492290376 ps
CPU time 1.32 seconds
Started Jul 16 04:55:24 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 196164 kb
Host smart-7ff75762-93ff-42bf-9276-fc9e59acd4df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530430940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.530430940
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2606659885
Short name T175
Test name
Test status
Simulation time 30322298515 ps
CPU time 177.04 seconds
Started Jul 16 04:55:48 PM PDT 24
Finished Jul 16 04:58:46 PM PDT 24
Peak memory 198600 kb
Host smart-aec7d77b-3eff-4d7d-9083-787fd300085f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606659885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2606659885
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2839570717
Short name T699
Test name
Test status
Simulation time 78806280 ps
CPU time 0.57 seconds
Started Jul 16 04:55:26 PM PDT 24
Finished Jul 16 04:55:27 PM PDT 24
Peak memory 194580 kb
Host smart-33401597-231e-4af6-a64f-8966338f823a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839570717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2839570717
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1736256272
Short name T435
Test name
Test status
Simulation time 28902810 ps
CPU time 0.87 seconds
Started Jul 16 04:55:28 PM PDT 24
Finished Jul 16 04:55:29 PM PDT 24
Peak memory 196240 kb
Host smart-d11523eb-7231-4db4-ba3c-28e29d694d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736256272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1736256272
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3114305266
Short name T210
Test name
Test status
Simulation time 2424041813 ps
CPU time 22.33 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:54 PM PDT 24
Peak memory 197472 kb
Host smart-07c86d9b-df12-4a53-bb90-111029007243
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114305266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3114305266
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2066157734
Short name T6
Test name
Test status
Simulation time 84752515 ps
CPU time 1.1 seconds
Started Jul 16 04:55:29 PM PDT 24
Finished Jul 16 04:55:31 PM PDT 24
Peak memory 197236 kb
Host smart-5300c3b7-89da-47b4-af97-dee787a987c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066157734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2066157734
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.380576923
Short name T468
Test name
Test status
Simulation time 23395939 ps
CPU time 0.77 seconds
Started Jul 16 04:55:30 PM PDT 24
Finished Jul 16 04:55:31 PM PDT 24
Peak memory 195556 kb
Host smart-6df581ff-799d-4233-b08d-b2a94c2936a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380576923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.380576923
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1973407422
Short name T428
Test name
Test status
Simulation time 371465935 ps
CPU time 1.1 seconds
Started Jul 16 04:55:14 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 197928 kb
Host smart-5a08c8ab-279b-4982-ac0f-296764608e70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973407422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1973407422
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.224241799
Short name T198
Test name
Test status
Simulation time 142394426 ps
CPU time 3.11 seconds
Started Jul 16 04:55:28 PM PDT 24
Finished Jul 16 04:55:32 PM PDT 24
Peak memory 197572 kb
Host smart-19ab8209-6eb5-45f9-84a6-2aeefa9c11d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224241799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
224241799
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.654263196
Short name T366
Test name
Test status
Simulation time 174890778 ps
CPU time 0.8 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 195888 kb
Host smart-c4a397f9-3aff-45ad-90d4-bf95acef6ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654263196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.654263196
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3574509209
Short name T708
Test name
Test status
Simulation time 221595908 ps
CPU time 1.34 seconds
Started Jul 16 04:55:25 PM PDT 24
Finished Jul 16 04:55:27 PM PDT 24
Peak memory 198588 kb
Host smart-12f7f4c8-cf74-4851-aacb-14b10398e455
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574509209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3574509209
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2786313655
Short name T629
Test name
Test status
Simulation time 370306029 ps
CPU time 4.36 seconds
Started Jul 16 04:55:21 PM PDT 24
Finished Jul 16 04:55:26 PM PDT 24
Peak memory 198380 kb
Host smart-335d36c2-5fb2-4b8a-8bba-3e59c83cfd0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786313655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2786313655
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1018795520
Short name T597
Test name
Test status
Simulation time 95427134 ps
CPU time 1.03 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:19 PM PDT 24
Peak memory 196344 kb
Host smart-cbaa3671-65be-45c2-9ee6-c97100bc94b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018795520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1018795520
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.63027137
Short name T274
Test name
Test status
Simulation time 115592406 ps
CPU time 1.05 seconds
Started Jul 16 04:55:25 PM PDT 24
Finished Jul 16 04:55:27 PM PDT 24
Peak memory 196336 kb
Host smart-a6e173a5-5b23-42ac-ba31-8371a8bfca18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63027137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.63027137
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2763085857
Short name T491
Test name
Test status
Simulation time 50234211209 ps
CPU time 157.5 seconds
Started Jul 16 04:55:40 PM PDT 24
Finished Jul 16 04:58:18 PM PDT 24
Peak memory 198580 kb
Host smart-48078445-0afb-42b7-a4e9-c60ef6e88ade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763085857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2763085857
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3361075199
Short name T696
Test name
Test status
Simulation time 24688940 ps
CPU time 0.58 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 194436 kb
Host smart-4bc297d1-f978-4812-9df8-f9a1927db695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361075199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3361075199
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3719561772
Short name T534
Test name
Test status
Simulation time 81678388 ps
CPU time 0.85 seconds
Started Jul 16 04:55:35 PM PDT 24
Finished Jul 16 04:55:37 PM PDT 24
Peak memory 197636 kb
Host smart-c7eb6543-fa35-4aee-8bab-f2b791702c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719561772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3719561772
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_full_random.1498084415
Short name T467
Test name
Test status
Simulation time 48066919 ps
CPU time 0.77 seconds
Started Jul 16 04:55:38 PM PDT 24
Finished Jul 16 04:55:40 PM PDT 24
Peak memory 196388 kb
Host smart-c9a79d77-f3db-4aa8-a843-16916d2e180a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498084415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1498084415
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.867398400
Short name T369
Test name
Test status
Simulation time 103929928 ps
CPU time 1.37 seconds
Started Jul 16 04:55:34 PM PDT 24
Finished Jul 16 04:55:36 PM PDT 24
Peak memory 198520 kb
Host smart-3dee79f4-ec47-4134-8f6e-3f5ecce56dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867398400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.867398400
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2686292564
Short name T132
Test name
Test status
Simulation time 99442161 ps
CPU time 1.93 seconds
Started Jul 16 04:55:20 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 196804 kb
Host smart-fc25f6d2-0c13-4681-b5c1-13463d9060e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686292564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2686292564
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2425362229
Short name T583
Test name
Test status
Simulation time 96772756 ps
CPU time 2.79 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 197620 kb
Host smart-c4121709-0fe2-4114-b892-455a8970fc50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425362229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2425362229
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2739567616
Short name T187
Test name
Test status
Simulation time 294893449 ps
CPU time 1.18 seconds
Started Jul 16 04:55:13 PM PDT 24
Finished Jul 16 04:55:15 PM PDT 24
Peak memory 198560 kb
Host smart-ed9b31d3-b214-4ccf-a2a5-48c546e1767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739567616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2739567616
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3784734525
Short name T77
Test name
Test status
Simulation time 19855864 ps
CPU time 0.81 seconds
Started Jul 16 04:55:13 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 197132 kb
Host smart-49cd22fb-a023-48db-aa2f-75a4a9f002e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784734525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3784734525
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3825906785
Short name T16
Test name
Test status
Simulation time 78456633 ps
CPU time 3.49 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:45 PM PDT 24
Peak memory 198368 kb
Host smart-660eaf75-e668-4fb8-b71d-27be46d6e075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825906785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3825906785
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1379828731
Short name T244
Test name
Test status
Simulation time 229121352 ps
CPU time 1.27 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 197048 kb
Host smart-4b12594c-6182-4283-919d-596f49ad254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379828731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1379828731
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.841959161
Short name T120
Test name
Test status
Simulation time 43932874 ps
CPU time 1.28 seconds
Started Jul 16 04:55:17 PM PDT 24
Finished Jul 16 04:55:20 PM PDT 24
Peak memory 197480 kb
Host smart-4f8240a0-4492-4d3e-b7f5-7e287c5dc512
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841959161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.841959161
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1647150629
Short name T421
Test name
Test status
Simulation time 24751344459 ps
CPU time 83.98 seconds
Started Jul 16 04:55:29 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 198556 kb
Host smart-bcaff9a7-b060-48c9-91a5-def15390fd77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647150629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1647150629
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3634532519
Short name T610
Test name
Test status
Simulation time 499600668515 ps
CPU time 1385.54 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 05:18:48 PM PDT 24
Peak memory 198748 kb
Host smart-e81cd9ca-3dd9-4e4c-98ba-c905a9d1b4ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3634532519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3634532519
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.999254466
Short name T45
Test name
Test status
Simulation time 176811641 ps
CPU time 0.57 seconds
Started Jul 16 04:55:40 PM PDT 24
Finished Jul 16 04:55:42 PM PDT 24
Peak memory 194616 kb
Host smart-e4b63c1e-34ad-4681-b509-9df1b126cd48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999254466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.999254466
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.444126201
Short name T291
Test name
Test status
Simulation time 209362134 ps
CPU time 0.63 seconds
Started Jul 16 04:55:35 PM PDT 24
Finished Jul 16 04:55:36 PM PDT 24
Peak memory 194596 kb
Host smart-267a807b-5bae-40fb-a5c3-25ca1f0db085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444126201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.444126201
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.543672714
Short name T307
Test name
Test status
Simulation time 630098839 ps
CPU time 9.1 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 197356 kb
Host smart-a8cce626-5b01-4f33-8189-68b139db8a3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543672714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.543672714
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.460522125
Short name T309
Test name
Test status
Simulation time 20529010 ps
CPU time 0.64 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 04:55:38 PM PDT 24
Peak memory 195680 kb
Host smart-ab5621e3-3944-412f-96c4-bf7faf7fb3ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460522125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.460522125
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1979566212
Short name T261
Test name
Test status
Simulation time 178061508 ps
CPU time 1.27 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 196772 kb
Host smart-0fb8fb68-ad8c-418d-a859-82764d80ef6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979566212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1979566212
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1666494935
Short name T479
Test name
Test status
Simulation time 77805868 ps
CPU time 0.89 seconds
Started Jul 16 04:55:34 PM PDT 24
Finished Jul 16 04:55:36 PM PDT 24
Peak memory 196744 kb
Host smart-fb43b500-7e5c-4934-a7e7-5b222bd40901
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666494935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1666494935
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2346819074
Short name T493
Test name
Test status
Simulation time 58118937 ps
CPU time 1.21 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 04:55:38 PM PDT 24
Peak memory 197120 kb
Host smart-84be3587-ed8f-41f5-b46d-ff94d1a2ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346819074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2346819074
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2374897674
Short name T429
Test name
Test status
Simulation time 17268554 ps
CPU time 0.75 seconds
Started Jul 16 04:55:49 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 195884 kb
Host smart-3a92a33a-18d5-47c4-a6f1-d4e0f30a732f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374897674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2374897674
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1477091481
Short name T631
Test name
Test status
Simulation time 1330980180 ps
CPU time 5.73 seconds
Started Jul 16 04:55:37 PM PDT 24
Finished Jul 16 04:55:43 PM PDT 24
Peak memory 198456 kb
Host smart-0298db94-5de2-4817-9fca-dcecab85c2fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477091481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1477091481
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2888117352
Short name T349
Test name
Test status
Simulation time 138692360 ps
CPU time 0.98 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:43 PM PDT 24
Peak memory 196280 kb
Host smart-cf5565db-f6aa-4cd1-a40c-e5d8e69cabc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888117352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2888117352
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4108021901
Short name T232
Test name
Test status
Simulation time 406695624 ps
CPU time 1.19 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:48 PM PDT 24
Peak memory 197112 kb
Host smart-667055b6-1d09-44fe-99f6-f9645f320e77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108021901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4108021901
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.684042871
Short name T364
Test name
Test status
Simulation time 28008781521 ps
CPU time 65.54 seconds
Started Jul 16 04:55:48 PM PDT 24
Finished Jul 16 04:56:55 PM PDT 24
Peak memory 198516 kb
Host smart-fd71b9c0-3a00-4a46-9b7a-a4e150e2cebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684042871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.684042871
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1081541193
Short name T180
Test name
Test status
Simulation time 44083680 ps
CPU time 0.58 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:43 PM PDT 24
Peak memory 195404 kb
Host smart-f7d76747-db4c-4d7c-a86c-bbf8ed785fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081541193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1081541193
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1551834873
Short name T712
Test name
Test status
Simulation time 44121983 ps
CPU time 0.89 seconds
Started Jul 16 04:55:43 PM PDT 24
Finished Jul 16 04:55:45 PM PDT 24
Peak memory 196320 kb
Host smart-4f917f30-7ae2-473e-b7a0-f5c0987e319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551834873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1551834873
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2471341163
Short name T662
Test name
Test status
Simulation time 594860473 ps
CPU time 14.53 seconds
Started Jul 16 04:55:42 PM PDT 24
Finished Jul 16 04:55:57 PM PDT 24
Peak memory 196764 kb
Host smart-cd7bdaed-2a81-4cf6-b3f7-bb8588ffbe51
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471341163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2471341163
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3059041927
Short name T424
Test name
Test status
Simulation time 210922579 ps
CPU time 0.85 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:47 PM PDT 24
Peak memory 196588 kb
Host smart-781ba91c-40c9-4a8a-96d0-b6c4880d1a73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059041927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3059041927
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2119132251
Short name T462
Test name
Test status
Simulation time 66792930 ps
CPU time 1.17 seconds
Started Jul 16 04:55:35 PM PDT 24
Finished Jul 16 04:55:36 PM PDT 24
Peak memory 196740 kb
Host smart-21abaa6c-d50d-4803-99b8-bfbc5dbfb6d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119132251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2119132251
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1061017158
Short name T138
Test name
Test status
Simulation time 86512295 ps
CPU time 2.74 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:45 PM PDT 24
Peak memory 198572 kb
Host smart-499427fb-a1ec-4d7b-9fb5-96879c4bd117
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061017158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1061017158
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.487906630
Short name T612
Test name
Test status
Simulation time 133186102 ps
CPU time 1.58 seconds
Started Jul 16 04:55:34 PM PDT 24
Finished Jul 16 04:55:36 PM PDT 24
Peak memory 196964 kb
Host smart-b2e3e5d9-bab9-43f1-a6b1-12a7ef5d6b36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487906630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
487906630
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1418226975
Short name T346
Test name
Test status
Simulation time 20385166 ps
CPU time 0.74 seconds
Started Jul 16 04:55:33 PM PDT 24
Finished Jul 16 04:55:34 PM PDT 24
Peak memory 194684 kb
Host smart-6b1c4a45-2968-4be1-847b-7b74f8febfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418226975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1418226975
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1703242950
Short name T525
Test name
Test status
Simulation time 190711594 ps
CPU time 1.08 seconds
Started Jul 16 04:55:40 PM PDT 24
Finished Jul 16 04:55:42 PM PDT 24
Peak memory 196484 kb
Host smart-89f06648-6cac-4c96-a717-4a551478efc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703242950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1703242950
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1468238438
Short name T269
Test name
Test status
Simulation time 1052751453 ps
CPU time 4.57 seconds
Started Jul 16 04:55:41 PM PDT 24
Finished Jul 16 04:55:47 PM PDT 24
Peak memory 198416 kb
Host smart-8b8ec156-ad4b-49e9-a1ea-80fe211f61c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468238438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1468238438
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.42466241
Short name T654
Test name
Test status
Simulation time 304656946 ps
CPU time 1.27 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:47 PM PDT 24
Peak memory 197368 kb
Host smart-7a508d8f-f297-498d-85b9-cbec9af28836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42466241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.42466241
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2200396221
Short name T322
Test name
Test status
Simulation time 53452859 ps
CPU time 1.19 seconds
Started Jul 16 04:55:37 PM PDT 24
Finished Jul 16 04:55:39 PM PDT 24
Peak memory 196100 kb
Host smart-45eb5f3f-e96c-4d98-bfca-abcf7c670964
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200396221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2200396221
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2111658588
Short name T439
Test name
Test status
Simulation time 41664007450 ps
CPU time 147 seconds
Started Jul 16 04:55:34 PM PDT 24
Finished Jul 16 04:58:02 PM PDT 24
Peak memory 198756 kb
Host smart-6020a1e5-b36e-47d2-b8de-437d9f8da440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111658588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2111658588
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.970484275
Short name T158
Test name
Test status
Simulation time 45429351 ps
CPU time 0.64 seconds
Started Jul 16 04:55:33 PM PDT 24
Finished Jul 16 04:55:34 PM PDT 24
Peak memory 195408 kb
Host smart-1aa491ab-bb77-4b4c-afa3-f01bbb55b45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970484275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.970484275
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3871715957
Short name T370
Test name
Test status
Simulation time 79401608 ps
CPU time 0.83 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 04:55:38 PM PDT 24
Peak memory 195788 kb
Host smart-f52e84cc-40cb-4caf-ba23-49b8c981a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871715957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3871715957
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2083206805
Short name T447
Test name
Test status
Simulation time 1973573495 ps
CPU time 16.7 seconds
Started Jul 16 04:55:42 PM PDT 24
Finished Jul 16 04:56:00 PM PDT 24
Peak memory 197368 kb
Host smart-7c248956-21b2-4f2d-8c17-44d62006beea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083206805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2083206805
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.886612406
Short name T400
Test name
Test status
Simulation time 135532521 ps
CPU time 0.99 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:46 PM PDT 24
Peak memory 197100 kb
Host smart-b65d80ad-d630-4900-9eda-54e0b77f0dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886612406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.886612406
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3374698320
Short name T560
Test name
Test status
Simulation time 94375505 ps
CPU time 1.33 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:56 PM PDT 24
Peak memory 196336 kb
Host smart-ca634aa9-5e5c-412a-9aa3-0ead7f4ffc6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374698320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3374698320
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2359520194
Short name T155
Test name
Test status
Simulation time 60870510 ps
CPU time 2.14 seconds
Started Jul 16 04:55:32 PM PDT 24
Finished Jul 16 04:55:35 PM PDT 24
Peak memory 198548 kb
Host smart-bcffeb3b-7568-4447-8c13-231e6f399c8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359520194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2359520194
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3097263224
Short name T646
Test name
Test status
Simulation time 132458552 ps
CPU time 2.95 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:54 PM PDT 24
Peak memory 198704 kb
Host smart-8dd640af-96c1-44a3-bc7a-c142e058ebcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097263224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3097263224
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.780351325
Short name T169
Test name
Test status
Simulation time 268093702 ps
CPU time 0.7 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:45 PM PDT 24
Peak memory 195412 kb
Host smart-b118a88d-44b0-41b0-943e-9baa4666a983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780351325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.780351325
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3172204941
Short name T183
Test name
Test status
Simulation time 76723183 ps
CPU time 1.04 seconds
Started Jul 16 04:55:39 PM PDT 24
Finished Jul 16 04:55:41 PM PDT 24
Peak memory 196512 kb
Host smart-a2359b81-c50e-4b6d-971f-2ac38feb59bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172204941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3172204941
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3899266100
Short name T480
Test name
Test status
Simulation time 123132252 ps
CPU time 5.46 seconds
Started Jul 16 04:55:42 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 198464 kb
Host smart-809acabe-2011-4829-9b4d-3cad823c011a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899266100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3899266100
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.295136035
Short name T200
Test name
Test status
Simulation time 258103489 ps
CPU time 1.22 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:46 PM PDT 24
Peak memory 196828 kb
Host smart-fcacbe78-7b91-4633-82ed-892632b0dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295136035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.295136035
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3328288633
Short name T405
Test name
Test status
Simulation time 98507537 ps
CPU time 1.58 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 196808 kb
Host smart-43792250-56f4-4fb3-ad60-b5567e260957
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328288633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3328288633
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3192454673
Short name T359
Test name
Test status
Simulation time 159499354716 ps
CPU time 176.94 seconds
Started Jul 16 04:55:32 PM PDT 24
Finished Jul 16 04:58:30 PM PDT 24
Peak memory 198640 kb
Host smart-c3684be9-0a04-4ee8-953b-dde872d3c57b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192454673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3192454673
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2074560908
Short name T35
Test name
Test status
Simulation time 249846710685 ps
CPU time 2432.77 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 05:36:10 PM PDT 24
Peak memory 198808 kb
Host smart-0b9c291f-0f9c-442a-baa4-066be2a1b1e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2074560908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2074560908
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1517845646
Short name T431
Test name
Test status
Simulation time 15450770 ps
CPU time 0.57 seconds
Started Jul 16 04:55:37 PM PDT 24
Finished Jul 16 04:55:38 PM PDT 24
Peak memory 194728 kb
Host smart-fdd72484-daa2-4b2a-aee5-1b9ebad54fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517845646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1517845646
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.424473867
Short name T530
Test name
Test status
Simulation time 26889778 ps
CPU time 0.85 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 196692 kb
Host smart-cd9d6838-38f0-43c0-9e25-8840beacbb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424473867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.424473867
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.835232798
Short name T521
Test name
Test status
Simulation time 2729997635 ps
CPU time 17.18 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:56:12 PM PDT 24
Peak memory 197512 kb
Host smart-6e007959-b518-4a63-9b16-2632c8be142f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835232798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.835232798
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.177680555
Short name T182
Test name
Test status
Simulation time 557318209 ps
CPU time 1.14 seconds
Started Jul 16 04:55:31 PM PDT 24
Finished Jul 16 04:55:33 PM PDT 24
Peak memory 196912 kb
Host smart-e2ca7827-16e0-4b2f-8fd6-d13e57b9d275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177680555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.177680555
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.437477069
Short name T298
Test name
Test status
Simulation time 128343145 ps
CPU time 0.96 seconds
Started Jul 16 04:55:37 PM PDT 24
Finished Jul 16 04:55:39 PM PDT 24
Peak memory 196516 kb
Host smart-dbb60de8-8b73-407c-8be8-933112444a03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437477069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.437477069
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.69649093
Short name T259
Test name
Test status
Simulation time 220236594 ps
CPU time 2.49 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 04:55:40 PM PDT 24
Peak memory 198648 kb
Host smart-4c2cfc54-96a5-4bd3-92fe-92491fab30af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69649093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.gpio_intr_with_filter_rand_intr_event.69649093
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1253351329
Short name T172
Test name
Test status
Simulation time 153895181 ps
CPU time 2.27 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 197780 kb
Host smart-a2c98b78-efae-4ce8-8965-6686052e97e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253351329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1253351329
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3303807928
Short name T166
Test name
Test status
Simulation time 135026694 ps
CPU time 1.26 seconds
Started Jul 16 04:55:36 PM PDT 24
Finished Jul 16 04:55:38 PM PDT 24
Peak memory 197440 kb
Host smart-e6cceb53-e635-4730-a5f5-31e108b5cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303807928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3303807928
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1352463863
Short name T205
Test name
Test status
Simulation time 92501287 ps
CPU time 0.98 seconds
Started Jul 16 04:55:43 PM PDT 24
Finished Jul 16 04:55:45 PM PDT 24
Peak memory 196420 kb
Host smart-f939cdcc-c4db-46de-a3a6-e1d38ee25ee5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352463863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1352463863
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3082435694
Short name T532
Test name
Test status
Simulation time 312070867 ps
CPU time 3.44 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:50 PM PDT 24
Peak memory 198480 kb
Host smart-c1883d17-3a38-433f-8515-30b02f8596fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082435694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3082435694
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.555631385
Short name T72
Test name
Test status
Simulation time 334096261 ps
CPU time 0.83 seconds
Started Jul 16 04:55:40 PM PDT 24
Finished Jul 16 04:55:42 PM PDT 24
Peak memory 195884 kb
Host smart-eb34ad70-e5b8-406e-8a87-44a2ed399528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555631385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.555631385
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4249976339
Short name T678
Test name
Test status
Simulation time 43031223 ps
CPU time 1.09 seconds
Started Jul 16 04:55:42 PM PDT 24
Finished Jul 16 04:55:44 PM PDT 24
Peak memory 196248 kb
Host smart-85e4b3b6-e9be-4ab6-aa4e-b35e2e8abad1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249976339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4249976339
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2583531642
Short name T402
Test name
Test status
Simulation time 1681735924 ps
CPU time 41.4 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:56:33 PM PDT 24
Peak memory 198520 kb
Host smart-1c383ad0-9d2b-40c6-bc24-b3ab562a15b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583531642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2583531642
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1949130668
Short name T76
Test name
Test status
Simulation time 51421026 ps
CPU time 0.56 seconds
Started Jul 16 04:54:47 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 194560 kb
Host smart-56c2d556-37a3-41ac-9f73-b1c60e996bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949130668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1949130668
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3595511808
Short name T353
Test name
Test status
Simulation time 27993600 ps
CPU time 0.85 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 195804 kb
Host smart-6b1e0e85-22e2-43a1-8c29-4072443f22a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595511808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3595511808
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3887613814
Short name T660
Test name
Test status
Simulation time 412431643 ps
CPU time 5.23 seconds
Started Jul 16 04:54:46 PM PDT 24
Finished Jul 16 04:54:53 PM PDT 24
Peak memory 197528 kb
Host smart-72946291-bbe1-48f6-9c14-2aecb773dbc5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887613814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3887613814
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3627577761
Short name T516
Test name
Test status
Simulation time 31032650 ps
CPU time 0.73 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 195268 kb
Host smart-8599e23b-527c-4211-b276-512f770dabf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627577761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3627577761
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2474423388
Short name T450
Test name
Test status
Simulation time 71131416 ps
CPU time 1.26 seconds
Started Jul 16 04:54:51 PM PDT 24
Finished Jul 16 04:54:53 PM PDT 24
Peak memory 198540 kb
Host smart-48dd813a-1361-48e8-be07-bdc70e4812a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474423388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2474423388
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4237739543
Short name T145
Test name
Test status
Simulation time 71647279 ps
CPU time 1.33 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 197252 kb
Host smart-1f9d36dc-5c7d-4cea-9a3a-b93ece779bfe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237739543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4237739543
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3458254400
Short name T21
Test name
Test status
Simulation time 179215647 ps
CPU time 1.2 seconds
Started Jul 16 04:55:01 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 196988 kb
Host smart-80cfde39-3ce9-4e61-b5ae-2b2edf38f4cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458254400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3458254400
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1206311634
Short name T416
Test name
Test status
Simulation time 235992927 ps
CPU time 1.35 seconds
Started Jul 16 04:54:48 PM PDT 24
Finished Jul 16 04:54:51 PM PDT 24
Peak memory 198500 kb
Host smart-c87dbb52-6c02-4f4a-8f3b-fcdf8ff0b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206311634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1206311634
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.274177918
Short name T149
Test name
Test status
Simulation time 34215233 ps
CPU time 1.15 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:56 PM PDT 24
Peak memory 197524 kb
Host smart-091491ca-8d68-403b-a68f-b0190481a7b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274177918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.274177918
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.444582081
Short name T395
Test name
Test status
Simulation time 220481827 ps
CPU time 4.63 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:18 PM PDT 24
Peak memory 198776 kb
Host smart-151b62a4-8901-48ef-9693-fe3561c9a0e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444582081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.444582081
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.964202349
Short name T230
Test name
Test status
Simulation time 46428719 ps
CPU time 1.41 seconds
Started Jul 16 04:54:48 PM PDT 24
Finished Jul 16 04:54:50 PM PDT 24
Peak memory 198488 kb
Host smart-bcd94747-c64f-4bd0-a759-2455465e5758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964202349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.964202349
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2872711800
Short name T412
Test name
Test status
Simulation time 177054696 ps
CPU time 1.04 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 196384 kb
Host smart-ee5fe63f-6a09-4737-b099-c26238d1a22a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872711800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2872711800
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2186657772
Short name T271
Test name
Test status
Simulation time 7373122822 ps
CPU time 95.34 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:56:35 PM PDT 24
Peak memory 198624 kb
Host smart-dd07cfa9-91c6-44e4-8afc-9b968df91895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186657772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2186657772
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3615113624
Short name T130
Test name
Test status
Simulation time 11895547 ps
CPU time 0.58 seconds
Started Jul 16 04:55:49 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 194440 kb
Host smart-629f227e-f771-44cc-ab35-5c4acee6ecc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615113624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3615113624
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2075208864
Short name T641
Test name
Test status
Simulation time 45649174 ps
CPU time 0.79 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 196452 kb
Host smart-a78403c1-9345-4eb3-8771-b539281493e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075208864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2075208864
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2692173938
Short name T59
Test name
Test status
Simulation time 1309777280 ps
CPU time 23.69 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:56:12 PM PDT 24
Peak memory 197516 kb
Host smart-21f203a8-ec1c-4a6a-b1c0-29013504c908
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692173938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2692173938
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1949941389
Short name T559
Test name
Test status
Simulation time 68504542 ps
CPU time 0.66 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:47 PM PDT 24
Peak memory 194924 kb
Host smart-354dc637-c586-4257-a4e1-4dfab55e6f9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949941389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1949941389
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.50667979
Short name T632
Test name
Test status
Simulation time 122757288 ps
CPU time 1.24 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 197224 kb
Host smart-f6457f98-0014-4766-b4db-0ab7ea931e7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50667979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.50667979
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.150447157
Short name T207
Test name
Test status
Simulation time 83853008 ps
CPU time 3.35 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 198588 kb
Host smart-7f6e9e2e-9512-4308-b21b-23da0cef2d1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150447157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.150447157
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.4051791118
Short name T256
Test name
Test status
Simulation time 449335668 ps
CPU time 2.72 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 198600 kb
Host smart-c54bd92f-5a50-4ed0-b6d6-d5d49a1355c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051791118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.4051791118
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1349370360
Short name T579
Test name
Test status
Simulation time 41288079 ps
CPU time 0.92 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 196508 kb
Host smart-0d4f049f-f042-4187-9122-4bf42cfe9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349370360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1349370360
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3202117659
Short name T552
Test name
Test status
Simulation time 32286349 ps
CPU time 0.82 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 196036 kb
Host smart-24f5b06c-c734-4fa7-8a15-a8d1492a9d7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202117659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3202117659
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.400078250
Short name T595
Test name
Test status
Simulation time 79484828 ps
CPU time 1.75 seconds
Started Jul 16 04:55:46 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 198476 kb
Host smart-b2a26535-e56d-4ab1-a3be-6c2ff34a090e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400078250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.400078250
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.586487321
Short name T345
Test name
Test status
Simulation time 70731096 ps
CPU time 1.08 seconds
Started Jul 16 04:55:42 PM PDT 24
Finished Jul 16 04:55:44 PM PDT 24
Peak memory 196092 kb
Host smart-c1514dc8-e67d-4879-8446-27a567736d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586487321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.586487321
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1368922331
Short name T433
Test name
Test status
Simulation time 341639667 ps
CPU time 0.9 seconds
Started Jul 16 04:55:46 PM PDT 24
Finished Jul 16 04:55:48 PM PDT 24
Peak memory 195844 kb
Host smart-0b3f50ba-f4df-4065-a435-db3da884297d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368922331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1368922331
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1374055665
Short name T621
Test name
Test status
Simulation time 62653055464 ps
CPU time 105.25 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:57:40 PM PDT 24
Peak memory 198608 kb
Host smart-9fdcb8d0-afaf-4530-a9a9-3762d2685a54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374055665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1374055665
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.66095708
Short name T620
Test name
Test status
Simulation time 33052941 ps
CPU time 0.58 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:55 PM PDT 24
Peak memory 194460 kb
Host smart-ad86d63d-4168-4060-83de-129664d27e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66095708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.66095708
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1811333633
Short name T319
Test name
Test status
Simulation time 58641546 ps
CPU time 0.74 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 195820 kb
Host smart-e97a0b6e-055c-46f9-9a84-c777930a81a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811333633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1811333633
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2164646472
Short name T648
Test name
Test status
Simulation time 346602580 ps
CPU time 5.75 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:56:00 PM PDT 24
Peak memory 196060 kb
Host smart-6709b39c-447c-475c-af38-c79218b06da6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164646472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2164646472
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3385919339
Short name T451
Test name
Test status
Simulation time 37386220 ps
CPU time 0.83 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:52 PM PDT 24
Peak memory 197280 kb
Host smart-dcc30452-1816-4d2c-b090-f77ab21051d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385919339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3385919339
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1091788687
Short name T215
Test name
Test status
Simulation time 49239364 ps
CPU time 0.83 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:55:59 PM PDT 24
Peak memory 195892 kb
Host smart-1416cd1c-67b9-40e7-b58e-a0dd6715ca68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091788687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1091788687
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.312006329
Short name T506
Test name
Test status
Simulation time 94180683 ps
CPU time 3.43 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 04:55:56 PM PDT 24
Peak memory 196824 kb
Host smart-c2d9d98f-f433-4fe9-bd41-c84d86d44d89
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312006329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.312006329
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.986420719
Short name T408
Test name
Test status
Simulation time 69195219 ps
CPU time 2.01 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 197044 kb
Host smart-a9cb3cf8-b2a0-4cbc-959d-4134ed6fd16c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986420719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
986420719
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1932951197
Short name T241
Test name
Test status
Simulation time 189054377 ps
CPU time 1.07 seconds
Started Jul 16 04:55:46 PM PDT 24
Finished Jul 16 04:55:48 PM PDT 24
Peak memory 197360 kb
Host smart-767cd5cf-70a6-4ebf-9e7b-55bf9c8f2991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932951197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1932951197
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2091633294
Short name T692
Test name
Test status
Simulation time 72236520 ps
CPU time 1.16 seconds
Started Jul 16 04:55:40 PM PDT 24
Finished Jul 16 04:55:42 PM PDT 24
Peak memory 197616 kb
Host smart-2890a40c-d54d-4ffb-adc2-b5b29f8e6b60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091633294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2091633294
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1318999810
Short name T194
Test name
Test status
Simulation time 70891026 ps
CPU time 1.37 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 198440 kb
Host smart-a364a1c9-8fda-442b-9232-9798b29d0257
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318999810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1318999810
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3281142356
Short name T305
Test name
Test status
Simulation time 166301808 ps
CPU time 1.12 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:47 PM PDT 24
Peak memory 196056 kb
Host smart-b3b92f43-02a2-41ed-b906-2cd78dd53300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281142356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3281142356
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2168277053
Short name T563
Test name
Test status
Simulation time 49652510 ps
CPU time 1.01 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 196924 kb
Host smart-e3117279-3f07-4fc0-9a2e-5a1d393f894f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168277053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2168277053
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3196334752
Short name T373
Test name
Test status
Simulation time 9274581144 ps
CPU time 98.5 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:57:37 PM PDT 24
Peak memory 198636 kb
Host smart-33d39d1c-52a2-406f-b17f-62eeb8b559bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196334752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3196334752
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2062522242
Short name T442
Test name
Test status
Simulation time 156004873937 ps
CPU time 454.11 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 05:03:25 PM PDT 24
Peak memory 198876 kb
Host smart-2fea593c-3fb7-4e7a-9766-5413df517d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2062522242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2062522242
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1091141526
Short name T443
Test name
Test status
Simulation time 23234471 ps
CPU time 0.59 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:48 PM PDT 24
Peak memory 195440 kb
Host smart-d33a2a2f-22fc-4b28-8199-4c51aa8fbd14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091141526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1091141526
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2928558716
Short name T557
Test name
Test status
Simulation time 59946562 ps
CPU time 0.65 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:56 PM PDT 24
Peak memory 195192 kb
Host smart-df66e155-fb3b-428f-9357-f17aa1e8b747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928558716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2928558716
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2933090634
Short name T693
Test name
Test status
Simulation time 248125668 ps
CPU time 6.55 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 197472 kb
Host smart-5fe97414-a0f6-45d4-8f14-48ec0ac7f616
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933090634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2933090634
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2775414570
Short name T498
Test name
Test status
Simulation time 33867393 ps
CPU time 0.7 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 195884 kb
Host smart-c1c772f5-4a55-42ac-af41-92bde2b66e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775414570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2775414570
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3005417367
Short name T475
Test name
Test status
Simulation time 196855121 ps
CPU time 0.8 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:56 PM PDT 24
Peak memory 196044 kb
Host smart-452f4096-7fab-461a-8d0b-c1b817b6e111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005417367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3005417367
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1870940058
Short name T695
Test name
Test status
Simulation time 90505736 ps
CPU time 1.09 seconds
Started Jul 16 04:55:46 PM PDT 24
Finished Jul 16 04:55:48 PM PDT 24
Peak memory 196556 kb
Host smart-218a15c5-3a59-437a-898e-fc5ce13fa0c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870940058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1870940058
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.43127203
Short name T358
Test name
Test status
Simulation time 79552356 ps
CPU time 1.79 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:55 PM PDT 24
Peak memory 196708 kb
Host smart-c9188b44-4033-4264-9da6-7ed4cfda53bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43127203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.43127203
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.949171387
Short name T415
Test name
Test status
Simulation time 45542868 ps
CPU time 0.76 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:48 PM PDT 24
Peak memory 196008 kb
Host smart-048cfbda-0876-4d50-a387-cb176be3c669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949171387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.949171387
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.935107903
Short name T628
Test name
Test status
Simulation time 64540687 ps
CPU time 1.08 seconds
Started Jul 16 04:55:48 PM PDT 24
Finished Jul 16 04:55:50 PM PDT 24
Peak memory 196472 kb
Host smart-179db8d1-a90b-4b3c-9166-c30f6728a676
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935107903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.935107903
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1449516406
Short name T494
Test name
Test status
Simulation time 473256499 ps
CPU time 4.8 seconds
Started Jul 16 04:55:49 PM PDT 24
Finished Jul 16 04:55:55 PM PDT 24
Peak memory 198488 kb
Host smart-db1aa0ec-96b2-4b8e-b848-735af8c9b77e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449516406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1449516406
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.649230633
Short name T616
Test name
Test status
Simulation time 48503358 ps
CPU time 0.89 seconds
Started Jul 16 04:55:48 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 196172 kb
Host smart-4f8bdc2c-77a2-4fdd-94b8-b4a680b02af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649230633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.649230633
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3860363940
Short name T644
Test name
Test status
Simulation time 35717433 ps
CPU time 0.77 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 195648 kb
Host smart-8ede8303-341b-4467-8530-d41a58052328
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860363940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3860363940
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.401944071
Short name T7
Test name
Test status
Simulation time 7041933426 ps
CPU time 35.79 seconds
Started Jul 16 04:56:41 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 198640 kb
Host smart-eb6f36b3-69f3-4d87-b6da-4097ac6cb3c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401944071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.401944071
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1123538004
Short name T505
Test name
Test status
Simulation time 12212487 ps
CPU time 0.6 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 194488 kb
Host smart-74b12352-de2e-43b3-80c4-049320059d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123538004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1123538004
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1751343714
Short name T523
Test name
Test status
Simulation time 42375244 ps
CPU time 0.68 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:54 PM PDT 24
Peak memory 195348 kb
Host smart-6d895d96-6bcc-483e-b89d-8e816b4e2141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751343714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1751343714
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3338071203
Short name T518
Test name
Test status
Simulation time 1095143514 ps
CPU time 14.66 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 04:56:07 PM PDT 24
Peak memory 198500 kb
Host smart-7a7397db-8fca-4752-a219-94718ddaec84
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338071203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3338071203
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.4041330872
Short name T529
Test name
Test status
Simulation time 314250501 ps
CPU time 0.97 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:55:59 PM PDT 24
Peak memory 198440 kb
Host smart-ee5f9fd8-f136-4cbe-aeb2-15352319801f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041330872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.4041330872
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2418389374
Short name T417
Test name
Test status
Simulation time 359158742 ps
CPU time 1.27 seconds
Started Jul 16 04:56:33 PM PDT 24
Finished Jul 16 04:56:36 PM PDT 24
Peak memory 196652 kb
Host smart-bd83676f-6c28-447c-b2bd-a23f5d40d0f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418389374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2418389374
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1444550637
Short name T538
Test name
Test status
Simulation time 286434255 ps
CPU time 3.11 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 198504 kb
Host smart-f311a4ca-9dc7-4c6f-bc27-04032dab23f6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444550637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1444550637
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3817612529
Short name T122
Test name
Test status
Simulation time 334369614 ps
CPU time 1.94 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:55:59 PM PDT 24
Peak memory 196512 kb
Host smart-4c64c2a4-dd78-43d7-b44f-0de9145a7252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817612529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3817612529
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1751407570
Short name T340
Test name
Test status
Simulation time 89999611 ps
CPU time 0.87 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 196488 kb
Host smart-e6070ea7-b8f4-4433-93c6-e6b6975b5110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751407570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1751407570
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3705468803
Short name T640
Test name
Test status
Simulation time 63997279 ps
CPU time 0.69 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:57 PM PDT 24
Peak memory 195504 kb
Host smart-669cc98c-1612-4c89-913a-6390b918f96e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705468803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3705468803
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1611265165
Short name T710
Test name
Test status
Simulation time 365742638 ps
CPU time 2.95 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 198524 kb
Host smart-1fd6c76f-8c2e-4a9c-b827-b3a57c22f83e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611265165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1611265165
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3688462
Short name T283
Test name
Test status
Simulation time 251007495 ps
CPU time 1.22 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:58 PM PDT 24
Peak memory 196048 kb
Host smart-03fa1ca4-e316-4ca1-b33d-d36a96149e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3688462
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3606572103
Short name T275
Test name
Test status
Simulation time 46569066 ps
CPU time 1.05 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:00 PM PDT 24
Peak memory 196320 kb
Host smart-2d437e4a-598c-49a3-ba22-6696ef684ea6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606572103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3606572103
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1208079297
Short name T598
Test name
Test status
Simulation time 3980578361 ps
CPU time 102.01 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:57:34 PM PDT 24
Peak memory 198680 kb
Host smart-0eb2c486-00d6-448d-9034-dca55ecd68a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208079297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1208079297
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3414919282
Short name T109
Test name
Test status
Simulation time 304115082626 ps
CPU time 1649.63 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 05:23:22 PM PDT 24
Peak memory 198764 kb
Host smart-42f7109f-a0b7-44b5-8de8-fe948854dea8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3414919282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3414919282
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1053483804
Short name T56
Test name
Test status
Simulation time 31876232 ps
CPU time 0.56 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:55 PM PDT 24
Peak memory 195360 kb
Host smart-4c3e7e95-fb54-4dd8-88f5-1f4dff0b3064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053483804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1053483804
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1511735194
Short name T446
Test name
Test status
Simulation time 36623136 ps
CPU time 0.78 seconds
Started Jul 16 04:55:43 PM PDT 24
Finished Jul 16 04:55:45 PM PDT 24
Peak memory 195876 kb
Host smart-17aada55-df07-4251-a37c-2ded3b98d680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511735194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1511735194
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.84551467
Short name T140
Test name
Test status
Simulation time 404477318 ps
CPU time 11.92 seconds
Started Jul 16 04:55:43 PM PDT 24
Finished Jul 16 04:55:56 PM PDT 24
Peak memory 197460 kb
Host smart-8f4117a3-1b07-46cd-b97e-3792b3f8f84d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84551467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stress
.84551467
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3163536056
Short name T131
Test name
Test status
Simulation time 31478939 ps
CPU time 0.69 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 195452 kb
Host smart-30b21aa7-1024-4b76-b264-9732c761f7cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163536056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3163536056
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1213830251
Short name T314
Test name
Test status
Simulation time 17352360 ps
CPU time 0.65 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:54 PM PDT 24
Peak memory 194848 kb
Host smart-155d0f00-59a8-47c1-8721-788da1bbdb0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213830251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1213830251
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3613941983
Short name T586
Test name
Test status
Simulation time 68487235 ps
CPU time 2.45 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:54 PM PDT 24
Peak memory 198512 kb
Host smart-e8b25223-6321-447b-8a6e-4b6daa707d8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613941983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3613941983
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3577151640
Short name T362
Test name
Test status
Simulation time 273228245 ps
CPU time 2.85 seconds
Started Jul 16 04:56:01 PM PDT 24
Finished Jul 16 04:56:09 PM PDT 24
Peak memory 197800 kb
Host smart-109e105d-cab3-4824-ad26-ef820027feb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577151640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3577151640
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1350119990
Short name T515
Test name
Test status
Simulation time 141589273 ps
CPU time 0.88 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:46 PM PDT 24
Peak memory 197140 kb
Host smart-015334b2-e5ff-4b34-b6e0-aaefc902f887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350119990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1350119990
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3538599305
Short name T604
Test name
Test status
Simulation time 66612836 ps
CPU time 1.29 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:00 PM PDT 24
Peak memory 198580 kb
Host smart-07fa29d9-3c5d-490d-81c3-06a4fad0cbda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538599305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3538599305
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3938026651
Short name T199
Test name
Test status
Simulation time 229382535 ps
CPU time 2.54 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 198352 kb
Host smart-ddc27c0e-a06d-444c-b0a5-a34cdd986f70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938026651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3938026651
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3511699008
Short name T460
Test name
Test status
Simulation time 118506936 ps
CPU time 0.94 seconds
Started Jul 16 04:55:48 PM PDT 24
Finished Jul 16 04:55:50 PM PDT 24
Peak memory 196296 kb
Host smart-9d768632-3838-4e63-9de2-0a432e065040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511699008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3511699008
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.302094937
Short name T294
Test name
Test status
Simulation time 64511632 ps
CPU time 1.12 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:52 PM PDT 24
Peak memory 196396 kb
Host smart-300332d9-a59b-408a-9dfb-08bcf6a47f36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302094937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.302094937
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2998109880
Short name T645
Test name
Test status
Simulation time 11189004393 ps
CPU time 123.79 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:58:09 PM PDT 24
Peak memory 198600 kb
Host smart-4a761eef-b2e3-448f-8840-0f84625e2cfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998109880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2998109880
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.62790270
Short name T239
Test name
Test status
Simulation time 54900886 ps
CPU time 0.58 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 194708 kb
Host smart-8c0abcd1-d81e-4b9c-a6c7-911cebed99e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62790270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.62790270
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3447068475
Short name T663
Test name
Test status
Simulation time 33739874 ps
CPU time 0.82 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 195800 kb
Host smart-4b221987-1164-44f3-9dd1-b3863ba51e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447068475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3447068475
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1216272067
Short name T514
Test name
Test status
Simulation time 589042491 ps
CPU time 19.86 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:18 PM PDT 24
Peak memory 198596 kb
Host smart-0e218bf5-854a-41c0-9c18-6e51d5e08eca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216272067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1216272067
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2904109518
Short name T360
Test name
Test status
Simulation time 803993475 ps
CPU time 1.04 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 197032 kb
Host smart-66c130e3-47cb-4be4-ba44-b7fa95544819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904109518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2904109518
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1697929435
Short name T302
Test name
Test status
Simulation time 103120116 ps
CPU time 1.13 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 196576 kb
Host smart-95880df9-fb69-4eef-a5d9-fc36194d8cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697929435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1697929435
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2574933360
Short name T235
Test name
Test status
Simulation time 185761631 ps
CPU time 3.59 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 04:55:56 PM PDT 24
Peak memory 198552 kb
Host smart-355f5b91-b8dc-4b33-8382-302bef29b94a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574933360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2574933360
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.121907546
Short name T401
Test name
Test status
Simulation time 707010363 ps
CPU time 3.05 seconds
Started Jul 16 04:55:49 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 197516 kb
Host smart-608448be-f8b9-4dd3-bc95-82ec81d72838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121907546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
121907546
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.65681619
Short name T293
Test name
Test status
Simulation time 24062665 ps
CPU time 0.67 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 194848 kb
Host smart-650ce4b5-00c3-4b20-b544-33042ea1027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65681619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.65681619
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4022346677
Short name T281
Test name
Test status
Simulation time 65538790 ps
CPU time 1.18 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:55 PM PDT 24
Peak memory 198604 kb
Host smart-2c9c4717-4ff9-46f7-8edb-5665b1935230
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022346677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4022346677
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1049728349
Short name T572
Test name
Test status
Simulation time 807219970 ps
CPU time 4.15 seconds
Started Jul 16 04:55:44 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 198496 kb
Host smart-cb6ae2ea-185d-42be-8cb2-a28d69a69a1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049728349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1049728349
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.4066155923
Short name T242
Test name
Test status
Simulation time 97441659 ps
CPU time 1.39 seconds
Started Jul 16 04:55:45 PM PDT 24
Finished Jul 16 04:55:47 PM PDT 24
Peak memory 197156 kb
Host smart-e6238006-0454-4ed6-ae81-c067ef61442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066155923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4066155923
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1457306211
Short name T456
Test name
Test status
Simulation time 69532442 ps
CPU time 1.35 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:55 PM PDT 24
Peak memory 197348 kb
Host smart-c23b5128-0268-4c54-af6c-1d0fb18fa597
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457306211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1457306211
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3090595150
Short name T509
Test name
Test status
Simulation time 32865876 ps
CPU time 0.6 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 194616 kb
Host smart-0a3c859a-65e1-4edc-a27a-e272ec19f05e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090595150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3090595150
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.690582484
Short name T549
Test name
Test status
Simulation time 101939874 ps
CPU time 0.81 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 195776 kb
Host smart-049e96af-3fe3-45ec-a9f6-ba5f7ba2d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690582484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.690582484
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1670449866
Short name T488
Test name
Test status
Simulation time 1127748523 ps
CPU time 19.34 seconds
Started Jul 16 04:56:03 PM PDT 24
Finished Jul 16 04:56:26 PM PDT 24
Peak memory 198460 kb
Host smart-08f52b11-c46b-4a82-b237-727d8e396d87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670449866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1670449866
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3305618343
Short name T550
Test name
Test status
Simulation time 63092693 ps
CPU time 0.89 seconds
Started Jul 16 04:56:15 PM PDT 24
Finished Jul 16 04:56:16 PM PDT 24
Peak memory 196444 kb
Host smart-1b94ee38-1726-4d27-8c99-fff618ddefc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305618343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3305618343
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1427304235
Short name T492
Test name
Test status
Simulation time 369304449 ps
CPU time 0.85 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 197968 kb
Host smart-72e9a018-3c2b-4d52-a8ff-04221993b339
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427304235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1427304235
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2977122801
Short name T219
Test name
Test status
Simulation time 448009277 ps
CPU time 3.2 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 198456 kb
Host smart-2bd23a1c-1dd6-404f-884a-71b08be6c866
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977122801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2977122801
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3187097374
Short name T250
Test name
Test status
Simulation time 64963131 ps
CPU time 1.95 seconds
Started Jul 16 04:56:20 PM PDT 24
Finished Jul 16 04:56:23 PM PDT 24
Peak memory 198568 kb
Host smart-205f93eb-d2a5-478a-b45d-92a8ac2226c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187097374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3187097374
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3596010309
Short name T139
Test name
Test status
Simulation time 89139671 ps
CPU time 1.03 seconds
Started Jul 16 04:55:48 PM PDT 24
Finished Jul 16 04:55:51 PM PDT 24
Peak memory 197276 kb
Host smart-ba87892f-0a5f-4507-98f0-9b64387e0807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596010309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3596010309
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2529849858
Short name T473
Test name
Test status
Simulation time 224885597 ps
CPU time 1.23 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:55:59 PM PDT 24
Peak memory 196384 kb
Host smart-e63e677e-4da3-4c19-b2fa-2477c96c86eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529849858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2529849858
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3373130080
Short name T680
Test name
Test status
Simulation time 339653275 ps
CPU time 3.58 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:59 PM PDT 24
Peak memory 198484 kb
Host smart-331930d7-8752-4073-8bde-ef70e7146d77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373130080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3373130080
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1422691578
Short name T703
Test name
Test status
Simulation time 51632576 ps
CPU time 0.94 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 196268 kb
Host smart-12c842b7-4c1a-4559-be44-3c802a5128b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422691578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1422691578
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3443979527
Short name T115
Test name
Test status
Simulation time 96313614 ps
CPU time 1.01 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:55:59 PM PDT 24
Peak memory 196264 kb
Host smart-f0c2f377-2724-4708-84ec-5a24bb421797
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443979527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3443979527
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2468010803
Short name T218
Test name
Test status
Simulation time 6907484461 ps
CPU time 169.13 seconds
Started Jul 16 04:56:01 PM PDT 24
Finished Jul 16 04:58:56 PM PDT 24
Peak memory 198620 kb
Host smart-0f15229b-3bf7-44c6-8a1d-2c18036c59c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468010803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2468010803
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2004770701
Short name T709
Test name
Test status
Simulation time 42175406 ps
CPU time 0.56 seconds
Started Jul 16 04:56:01 PM PDT 24
Finished Jul 16 04:56:07 PM PDT 24
Peak memory 194676 kb
Host smart-b6ff56dd-54ad-4175-96ab-09ffb79f788d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004770701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2004770701
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3723482197
Short name T323
Test name
Test status
Simulation time 33477310 ps
CPU time 0.76 seconds
Started Jul 16 04:56:07 PM PDT 24
Finished Jul 16 04:56:10 PM PDT 24
Peak memory 196620 kb
Host smart-23e2d42c-3a6c-4a95-88a3-c40f29df73b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723482197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3723482197
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3956263639
Short name T73
Test name
Test status
Simulation time 599379498 ps
CPU time 15.45 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:56:07 PM PDT 24
Peak memory 196028 kb
Host smart-3e0cea6c-0433-4394-a23b-d3ebaefd71a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956263639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3956263639
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2376703401
Short name T464
Test name
Test status
Simulation time 224168514 ps
CPU time 0.89 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 197412 kb
Host smart-b0f0bc62-516a-4ade-98c2-2ff1c924b979
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376703401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2376703401
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1919850532
Short name T652
Test name
Test status
Simulation time 386529315 ps
CPU time 1.24 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:58 PM PDT 24
Peak memory 196784 kb
Host smart-8e310f7f-6449-44f5-b625-b3cc980e5ac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919850532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1919850532
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.307007344
Short name T377
Test name
Test status
Simulation time 212231004 ps
CPU time 2.48 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:07 PM PDT 24
Peak memory 198452 kb
Host smart-aead4050-8de7-4be8-838c-1586a76eda3b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307007344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.307007344
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3616488703
Short name T80
Test name
Test status
Simulation time 160891890 ps
CPU time 1.13 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 196008 kb
Host smart-e629f5d9-e296-453d-a548-909616bbf250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616488703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3616488703
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3401207954
Short name T425
Test name
Test status
Simulation time 86975071 ps
CPU time 0.78 seconds
Started Jul 16 04:55:47 PM PDT 24
Finished Jul 16 04:55:49 PM PDT 24
Peak memory 195848 kb
Host smart-a2bcb7e7-5db5-4d6d-8876-b034b9866cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401207954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3401207954
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3810936790
Short name T367
Test name
Test status
Simulation time 51159074 ps
CPU time 0.62 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 194720 kb
Host smart-1dee19ee-6876-4a1b-b7ee-5c3338369fc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810936790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3810936790
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2831202760
Short name T585
Test name
Test status
Simulation time 3379080647 ps
CPU time 5.54 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:08 PM PDT 24
Peak memory 198580 kb
Host smart-a2bcb234-0e7d-458f-ae98-d034e8048a1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831202760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2831202760
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.743862166
Short name T69
Test name
Test status
Simulation time 486008838 ps
CPU time 1.23 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 197588 kb
Host smart-6bdb5d6f-26f6-460c-ad87-255633f4e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743862166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.743862166
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.653333584
Short name T466
Test name
Test status
Simulation time 134876562 ps
CPU time 1.14 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 196420 kb
Host smart-1360cef6-0675-473f-9d40-82ca647e70c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653333584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.653333584
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1320198657
Short name T690
Test name
Test status
Simulation time 56074865602 ps
CPU time 184.06 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:59:07 PM PDT 24
Peak memory 198756 kb
Host smart-7a807729-37b9-4e66-9741-e0c152280f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320198657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1320198657
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.307192832
Short name T383
Test name
Test status
Simulation time 32144642 ps
CPU time 0.55 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 195296 kb
Host smart-973e49a0-83a2-40df-9e7f-8bd0872a7373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307192832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.307192832
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2390085179
Short name T224
Test name
Test status
Simulation time 91450708 ps
CPU time 0.81 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:00 PM PDT 24
Peak memory 195892 kb
Host smart-1405b203-8632-4760-a914-c03ab2d3b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390085179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2390085179
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3507969180
Short name T214
Test name
Test status
Simulation time 2282958216 ps
CPU time 15.12 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:19 PM PDT 24
Peak memory 197400 kb
Host smart-259abaa2-abb1-43d0-ae5c-d0efa31b93b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507969180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3507969180
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1941098467
Short name T396
Test name
Test status
Simulation time 204588207 ps
CPU time 1.1 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:56:21 PM PDT 24
Peak memory 197176 kb
Host smart-e8079435-7476-43f8-8a6e-a7cee172406d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941098467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1941098467
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.838655244
Short name T607
Test name
Test status
Simulation time 114316446 ps
CPU time 1.05 seconds
Started Jul 16 04:56:16 PM PDT 24
Finished Jul 16 04:56:18 PM PDT 24
Peak memory 197388 kb
Host smart-59398d43-07d8-41bf-afea-e7afb71043e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838655244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.838655244
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.349382415
Short name T392
Test name
Test status
Simulation time 27365112 ps
CPU time 1.14 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 196632 kb
Host smart-bce19ec0-03f9-4f33-b09b-ad1802590ca8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349382415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.349382415
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2760719585
Short name T432
Test name
Test status
Simulation time 91880066 ps
CPU time 1.5 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:00 PM PDT 24
Peak memory 196392 kb
Host smart-dd48ac94-bac0-42fa-92da-87d871a8fd12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760719585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2760719585
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.308546653
Short name T666
Test name
Test status
Simulation time 45470639 ps
CPU time 1.04 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:55:58 PM PDT 24
Peak memory 196504 kb
Host smart-0e5d0726-cf7a-45ab-b7bd-0de08e9ab3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308546653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.308546653
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.659355594
Short name T622
Test name
Test status
Simulation time 76289392 ps
CPU time 0.9 seconds
Started Jul 16 04:55:50 PM PDT 24
Finished Jul 16 04:55:53 PM PDT 24
Peak memory 197220 kb
Host smart-115257c3-477f-4093-988b-d961a4007129
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659355594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.659355594
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.250106602
Short name T355
Test name
Test status
Simulation time 420262801 ps
CPU time 4.83 seconds
Started Jul 16 04:56:05 PM PDT 24
Finished Jul 16 04:56:12 PM PDT 24
Peak memory 198556 kb
Host smart-aa705ee1-c9df-4599-9728-79f6c2f60432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250106602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.250106602
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.846765189
Short name T463
Test name
Test status
Simulation time 66491535 ps
CPU time 1.14 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:00 PM PDT 24
Peak memory 196260 kb
Host smart-6dcbbbef-90f5-46b9-a8b0-0a53672c9f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846765189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.846765189
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2768020816
Short name T686
Test name
Test status
Simulation time 62020644 ps
CPU time 1.07 seconds
Started Jul 16 04:55:51 PM PDT 24
Finished Jul 16 04:55:54 PM PDT 24
Peak memory 196700 kb
Host smart-e6836282-efa9-491b-ba0f-bf934c52570d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768020816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2768020816
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1504794147
Short name T413
Test name
Test status
Simulation time 5595234053 ps
CPU time 145.72 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:58:27 PM PDT 24
Peak memory 198588 kb
Host smart-65f73667-5ad5-4fe8-86ec-79e44bf51eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504794147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1504794147
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2137016302
Short name T34
Test name
Test status
Simulation time 64527205032 ps
CPU time 1192.75 seconds
Started Jul 16 04:56:14 PM PDT 24
Finished Jul 16 05:16:07 PM PDT 24
Peak memory 198796 kb
Host smart-e5691523-1692-4ce8-9a93-9ab25148649e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2137016302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2137016302
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.935160392
Short name T330
Test name
Test status
Simulation time 142261905 ps
CPU time 0.57 seconds
Started Jul 16 04:56:06 PM PDT 24
Finished Jul 16 04:56:09 PM PDT 24
Peak memory 194416 kb
Host smart-a64e4bf6-1ecb-4745-87f5-155888617e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935160392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.935160392
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1700290923
Short name T647
Test name
Test status
Simulation time 71672918 ps
CPU time 0.73 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 196540 kb
Host smart-e21a59f8-a176-476b-87dc-c47d0f9cabb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700290923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1700290923
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.702805109
Short name T633
Test name
Test status
Simulation time 1038948487 ps
CPU time 5.6 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 197432 kb
Host smart-147b3605-ba69-4ee7-a2f3-85b74a05256a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702805109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.702805109
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.468587510
Short name T655
Test name
Test status
Simulation time 247791742 ps
CPU time 0.97 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 198264 kb
Host smart-4f7b8d64-7175-4bd8-afa8-0a2850082126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468587510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.468587510
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3263363803
Short name T213
Test name
Test status
Simulation time 671141114 ps
CPU time 0.87 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 196132 kb
Host smart-d8702481-b23c-4a3f-8372-3a7813569214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263363803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3263363803
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.293672510
Short name T445
Test name
Test status
Simulation time 53749298 ps
CPU time 2.06 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 198612 kb
Host smart-5541f67d-c943-4380-9832-d6201a154381
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293672510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.293672510
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2895099299
Short name T465
Test name
Test status
Simulation time 208433674 ps
CPU time 2.95 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 198608 kb
Host smart-ff877963-cbb1-4484-b725-d822cfba5e08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895099299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2895099299
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.37988152
Short name T78
Test name
Test status
Simulation time 15683763 ps
CPU time 0.69 seconds
Started Jul 16 04:55:52 PM PDT 24
Finished Jul 16 04:55:54 PM PDT 24
Peak memory 194716 kb
Host smart-ddc4bbe9-cb9a-426d-a9d3-b45696224688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37988152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.37988152
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3665767933
Short name T444
Test name
Test status
Simulation time 60167049 ps
CPU time 1.11 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:56 PM PDT 24
Peak memory 196308 kb
Host smart-70032c8d-7590-4e9e-a4c7-72b390b12be8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665767933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3665767933
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3507248143
Short name T656
Test name
Test status
Simulation time 884194573 ps
CPU time 4.67 seconds
Started Jul 16 04:56:07 PM PDT 24
Finished Jul 16 04:56:13 PM PDT 24
Peak memory 198472 kb
Host smart-48a1983d-f0fc-475d-8f20-c540d216a0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507248143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3507248143
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.903639106
Short name T584
Test name
Test status
Simulation time 34058533 ps
CPU time 0.95 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 196844 kb
Host smart-bb7aa348-e054-418a-90c7-eb4e7331424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903639106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.903639106
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.328886599
Short name T181
Test name
Test status
Simulation time 251895533 ps
CPU time 1.22 seconds
Started Jul 16 04:55:54 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 196452 kb
Host smart-c94670ae-4b1c-49c9-a691-692da450c9c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328886599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.328886599
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3632997120
Short name T568
Test name
Test status
Simulation time 72612667317 ps
CPU time 194.15 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:59:10 PM PDT 24
Peak memory 198736 kb
Host smart-161b4947-b9a9-43d7-9173-2519eeaed186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632997120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3632997120
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3752118038
Short name T543
Test name
Test status
Simulation time 92455699064 ps
CPU time 611.87 seconds
Started Jul 16 04:55:48 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 198820 kb
Host smart-427c31e2-0917-4a72-acda-af65146fcc4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3752118038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3752118038
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3205688876
Short name T423
Test name
Test status
Simulation time 26619336 ps
CPU time 0.59 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 194528 kb
Host smart-d5bbe023-a6b1-44ad-aafd-87e1cf2b049e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205688876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3205688876
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1825640734
Short name T326
Test name
Test status
Simulation time 19670521 ps
CPU time 0.67 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 195320 kb
Host smart-ce5071dd-cdd1-4169-9fff-2f8b14970385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825640734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1825640734
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.198971247
Short name T170
Test name
Test status
Simulation time 566501861 ps
CPU time 5.86 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 197396 kb
Host smart-3965869d-becc-4159-87ef-fc47c3b51b18
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198971247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.198971247
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1104993515
Short name T635
Test name
Test status
Simulation time 26547602 ps
CPU time 0.67 seconds
Started Jul 16 04:54:47 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 195056 kb
Host smart-80d07655-5ad1-4a31-83a0-effb13813c31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104993515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1104993515
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1957692607
Short name T406
Test name
Test status
Simulation time 29451152 ps
CPU time 0.73 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 194804 kb
Host smart-612ce269-46c5-49a8-b7ef-429bf20b9342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957692607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1957692607
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1445087649
Short name T618
Test name
Test status
Simulation time 105558228 ps
CPU time 3.6 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 198536 kb
Host smart-9fcaa2ff-2788-4b9c-af4f-9cbfd2e777c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445087649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1445087649
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2160347272
Short name T247
Test name
Test status
Simulation time 53421837 ps
CPU time 1.31 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 197224 kb
Host smart-c4816415-9b0f-4a6e-ba8e-c56166a5f1ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160347272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2160347272
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2467058602
Short name T555
Test name
Test status
Simulation time 17167942 ps
CPU time 0.66 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 194648 kb
Host smart-62a58dc9-f964-4977-b263-16193a2088ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467058602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2467058602
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.287697498
Short name T668
Test name
Test status
Simulation time 72931935 ps
CPU time 1.26 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 198612 kb
Host smart-657087ce-9964-4c13-ae81-fe55189dd705
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287697498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.287697498
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4097819067
Short name T8
Test name
Test status
Simulation time 2115634570 ps
CPU time 6.13 seconds
Started Jul 16 04:54:50 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 198456 kb
Host smart-4631164e-2fb4-4710-8830-7e29eb39ba71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097819067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4097819067
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.38231875
Short name T57
Test name
Test status
Simulation time 421376893 ps
CPU time 0.9 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 214916 kb
Host smart-002ebdd9-d006-41aa-9e44-35f7b674e6b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38231875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.38231875
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2019850594
Short name T422
Test name
Test status
Simulation time 88122129 ps
CPU time 1.27 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 197832 kb
Host smart-a98ce566-90ba-4882-8c6b-209856f9b819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019850594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2019850594
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3689650892
Short name T351
Test name
Test status
Simulation time 23848361 ps
CPU time 0.82 seconds
Started Jul 16 04:55:07 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 195776 kb
Host smart-afb4d7da-023c-4c33-bd41-065a26cc644b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689650892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3689650892
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.486083477
Short name T602
Test name
Test status
Simulation time 8590061152 ps
CPU time 49.5 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:55 PM PDT 24
Peak memory 198560 kb
Host smart-c1e0e60e-f07b-4409-9298-fa5fca7e306c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486083477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.486083477
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1762224296
Short name T570
Test name
Test status
Simulation time 20848005 ps
CPU time 0.56 seconds
Started Jul 16 04:56:07 PM PDT 24
Finished Jul 16 04:56:09 PM PDT 24
Peak memory 194536 kb
Host smart-7656cb80-57f9-42fe-bcdc-4a81044e1b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762224296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1762224296
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.594329507
Short name T458
Test name
Test status
Simulation time 203068461 ps
CPU time 0.75 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 195776 kb
Host smart-90a42124-c1f3-407f-98e1-5b1cd844997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594329507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.594329507
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1927694357
Short name T164
Test name
Test status
Simulation time 1038346919 ps
CPU time 29.24 seconds
Started Jul 16 04:56:01 PM PDT 24
Finished Jul 16 04:56:35 PM PDT 24
Peak memory 197240 kb
Host smart-28b9729d-f4ce-499d-9d4f-31a02616e707
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927694357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1927694357
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1576582456
Short name T327
Test name
Test status
Simulation time 1830611400 ps
CPU time 1.05 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 197120 kb
Host smart-dc7dcc24-6215-4475-b1b8-4a8ef1c59da5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576582456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1576582456
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3113833958
Short name T617
Test name
Test status
Simulation time 67184835 ps
CPU time 1.22 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 196384 kb
Host smart-3017492f-b362-4cad-80f6-3b93982be63d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113833958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3113833958
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3316075089
Short name T195
Test name
Test status
Simulation time 357466960 ps
CPU time 3.6 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:08 PM PDT 24
Peak memory 198652 kb
Host smart-4e83aa14-60ed-422e-b35d-30cc5d4ff0bf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316075089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3316075089
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.857545927
Short name T201
Test name
Test status
Simulation time 666619583 ps
CPU time 2.7 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 197760 kb
Host smart-6d9f5de6-6237-4f0f-a0b2-0671d3415d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857545927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
857545927
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1520933120
Short name T297
Test name
Test status
Simulation time 52697992 ps
CPU time 0.69 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:56:22 PM PDT 24
Peak memory 196020 kb
Host smart-930498ae-53f3-45a7-9754-f7aec0ffb2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520933120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1520933120
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1315077048
Short name T229
Test name
Test status
Simulation time 36160652 ps
CPU time 1.21 seconds
Started Jul 16 04:56:11 PM PDT 24
Finished Jul 16 04:56:13 PM PDT 24
Peak memory 197496 kb
Host smart-671053da-b520-40f2-83fe-4165d7ed3c19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315077048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1315077048
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2114767109
Short name T252
Test name
Test status
Simulation time 1040505794 ps
CPU time 3.5 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 197536 kb
Host smart-04241fe9-2404-476c-96fb-a88550f59b08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114767109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2114767109
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1663707524
Short name T676
Test name
Test status
Simulation time 120902553 ps
CPU time 1.19 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 196072 kb
Host smart-a316431c-a205-4483-8039-7d92dbfc0e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663707524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1663707524
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2391680128
Short name T702
Test name
Test status
Simulation time 59619416 ps
CPU time 1.17 seconds
Started Jul 16 04:56:00 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 196204 kb
Host smart-e8eba848-23e6-4cdb-8f77-a89980d96748
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391680128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2391680128
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2037648961
Short name T5
Test name
Test status
Simulation time 9539194317 ps
CPU time 112.72 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:57:57 PM PDT 24
Peak memory 198584 kb
Host smart-5a369cb4-0e57-4084-b8a1-9acbe18ed64a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037648961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2037648961
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2579212179
Short name T238
Test name
Test status
Simulation time 39603992 ps
CPU time 0.57 seconds
Started Jul 16 04:56:27 PM PDT 24
Finished Jul 16 04:56:29 PM PDT 24
Peak memory 195156 kb
Host smart-d274e69e-9685-43fa-83d6-476e04fbec28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579212179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2579212179
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3770749228
Short name T336
Test name
Test status
Simulation time 87756755 ps
CPU time 0.66 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 194604 kb
Host smart-5ab3d91b-334e-4b9f-ab89-c5db66d285fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770749228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3770749228
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.4287329999
Short name T74
Test name
Test status
Simulation time 502820795 ps
CPU time 8.91 seconds
Started Jul 16 04:56:09 PM PDT 24
Finished Jul 16 04:56:19 PM PDT 24
Peak memory 196892 kb
Host smart-19fd326d-4578-4a57-a5a9-af042a487f9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287329999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.4287329999
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2018007950
Short name T334
Test name
Test status
Simulation time 35471657 ps
CPU time 0.83 seconds
Started Jul 16 04:56:41 PM PDT 24
Finished Jul 16 04:56:43 PM PDT 24
Peak memory 197008 kb
Host smart-424f6f62-0178-4830-ba76-0710f05dd563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018007950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2018007950
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.4127029831
Short name T448
Test name
Test status
Simulation time 51483595 ps
CPU time 1.2 seconds
Started Jul 16 04:55:53 PM PDT 24
Finished Jul 16 04:55:58 PM PDT 24
Peak memory 196608 kb
Host smart-fe390bf0-8e9b-4ee8-9eee-b255a977534e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127029831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.4127029831
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1735917567
Short name T147
Test name
Test status
Simulation time 69688036 ps
CPU time 2.53 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:56:23 PM PDT 24
Peak memory 198652 kb
Host smart-71966616-8c08-4669-aff9-c64bb9d40da1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735917567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1735917567
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1595291183
Short name T301
Test name
Test status
Simulation time 94863910 ps
CPU time 2.08 seconds
Started Jul 16 04:56:08 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 197788 kb
Host smart-3ffceaf1-5e66-4ea4-8e3b-b3bf8b75a394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595291183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1595291183
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2128075756
Short name T161
Test name
Test status
Simulation time 67702037 ps
CPU time 1.18 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 197136 kb
Host smart-a3deb172-7804-4354-9440-b6ae98977700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128075756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2128075756
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2525535852
Short name T689
Test name
Test status
Simulation time 326976183 ps
CPU time 1.01 seconds
Started Jul 16 04:55:55 PM PDT 24
Finished Jul 16 04:56:01 PM PDT 24
Peak memory 196420 kb
Host smart-4e510afe-c6cc-4021-8dc7-b474313a2c4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525535852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2525535852
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.201242903
Short name T148
Test name
Test status
Simulation time 400668497 ps
CPU time 3.36 seconds
Started Jul 16 04:56:03 PM PDT 24
Finished Jul 16 04:56:10 PM PDT 24
Peak memory 198428 kb
Host smart-735a295d-20e4-4fcd-8b62-991d7b07282c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201242903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.201242903
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4182801103
Short name T411
Test name
Test status
Simulation time 49418197 ps
CPU time 1 seconds
Started Jul 16 04:56:11 PM PDT 24
Finished Jul 16 04:56:13 PM PDT 24
Peak memory 197072 kb
Host smart-4bbf94d5-3042-4816-ab5c-2202686ff8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182801103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4182801103
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2324383331
Short name T263
Test name
Test status
Simulation time 309664478 ps
CPU time 0.75 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:02 PM PDT 24
Peak memory 195780 kb
Host smart-8925f4d0-5cd1-4a59-92ec-971ade8bfd2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324383331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2324383331
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2085101227
Short name T245
Test name
Test status
Simulation time 6397888196 ps
CPU time 88.66 seconds
Started Jul 16 04:56:06 PM PDT 24
Finished Jul 16 04:57:37 PM PDT 24
Peak memory 198724 kb
Host smart-078ba552-add8-4ca2-858d-3725b2334ae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085101227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2085101227
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2890994903
Short name T237
Test name
Test status
Simulation time 12886918 ps
CPU time 0.58 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 194504 kb
Host smart-91e5da2b-c7f9-4883-8740-493ca9e034b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890994903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2890994903
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2986870306
Short name T126
Test name
Test status
Simulation time 35829339 ps
CPU time 0.81 seconds
Started Jul 16 04:56:22 PM PDT 24
Finished Jul 16 04:56:23 PM PDT 24
Peak memory 196400 kb
Host smart-4953e27c-573b-4cc0-86be-58cfa8a0072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986870306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2986870306
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1490899930
Short name T124
Test name
Test status
Simulation time 531689192 ps
CPU time 8.38 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:13 PM PDT 24
Peak memory 198500 kb
Host smart-ebd8ab7f-d903-4e5a-8d8f-4d13a530a09c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490899930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1490899930
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3257817328
Short name T331
Test name
Test status
Simulation time 290024538 ps
CPU time 0.87 seconds
Started Jul 16 04:56:23 PM PDT 24
Finished Jul 16 04:56:25 PM PDT 24
Peak memory 196520 kb
Host smart-716c292c-bb1c-46ef-93da-0a690fd6cf6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257817328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3257817328
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2132387129
Short name T471
Test name
Test status
Simulation time 49129082 ps
CPU time 1.11 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 196776 kb
Host smart-422d80a3-fd38-4e8b-83ae-14abdc410acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132387129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2132387129
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1155939205
Short name T582
Test name
Test status
Simulation time 78644567 ps
CPU time 3.05 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 197780 kb
Host smart-c647d353-a72b-4dc1-b885-003b0c601cb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155939205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1155939205
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2986516234
Short name T378
Test name
Test status
Simulation time 73340744 ps
CPU time 1.75 seconds
Started Jul 16 04:56:27 PM PDT 24
Finished Jul 16 04:56:29 PM PDT 24
Peak memory 197272 kb
Host smart-7b179181-651c-4e01-a5c4-e9a976fd98de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986516234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2986516234
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1829740347
Short name T581
Test name
Test status
Simulation time 20288612 ps
CPU time 0.8 seconds
Started Jul 16 04:56:14 PM PDT 24
Finished Jul 16 04:56:15 PM PDT 24
Peak memory 197036 kb
Host smart-8b3567d3-2259-4ca2-bf9e-ed99b848f882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829740347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1829740347
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2527338609
Short name T531
Test name
Test status
Simulation time 95479340 ps
CPU time 1.23 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 197524 kb
Host smart-ca7d2ad6-4011-432a-842c-d73e1eb6d73c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527338609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2527338609
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1532292360
Short name T144
Test name
Test status
Simulation time 325874349 ps
CPU time 1.54 seconds
Started Jul 16 04:56:10 PM PDT 24
Finished Jul 16 04:56:12 PM PDT 24
Peak memory 198548 kb
Host smart-b534e143-8299-4fe4-8261-fd1a9cbd77a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532292360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1532292360
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3847973645
Short name T217
Test name
Test status
Simulation time 144973589 ps
CPU time 0.84 seconds
Started Jul 16 04:56:00 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 195804 kb
Host smart-a6349543-cbb5-48d8-99b2-f67b6ac1243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847973645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3847973645
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.113776648
Short name T192
Test name
Test status
Simulation time 123115208 ps
CPU time 0.95 seconds
Started Jul 16 04:56:00 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 196988 kb
Host smart-d88bd9bf-9279-4bb9-93d0-e3f2a3b2af6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113776648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.113776648
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1620180581
Short name T661
Test name
Test status
Simulation time 8930055330 ps
CPU time 121.88 seconds
Started Jul 16 04:56:10 PM PDT 24
Finished Jul 16 04:58:13 PM PDT 24
Peak memory 198640 kb
Host smart-d7ac6265-dea4-4dcd-bbb9-fb1791a6a157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620180581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1620180581
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.133459658
Short name T220
Test name
Test status
Simulation time 44506987 ps
CPU time 0.56 seconds
Started Jul 16 04:56:34 PM PDT 24
Finished Jul 16 04:56:36 PM PDT 24
Peak memory 194460 kb
Host smart-3aa3f5a5-7d68-4bdf-ab6b-f0803056c408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133459658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.133459658
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.161732325
Short name T419
Test name
Test status
Simulation time 252301125 ps
CPU time 0.85 seconds
Started Jul 16 04:56:37 PM PDT 24
Finished Jul 16 04:56:38 PM PDT 24
Peak memory 197028 kb
Host smart-94e8af27-9f3b-4b72-b0f2-aee6e407eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161732325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.161732325
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2784548658
Short name T576
Test name
Test status
Simulation time 4143481369 ps
CPU time 27.51 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:56:48 PM PDT 24
Peak memory 198564 kb
Host smart-bd9025f4-51e6-4b38-b258-e1a50a75bc0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784548658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2784548658
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.268895059
Short name T397
Test name
Test status
Simulation time 106976150 ps
CPU time 1.06 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 196868 kb
Host smart-7cf376d6-4c6c-49a9-ab47-459d2ef820d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268895059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.268895059
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2262602235
Short name T512
Test name
Test status
Simulation time 906261193 ps
CPU time 1.05 seconds
Started Jul 16 04:56:10 PM PDT 24
Finished Jul 16 04:56:12 PM PDT 24
Peak memory 196336 kb
Host smart-30eba7c7-fe4d-4c1a-b748-f4dab366f1d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262602235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2262602235
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2205231555
Short name T497
Test name
Test status
Simulation time 39107412 ps
CPU time 1.64 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 198556 kb
Host smart-064fa2f8-139b-48b8-8cab-880c65194111
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205231555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2205231555
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2094914856
Short name T262
Test name
Test status
Simulation time 261840343 ps
CPU time 2.36 seconds
Started Jul 16 04:56:13 PM PDT 24
Finished Jul 16 04:56:21 PM PDT 24
Peak memory 197772 kb
Host smart-13883265-6815-45f3-a41b-a7bffdc1214f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094914856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2094914856
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2443364987
Short name T315
Test name
Test status
Simulation time 20798431 ps
CPU time 0.76 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 195904 kb
Host smart-26aa0a7d-49b0-4f0b-b802-684fe89d868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443364987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2443364987
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2050902315
Short name T553
Test name
Test status
Simulation time 104147022 ps
CPU time 1.19 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 04:56:33 PM PDT 24
Peak memory 197688 kb
Host smart-644b5ea0-49ef-4ba4-86e4-663ea7fafb72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050902315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2050902315
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.519910915
Short name T537
Test name
Test status
Simulation time 149341864 ps
CPU time 2.55 seconds
Started Jul 16 04:56:17 PM PDT 24
Finished Jul 16 04:56:20 PM PDT 24
Peak memory 198416 kb
Host smart-e3ca435b-5911-44b7-8a27-59cce4165951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519910915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.519910915
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.424510025
Short name T335
Test name
Test status
Simulation time 502210731 ps
CPU time 1.25 seconds
Started Jul 16 04:56:08 PM PDT 24
Finished Jul 16 04:56:10 PM PDT 24
Peak memory 196452 kb
Host smart-35e894a1-9c68-417f-a204-5973d0f19856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424510025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.424510025
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3972299676
Short name T637
Test name
Test status
Simulation time 237723683 ps
CPU time 0.85 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 195912 kb
Host smart-bc0b6a7d-011e-4fb7-816e-15f6e115267e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972299676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3972299676
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3908529788
Short name T14
Test name
Test status
Simulation time 14446790995 ps
CPU time 94.23 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 198664 kb
Host smart-baf16047-c8d1-4e9a-b1b7-1044c8fda8b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908529788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3908529788
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2365178757
Short name T664
Test name
Test status
Simulation time 12410250 ps
CPU time 0.54 seconds
Started Jul 16 04:56:15 PM PDT 24
Finished Jul 16 04:56:16 PM PDT 24
Peak memory 195192 kb
Host smart-d2399f4f-c27b-4b04-b9a9-3b1ad1eb1323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365178757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2365178757
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4037234319
Short name T189
Test name
Test status
Simulation time 56779469 ps
CPU time 0.99 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 196252 kb
Host smart-c4f99df9-4eae-41b3-9e39-5e6d221692a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037234319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4037234319
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1316492109
Short name T127
Test name
Test status
Simulation time 1661636716 ps
CPU time 25.58 seconds
Started Jul 16 04:56:11 PM PDT 24
Finished Jul 16 04:56:38 PM PDT 24
Peak memory 198472 kb
Host smart-1af8fb33-3ce2-401a-968a-7108e3fe77ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316492109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1316492109
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1135709632
Short name T354
Test name
Test status
Simulation time 66095378 ps
CPU time 1.09 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 197156 kb
Host smart-b24473ac-00aa-4650-8cc3-602b0122cd2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135709632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1135709632
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2410518449
Short name T292
Test name
Test status
Simulation time 139167309 ps
CPU time 0.71 seconds
Started Jul 16 04:56:05 PM PDT 24
Finished Jul 16 04:56:09 PM PDT 24
Peak memory 196592 kb
Host smart-488f31c7-5b57-48da-b074-96bd730c8fa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410518449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2410518449
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1826169911
Short name T24
Test name
Test status
Simulation time 312821751 ps
CPU time 2.51 seconds
Started Jul 16 04:56:03 PM PDT 24
Finished Jul 16 04:56:10 PM PDT 24
Peak memory 198392 kb
Host smart-9f9ca5b5-ebc4-4725-92db-70f1f7a64e56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826169911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1826169911
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2754024392
Short name T403
Test name
Test status
Simulation time 234520086 ps
CPU time 3.1 seconds
Started Jul 16 04:56:05 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 196332 kb
Host smart-fa0b975a-edeb-444c-b955-46ea8a3bf91e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754024392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2754024392
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2291270045
Short name T260
Test name
Test status
Simulation time 387928602 ps
CPU time 0.78 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 195976 kb
Host smart-7a7e8e6f-2c1a-4c53-9e17-b6e560da2eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291270045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2291270045
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3677518155
Short name T347
Test name
Test status
Simulation time 84948090 ps
CPU time 0.91 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:56:20 PM PDT 24
Peak memory 197052 kb
Host smart-e790e2f5-34e4-4b96-8af0-35b6743ada34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677518155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3677518155
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3210915606
Short name T371
Test name
Test status
Simulation time 250837555 ps
CPU time 2.95 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:56:33 PM PDT 24
Peak memory 198416 kb
Host smart-147cc734-3f44-4ecc-aaed-0cfb71ce16c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210915606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3210915606
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2550751303
Short name T320
Test name
Test status
Simulation time 80902344 ps
CPU time 1.29 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:56:21 PM PDT 24
Peak memory 197272 kb
Host smart-a22cc803-8bba-4036-b044-82c2eaef7666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550751303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2550751303
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.232521569
Short name T675
Test name
Test status
Simulation time 194764207 ps
CPU time 1.28 seconds
Started Jul 16 04:56:09 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 196176 kb
Host smart-8be8761a-3a76-4742-8015-6f7c2573cc31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232521569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.232521569
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.50062236
Short name T286
Test name
Test status
Simulation time 36460948316 ps
CPU time 197.08 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:59:20 PM PDT 24
Peak memory 198652 kb
Host smart-eef0edaf-f70f-44ef-a7e6-26363a05ffc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50062236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gp
io_stress_all.50062236
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2376291380
Short name T65
Test name
Test status
Simulation time 95389311926 ps
CPU time 1022.69 seconds
Started Jul 16 04:56:31 PM PDT 24
Finished Jul 16 05:13:35 PM PDT 24
Peak memory 198692 kb
Host smart-f0dca6b4-7736-410e-9d58-7887d5159b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2376291380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2376291380
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2159640826
Short name T154
Test name
Test status
Simulation time 39311823 ps
CPU time 0.58 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:56:35 PM PDT 24
Peak memory 194472 kb
Host smart-2f6a5a4c-5a9e-4e73-a024-85c9a3f6f6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159640826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2159640826
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3712036022
Short name T258
Test name
Test status
Simulation time 21436528 ps
CPU time 0.75 seconds
Started Jul 16 04:56:00 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 196640 kb
Host smart-b25ef5e8-9ef6-42e4-ae58-250eb4b140f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712036022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3712036022
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.285173128
Short name T313
Test name
Test status
Simulation time 9345681256 ps
CPU time 20.75 seconds
Started Jul 16 04:56:36 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 197448 kb
Host smart-5af5a9af-d452-477d-a13c-1b7f9e7ae2c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285173128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.285173128
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.392935234
Short name T452
Test name
Test status
Simulation time 75408217 ps
CPU time 0.87 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 196460 kb
Host smart-d030c5ed-33e6-47d2-8a84-5233085eaa6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392935234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.392935234
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3891829294
Short name T123
Test name
Test status
Simulation time 179550688 ps
CPU time 1.11 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 196528 kb
Host smart-578f8c51-5447-422f-a466-625533848ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891829294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3891829294
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.4123589911
Short name T186
Test name
Test status
Simulation time 26677087 ps
CPU time 1.11 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:08 PM PDT 24
Peak memory 197212 kb
Host smart-f0f574ab-fc08-4466-a1e6-dc13c906b841
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123589911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.4123589911
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2081744594
Short name T388
Test name
Test status
Simulation time 848567748 ps
CPU time 2.39 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 197512 kb
Host smart-6b066a9a-414e-4608-9c8a-a492d7aee05d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081744594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2081744594
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1042657946
Short name T285
Test name
Test status
Simulation time 21025315 ps
CPU time 0.63 seconds
Started Jul 16 04:56:16 PM PDT 24
Finished Jul 16 04:56:17 PM PDT 24
Peak memory 194740 kb
Host smart-bacb8c34-7b94-47de-994b-adf4cc49fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042657946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1042657946
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1944303416
Short name T50
Test name
Test status
Simulation time 134263196 ps
CPU time 1.24 seconds
Started Jul 16 04:56:11 PM PDT 24
Finished Jul 16 04:56:13 PM PDT 24
Peak memory 196628 kb
Host smart-b656c83b-c00d-49b0-9cda-8e110a0541c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944303416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1944303416
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2959931249
Short name T503
Test name
Test status
Simulation time 1099101921 ps
CPU time 4.49 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:08 PM PDT 24
Peak memory 198448 kb
Host smart-342321bc-6be8-47f2-938c-ea56fd835bfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959931249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2959931249
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.396508866
Short name T28
Test name
Test status
Simulation time 43321948 ps
CPU time 1.22 seconds
Started Jul 16 04:56:05 PM PDT 24
Finished Jul 16 04:56:09 PM PDT 24
Peak memory 196948 kb
Host smart-edde21f0-9fc0-4246-aa61-3e1584861e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396508866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.396508866
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.4096334027
Short name T697
Test name
Test status
Simulation time 133166198 ps
CPU time 1.09 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:56:32 PM PDT 24
Peak memory 196248 kb
Host smart-e7a11143-7a06-48ce-bfa1-88d7efd46b65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096334027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.4096334027
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3851489804
Short name T418
Test name
Test status
Simulation time 26300550082 ps
CPU time 95.07 seconds
Started Jul 16 04:56:25 PM PDT 24
Finished Jul 16 04:58:01 PM PDT 24
Peak memory 198484 kb
Host smart-95fd00ae-d721-464e-b8f7-7db7177dcfb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851489804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3851489804
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.419040632
Short name T611
Test name
Test status
Simulation time 34217996 ps
CPU time 0.55 seconds
Started Jul 16 04:56:06 PM PDT 24
Finished Jul 16 04:56:09 PM PDT 24
Peak memory 195472 kb
Host smart-b19629a4-a437-4548-9196-470064e81519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419040632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.419040632
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2010616593
Short name T190
Test name
Test status
Simulation time 20409076 ps
CPU time 0.64 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 194584 kb
Host smart-97542833-ae23-4b8d-bfa6-eb3538fc9084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010616593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2010616593
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.775532496
Short name T116
Test name
Test status
Simulation time 1567972064 ps
CPU time 22.68 seconds
Started Jul 16 04:58:04 PM PDT 24
Finished Jul 16 04:58:27 PM PDT 24
Peak memory 197660 kb
Host smart-b782e506-1cc0-4d98-8caf-84e899a68d42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775532496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.775532496
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2007840952
Short name T343
Test name
Test status
Simulation time 86171321 ps
CPU time 1.02 seconds
Started Jul 16 04:56:03 PM PDT 24
Finished Jul 16 04:56:08 PM PDT 24
Peak memory 197080 kb
Host smart-96163f5a-7b8a-4193-95a0-c08fd03ceebc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007840952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2007840952
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1459259202
Short name T511
Test name
Test status
Simulation time 26911485 ps
CPU time 0.67 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:04 PM PDT 24
Peak memory 194868 kb
Host smart-d2c6107e-a305-4f97-83a5-4526cb0378f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459259202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1459259202
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1549360627
Short name T526
Test name
Test status
Simulation time 225875827 ps
CPU time 2.29 seconds
Started Jul 16 04:55:57 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 198548 kb
Host smart-f7ab671f-43dc-443d-859e-b09bba45595e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549360627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1549360627
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4038889079
Short name T502
Test name
Test status
Simulation time 189249573 ps
CPU time 2.6 seconds
Started Jul 16 04:56:15 PM PDT 24
Finished Jul 16 04:56:18 PM PDT 24
Peak memory 198504 kb
Host smart-54f972ba-541f-41ab-9388-c4e7899657e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038889079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4038889079
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.72725036
Short name T221
Test name
Test status
Simulation time 24966512 ps
CPU time 0.96 seconds
Started Jul 16 04:56:12 PM PDT 24
Finished Jul 16 04:56:14 PM PDT 24
Peak memory 197200 kb
Host smart-dad1f2a4-c8ca-4c4d-a0f6-5bd676bcfca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72725036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.72725036
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2675549763
Short name T519
Test name
Test status
Simulation time 40050816 ps
CPU time 0.84 seconds
Started Jul 16 04:56:10 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 196316 kb
Host smart-4574c001-5956-4299-88ad-9d3a50e5d6c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675549763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2675549763
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1668418384
Short name T179
Test name
Test status
Simulation time 1726935508 ps
CPU time 4.57 seconds
Started Jul 16 04:56:03 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 198560 kb
Host smart-46814117-a0b3-43ea-b74c-c961ea884a89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668418384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1668418384
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.701783336
Short name T589
Test name
Test status
Simulation time 42691778 ps
CPU time 1.11 seconds
Started Jul 16 04:56:08 PM PDT 24
Finished Jul 16 04:56:10 PM PDT 24
Peak memory 196316 kb
Host smart-2c52cc31-b44d-4f63-9a07-6ba24e32044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701783336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.701783336
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.91366712
Short name T679
Test name
Test status
Simulation time 274454132 ps
CPU time 1.28 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:03 PM PDT 24
Peak memory 196888 kb
Host smart-bfd6372b-50ed-4194-a1fd-51d0f07becb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91366712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.91366712
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3083546149
Short name T698
Test name
Test status
Simulation time 21828138747 ps
CPU time 134.44 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:58:20 PM PDT 24
Peak memory 198748 kb
Host smart-33d8f281-6216-4df7-b547-e1ffc76f25e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083546149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3083546149
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.326890460
Short name T510
Test name
Test status
Simulation time 32890076 ps
CPU time 0.56 seconds
Started Jul 16 04:56:16 PM PDT 24
Finished Jul 16 04:56:17 PM PDT 24
Peak memory 194404 kb
Host smart-0ea3f6cc-8a1d-4500-b04b-f642d5292af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326890460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.326890460
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.626751121
Short name T391
Test name
Test status
Simulation time 115348142 ps
CPU time 0.86 seconds
Started Jul 16 04:56:01 PM PDT 24
Finished Jul 16 04:56:07 PM PDT 24
Peak memory 197000 kb
Host smart-ff7a38ad-fbc9-4aa5-b942-2c689eb131a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626751121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.626751121
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3689238692
Short name T310
Test name
Test status
Simulation time 351525869 ps
CPU time 4.29 seconds
Started Jul 16 04:55:56 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 196308 kb
Host smart-182cf4b1-c0d3-4107-b3ee-caaece747605
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689238692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3689238692
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4076821206
Short name T404
Test name
Test status
Simulation time 84932918 ps
CPU time 1.03 seconds
Started Jul 16 04:56:00 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 197112 kb
Host smart-35d3594a-e903-4dff-860f-8d48ce29859e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076821206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4076821206
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1100507317
Short name T29
Test name
Test status
Simulation time 112666804 ps
CPU time 1.34 seconds
Started Jul 16 04:56:12 PM PDT 24
Finished Jul 16 04:56:14 PM PDT 24
Peak memory 197892 kb
Host smart-3553d0e4-7dd3-4fa5-b653-c8bbff5fbf85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100507317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1100507317
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1766494728
Short name T389
Test name
Test status
Simulation time 240554584 ps
CPU time 2.37 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:07 PM PDT 24
Peak memory 198376 kb
Host smart-65334210-20e0-4c2c-b5fb-6ea2d7d33613
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766494728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1766494728
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3579184696
Short name T410
Test name
Test status
Simulation time 274645198 ps
CPU time 1.55 seconds
Started Jul 16 04:56:09 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 196548 kb
Host smart-e3ae8eae-cd4d-47e1-878e-88e19d381c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579184696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3579184696
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1624018309
Short name T321
Test name
Test status
Simulation time 23295415 ps
CPU time 0.93 seconds
Started Jul 16 04:56:18 PM PDT 24
Finished Jul 16 04:56:20 PM PDT 24
Peak memory 196328 kb
Host smart-30b3e3f7-279b-4c52-9bc6-e1be60761644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624018309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1624018309
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1711446245
Short name T394
Test name
Test status
Simulation time 46923690 ps
CPU time 0.7 seconds
Started Jul 16 04:56:04 PM PDT 24
Finished Jul 16 04:56:08 PM PDT 24
Peak memory 195924 kb
Host smart-c48c9baf-d89b-4385-b550-94d35cf0395e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711446245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1711446245
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3251105628
Short name T135
Test name
Test status
Simulation time 143287122 ps
CPU time 2.42 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 198444 kb
Host smart-0c6a4961-892a-496d-8529-01ab6f18acd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251105628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3251105628
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2560963537
Short name T152
Test name
Test status
Simulation time 120808519 ps
CPU time 1 seconds
Started Jul 16 04:55:59 PM PDT 24
Finished Jul 16 04:56:06 PM PDT 24
Peak memory 196176 kb
Host smart-dbda31d7-31f5-431e-83ba-e7fca7c82bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560963537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2560963537
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3392096040
Short name T436
Test name
Test status
Simulation time 186940186 ps
CPU time 1.01 seconds
Started Jul 16 04:56:14 PM PDT 24
Finished Jul 16 04:56:16 PM PDT 24
Peak memory 196632 kb
Host smart-c0699eef-facd-4d27-a6ea-ba8845eacc34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392096040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3392096040
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2352513814
Short name T137
Test name
Test status
Simulation time 82455774160 ps
CPU time 122.11 seconds
Started Jul 16 04:56:11 PM PDT 24
Finished Jul 16 04:58:14 PM PDT 24
Peak memory 198640 kb
Host smart-2d1f92cf-f71b-46f7-8a85-44065111af68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352513814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2352513814
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2922890504
Short name T66
Test name
Test status
Simulation time 105985967536 ps
CPU time 668.14 seconds
Started Jul 16 04:56:02 PM PDT 24
Finished Jul 16 05:07:15 PM PDT 24
Peak memory 198744 kb
Host smart-732b186a-4ad7-4d5b-98a7-c16902815e05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2922890504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2922890504
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2128829535
Short name T476
Test name
Test status
Simulation time 41514543 ps
CPU time 0.6 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:02 PM PDT 24
Peak memory 193684 kb
Host smart-b1f5742b-491d-4861-b896-1bc2272948f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128829535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2128829535
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.775590373
Short name T282
Test name
Test status
Simulation time 28273984 ps
CPU time 0.72 seconds
Started Jul 16 04:56:16 PM PDT 24
Finished Jul 16 04:56:18 PM PDT 24
Peak memory 196440 kb
Host smart-3248b95b-1de6-4391-b168-39438adc4608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775590373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.775590373
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1943899299
Short name T188
Test name
Test status
Simulation time 604464013 ps
CPU time 5.15 seconds
Started Jul 16 04:56:00 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 196044 kb
Host smart-3b01233d-ba72-45fd-bdf5-8a77cddc5bc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943899299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1943899299
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2045756987
Short name T129
Test name
Test status
Simulation time 239914084 ps
CPU time 0.85 seconds
Started Jul 16 04:56:14 PM PDT 24
Finished Jul 16 04:56:15 PM PDT 24
Peak memory 196516 kb
Host smart-417e0b1c-aca6-421d-95e3-48836cf393b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045756987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2045756987
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3925275429
Short name T683
Test name
Test status
Simulation time 151745140 ps
CPU time 1.31 seconds
Started Jul 16 04:56:12 PM PDT 24
Finished Jul 16 04:56:14 PM PDT 24
Peak memory 198676 kb
Host smart-628183d1-4407-4823-bdef-a8f583a1e8c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925275429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3925275429
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2607638725
Short name T615
Test name
Test status
Simulation time 490568411 ps
CPU time 1.37 seconds
Started Jul 16 04:56:09 PM PDT 24
Finished Jul 16 04:56:11 PM PDT 24
Peak memory 196944 kb
Host smart-858ba4cd-912e-466c-ad86-77202abbfd1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607638725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2607638725
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3412402762
Short name T558
Test name
Test status
Simulation time 50293841 ps
CPU time 1.15 seconds
Started Jul 16 04:56:13 PM PDT 24
Finished Jul 16 04:56:14 PM PDT 24
Peak memory 196908 kb
Host smart-23f7ddca-d060-4046-9465-118c4801eda9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412402762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3412402762
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.375319012
Short name T280
Test name
Test status
Simulation time 194902790 ps
CPU time 1.1 seconds
Started Jul 16 04:56:22 PM PDT 24
Finished Jul 16 04:56:24 PM PDT 24
Peak memory 197280 kb
Host smart-48359010-86ae-4dfa-99d0-c7299158bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375319012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.375319012
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.476745621
Short name T380
Test name
Test status
Simulation time 120937252 ps
CPU time 1.18 seconds
Started Jul 16 04:56:16 PM PDT 24
Finished Jul 16 04:56:18 PM PDT 24
Peak memory 197420 kb
Host smart-897e6305-f960-4864-ac90-92fea95307f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476745621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.476745621
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.428735439
Short name T9
Test name
Test status
Simulation time 551718363 ps
CPU time 1.96 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 198428 kb
Host smart-a2fa1cef-083e-4a38-9756-1d81e14d53f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428735439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.428735439
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1257726696
Short name T284
Test name
Test status
Simulation time 43881766 ps
CPU time 1.16 seconds
Started Jul 16 04:56:20 PM PDT 24
Finished Jul 16 04:56:22 PM PDT 24
Peak memory 196540 kb
Host smart-cd40b928-25f0-4afe-a3cc-dc05389d77d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257726696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1257726696
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1635077982
Short name T469
Test name
Test status
Simulation time 332213332 ps
CPU time 1.45 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 04:56:28 PM PDT 24
Peak memory 198488 kb
Host smart-48a890b4-f02b-4c14-9b07-07f9de0564a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635077982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1635077982
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1770415187
Short name T272
Test name
Test status
Simulation time 9464826214 ps
CPU time 34.81 seconds
Started Jul 16 04:56:05 PM PDT 24
Finished Jul 16 04:56:43 PM PDT 24
Peak memory 198580 kb
Host smart-3b13d8d2-4274-4f17-a84b-c9a93b72fc01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770415187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1770415187
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1129546313
Short name T440
Test name
Test status
Simulation time 785959195212 ps
CPU time 1545.03 seconds
Started Jul 16 04:56:27 PM PDT 24
Finished Jul 16 05:22:13 PM PDT 24
Peak memory 198852 kb
Host smart-94808f02-7f22-4478-855b-23547edb4eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1129546313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1129546313
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2627458385
Short name T575
Test name
Test status
Simulation time 47752818 ps
CPU time 0.56 seconds
Started Jul 16 04:56:20 PM PDT 24
Finished Jul 16 04:56:22 PM PDT 24
Peak memory 194708 kb
Host smart-26017e23-570f-49a2-983e-4009cc262b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627458385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2627458385
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.14290757
Short name T168
Test name
Test status
Simulation time 93704561 ps
CPU time 0.71 seconds
Started Jul 16 04:56:28 PM PDT 24
Finished Jul 16 04:56:30 PM PDT 24
Peak memory 195352 kb
Host smart-4287139d-4a8f-4ce3-b086-41aa2ca6db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14290757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.14290757
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.762748087
Short name T134
Test name
Test status
Simulation time 439087316 ps
CPU time 5.57 seconds
Started Jul 16 04:56:10 PM PDT 24
Finished Jul 16 04:56:16 PM PDT 24
Peak memory 197112 kb
Host smart-935bcea8-5cd5-46d2-a5f8-5eb42c7b5db1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762748087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.762748087
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2826581556
Short name T673
Test name
Test status
Simulation time 67413631 ps
CPU time 0.92 seconds
Started Jul 16 04:56:03 PM PDT 24
Finished Jul 16 04:56:08 PM PDT 24
Peak memory 197592 kb
Host smart-3c9feff8-8962-4f51-908e-f2b673c93c14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826581556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2826581556
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.739952356
Short name T185
Test name
Test status
Simulation time 46690704 ps
CPU time 0.87 seconds
Started Jul 16 04:56:11 PM PDT 24
Finished Jul 16 04:56:13 PM PDT 24
Peak memory 196156 kb
Host smart-3181225b-853f-4dc8-adad-87cd57c83a95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739952356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.739952356
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2789781633
Short name T165
Test name
Test status
Simulation time 27206075 ps
CPU time 1.07 seconds
Started Jul 16 04:56:21 PM PDT 24
Finished Jul 16 04:56:23 PM PDT 24
Peak memory 196808 kb
Host smart-8a29c955-b129-408b-87b7-5a2f8ea1fb0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789781633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2789781633
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2422018224
Short name T332
Test name
Test status
Simulation time 66090644 ps
CPU time 1 seconds
Started Jul 16 04:56:21 PM PDT 24
Finished Jul 16 04:56:23 PM PDT 24
Peak memory 195972 kb
Host smart-da442545-51e2-4811-b155-8af62634422b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422018224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2422018224
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.683595668
Short name T643
Test name
Test status
Simulation time 105798114 ps
CPU time 0.79 seconds
Started Jul 16 04:56:17 PM PDT 24
Finished Jul 16 04:56:19 PM PDT 24
Peak memory 195856 kb
Host smart-a457c42c-40d7-4baf-b8f9-5e8b5ca2f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683595668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.683595668
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3017590450
Short name T251
Test name
Test status
Simulation time 73882757 ps
CPU time 1.2 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 04:56:28 PM PDT 24
Peak memory 197040 kb
Host smart-451f5a3d-5adf-4f75-ab10-4553cdcb7c53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017590450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3017590450
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2590983924
Short name T324
Test name
Test status
Simulation time 45005088 ps
CPU time 1.07 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 198448 kb
Host smart-f3c93f37-901d-4727-9e7e-d770edc8a9a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590983924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2590983924
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4290763498
Short name T630
Test name
Test status
Simulation time 112772734 ps
CPU time 1.06 seconds
Started Jul 16 04:56:27 PM PDT 24
Finished Jul 16 04:56:28 PM PDT 24
Peak memory 196316 kb
Host smart-30120cb9-1000-4152-aed2-3f608c59d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290763498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4290763498
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.316551440
Short name T25
Test name
Test status
Simulation time 60474271 ps
CPU time 1 seconds
Started Jul 16 04:56:20 PM PDT 24
Finished Jul 16 04:56:22 PM PDT 24
Peak memory 196912 kb
Host smart-bbbcae06-a35d-45f7-a6cf-13a32ade782a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316551440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.316551440
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1804959184
Short name T659
Test name
Test status
Simulation time 32508124786 ps
CPU time 203.12 seconds
Started Jul 16 04:56:02 PM PDT 24
Finished Jul 16 04:59:30 PM PDT 24
Peak memory 198628 kb
Host smart-aabd57b4-933a-449d-83b7-20fa77797eeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804959184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1804959184
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3798333518
Short name T548
Test name
Test status
Simulation time 44684856 ps
CPU time 0.55 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 195464 kb
Host smart-806e62c9-90c7-4ab7-8c32-3aeae0cfaf1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798333518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3798333518
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2230160651
Short name T43
Test name
Test status
Simulation time 82893398 ps
CPU time 0.9 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:54:59 PM PDT 24
Peak memory 197000 kb
Host smart-b9634db6-de94-422b-9aa5-3625ebfb0042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230160651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2230160651
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.281594118
Short name T613
Test name
Test status
Simulation time 2543123349 ps
CPU time 20.37 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:55:17 PM PDT 24
Peak memory 198924 kb
Host smart-c47ff5e8-8b8f-4b4f-99de-ca2af09c79fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281594118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.281594118
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2903719102
Short name T3
Test name
Test status
Simulation time 157806300 ps
CPU time 0.96 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 197180 kb
Host smart-0d93459d-7d34-47d6-b0ea-ae21cbd75228
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903719102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2903719102
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3390339760
Short name T470
Test name
Test status
Simulation time 23621783 ps
CPU time 0.8 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:55 PM PDT 24
Peak memory 196188 kb
Host smart-a24057df-3b5a-4729-9d85-95cfa9a02a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390339760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3390339760
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2588443332
Short name T228
Test name
Test status
Simulation time 77809589 ps
CPU time 2.98 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 198620 kb
Host smart-d89c57d1-7c3e-4ffd-9885-33f639f04ad5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588443332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2588443332
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.273387900
Short name T427
Test name
Test status
Simulation time 198701017 ps
CPU time 2.96 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:05 PM PDT 24
Peak memory 197688 kb
Host smart-564081d6-f765-49c6-b61e-bcbbc52abb2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273387900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.273387900
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2404153076
Short name T625
Test name
Test status
Simulation time 38140887 ps
CPU time 0.9 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:56 PM PDT 24
Peak memory 196360 kb
Host smart-590958ba-ac02-4481-ae0b-aa520abb8e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404153076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2404153076
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1820743167
Short name T496
Test name
Test status
Simulation time 35865007 ps
CPU time 1.2 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 197496 kb
Host smart-fd8f5f02-b810-4e69-b9ad-7d018c91fe2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820743167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1820743167
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1336290194
Short name T15
Test name
Test status
Simulation time 221407534 ps
CPU time 2.88 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:56 PM PDT 24
Peak memory 198828 kb
Host smart-7dc18734-5bba-46bd-8e1b-887db6e3553f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336290194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1336290194
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2912433491
Short name T671
Test name
Test status
Simulation time 249312232 ps
CPU time 1.19 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:54:59 PM PDT 24
Peak memory 196292 kb
Host smart-646c9c7d-6a1f-4960-8e26-031b44f47fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912433491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2912433491
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3466272255
Short name T594
Test name
Test status
Simulation time 32088220 ps
CPU time 0.79 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 195780 kb
Host smart-3aa9e966-eb78-4cf2-95b5-456fb086ac43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466272255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3466272255
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.936663839
Short name T233
Test name
Test status
Simulation time 4555480576 ps
CPU time 117.66 seconds
Started Jul 16 04:55:09 PM PDT 24
Finished Jul 16 04:57:09 PM PDT 24
Peak memory 198588 kb
Host smart-80873ff9-8298-4394-b342-9e849a0e5b56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936663839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.936663839
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1765475874
Short name T623
Test name
Test status
Simulation time 47724659026 ps
CPU time 1035.28 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 05:12:18 PM PDT 24
Peak memory 198812 kb
Host smart-3385d2bd-02cf-4454-8f40-b31f0795fb19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1765475874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1765475874
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3804060471
Short name T409
Test name
Test status
Simulation time 49897712 ps
CPU time 0.58 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 194476 kb
Host smart-ba920cbb-32b0-4d8e-b377-c576c5247071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804060471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3804060471
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.725926788
Short name T160
Test name
Test status
Simulation time 20026667 ps
CPU time 0.64 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 194788 kb
Host smart-09e6a066-d886-4467-b29d-7b46d38d0b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725926788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.725926788
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3127794571
Short name T677
Test name
Test status
Simulation time 1409539704 ps
CPU time 22.99 seconds
Started Jul 16 04:54:46 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 198800 kb
Host smart-3d696b9d-f4da-4795-8ff5-5a9c50bebba0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127794571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3127794571
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.4271169292
Short name T665
Test name
Test status
Simulation time 45476515 ps
CPU time 0.61 seconds
Started Jul 16 04:55:05 PM PDT 24
Finished Jul 16 04:55:09 PM PDT 24
Peak memory 194908 kb
Host smart-b5fcd9ac-4115-4114-9676-20bd8e4e8e4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271169292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.4271169292
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2699447018
Short name T121
Test name
Test status
Simulation time 444503438 ps
CPU time 1.34 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 197664 kb
Host smart-b952f9d9-9c9e-4e1c-9b18-14695630678d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699447018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2699447018
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1096312101
Short name T118
Test name
Test status
Simulation time 381817515 ps
CPU time 3.58 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 198488 kb
Host smart-2114144e-f388-49c4-9c60-ce44cd6a3603
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096312101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1096312101
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1872079119
Short name T556
Test name
Test status
Simulation time 141454398 ps
CPU time 1.62 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 196436 kb
Host smart-95b8bbad-0d81-4d08-b6fc-753a765df6ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872079119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1872079119
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2856000488
Short name T209
Test name
Test status
Simulation time 533634852 ps
CPU time 0.84 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 197048 kb
Host smart-cfb54b11-1161-43fb-8387-3d52202781d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856000488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2856000488
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.204952961
Short name T573
Test name
Test status
Simulation time 327974721 ps
CPU time 1.25 seconds
Started Jul 16 04:54:47 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 198580 kb
Host smart-005fbdd7-4340-4b43-b15a-217d784c9e54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204952961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.204952961
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.449343925
Short name T290
Test name
Test status
Simulation time 321615824 ps
CPU time 4.04 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 198488 kb
Host smart-b062ce9c-c3f4-457d-9475-1ed93dfac6be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449343925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.449343925
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3762224918
Short name T486
Test name
Test status
Simulation time 30457224 ps
CPU time 0.69 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 195788 kb
Host smart-33f6e7a8-771b-4ac0-8144-b9944e560a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762224918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3762224918
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3800993670
Short name T649
Test name
Test status
Simulation time 140984756 ps
CPU time 0.86 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 197692 kb
Host smart-04178e52-597d-4234-ba7b-c61fdb0597a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800993670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3800993670
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1570441091
Short name T707
Test name
Test status
Simulation time 19231060023 ps
CPU time 99.78 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:56:33 PM PDT 24
Peak memory 198596 kb
Host smart-2a1f9bcc-66c9-4e63-aece-004ce0ce2a92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570441091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1570441091
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3717839174
Short name T64
Test name
Test status
Simulation time 48938226389 ps
CPU time 1208.32 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 05:15:02 PM PDT 24
Peak memory 198564 kb
Host smart-4ed91ba2-dd76-4344-b057-169f7d7441ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3717839174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3717839174
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2586138793
Short name T163
Test name
Test status
Simulation time 41717437 ps
CPU time 0.56 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 194428 kb
Host smart-d74e3f33-4594-422f-9d26-212d0d04edea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586138793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2586138793
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.187865636
Short name T257
Test name
Test status
Simulation time 58240929 ps
CPU time 0.85 seconds
Started Jul 16 04:54:50 PM PDT 24
Finished Jul 16 04:54:52 PM PDT 24
Peak memory 196788 kb
Host smart-2d31e227-3ac7-4807-95a6-97a40b8d92a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187865636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.187865636
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1148539333
Short name T153
Test name
Test status
Simulation time 413491931 ps
CPU time 15.44 seconds
Started Jul 16 04:54:51 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 198492 kb
Host smart-b0cdd22f-7724-461c-8ee3-60a427a53b8d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148539333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1148539333
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2312588459
Short name T128
Test name
Test status
Simulation time 93085487 ps
CPU time 0.68 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 195856 kb
Host smart-ea59fefa-7110-4aba-8f06-681714f16da3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312588459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2312588459
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4249129361
Short name T31
Test name
Test status
Simulation time 285503711 ps
CPU time 1.19 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:02 PM PDT 24
Peak memory 195612 kb
Host smart-3acc09f5-4c09-46d1-b933-2ca14b395628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249129361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4249129361
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.262617120
Short name T193
Test name
Test status
Simulation time 524208491 ps
CPU time 3.19 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:55:00 PM PDT 24
Peak memory 198404 kb
Host smart-7055bb86-d57e-4d1e-bbe0-d2c5af233a39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262617120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.262617120
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2842505428
Short name T398
Test name
Test status
Simulation time 148474153 ps
CPU time 2.28 seconds
Started Jul 16 04:55:05 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 198636 kb
Host smart-dd9cf18b-9688-4642-be2f-9d57caabedb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842505428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2842505428
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.38016998
Short name T642
Test name
Test status
Simulation time 241953393 ps
CPU time 1.25 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 197444 kb
Host smart-84c7a91b-d004-437f-9a92-400e541488c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38016998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.38016998
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.32836866
Short name T202
Test name
Test status
Simulation time 139011724 ps
CPU time 1.22 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 197424 kb
Host smart-cc09e0a3-13a3-418c-b0b3-8c674e5e445b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32836866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_p
ulldown.32836866
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2279736375
Short name T17
Test name
Test status
Simulation time 607857940 ps
CPU time 5.49 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:06 PM PDT 24
Peak memory 197612 kb
Host smart-8343a850-bba1-4761-b403-4318861e21d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279736375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2279736375
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3262480296
Short name T246
Test name
Test status
Simulation time 60936847 ps
CPU time 0.86 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 196812 kb
Host smart-583eda84-c1dc-43f2-b987-edd1041cd9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262480296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3262480296
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1754976892
Short name T522
Test name
Test status
Simulation time 294700119 ps
CPU time 1.24 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:54 PM PDT 24
Peak memory 198896 kb
Host smart-b37d355d-4632-48c0-9c5c-05a3fa34e07b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754976892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1754976892
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.305113203
Short name T638
Test name
Test status
Simulation time 20609959011 ps
CPU time 217.88 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:58:33 PM PDT 24
Peak memory 198544 kb
Host smart-6a6a5c68-43e9-4393-a886-b4c1b69dbb73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305113203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.305113203
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1004706725
Short name T624
Test name
Test status
Simulation time 19752967 ps
CPU time 0.55 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 194492 kb
Host smart-350a58cf-52f4-4dee-9765-1e115f7a5208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004706725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1004706725
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1736969548
Short name T426
Test name
Test status
Simulation time 21935907 ps
CPU time 0.7 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 194468 kb
Host smart-7b72e972-856f-4a5d-8965-5fdc831b005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736969548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1736969548
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1757576501
Short name T236
Test name
Test status
Simulation time 1748666190 ps
CPU time 12.52 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 197628 kb
Host smart-05ad2c6c-a6c2-4d5f-b0e2-bd19b7d43d66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757576501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1757576501
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3735298522
Short name T478
Test name
Test status
Simulation time 153869923 ps
CPU time 0.77 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 195300 kb
Host smart-55a17d3a-ca47-474c-bce5-ac507e16d796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735298522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3735298522
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.665130225
Short name T328
Test name
Test status
Simulation time 28567702 ps
CPU time 0.85 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 196812 kb
Host smart-ccc61b02-d705-4427-985c-5ac350097358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665130225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.665130225
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.420237127
Short name T141
Test name
Test status
Simulation time 190060483 ps
CPU time 2.1 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 198364 kb
Host smart-3f39a10c-2d1c-47ea-b210-efd5f2aabb9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420237127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.420237127
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.442156578
Short name T71
Test name
Test status
Simulation time 544884126 ps
CPU time 2.5 seconds
Started Jul 16 04:55:05 PM PDT 24
Finished Jul 16 04:55:11 PM PDT 24
Peak memory 197640 kb
Host smart-5d20fa8e-385a-429b-a6cd-b755390563b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442156578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.442156578
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3325739299
Short name T67
Test name
Test status
Simulation time 86731417 ps
CPU time 1.26 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:54:59 PM PDT 24
Peak memory 197572 kb
Host smart-e1aa8f7a-6a26-4a6b-96d5-c19583a30c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325739299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3325739299
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2237172519
Short name T593
Test name
Test status
Simulation time 109240443 ps
CPU time 1.3 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:56 PM PDT 24
Peak memory 197576 kb
Host smart-ab17843d-f331-4822-a3a7-e8835fa3f356
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237172519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2237172519
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3287499005
Short name T240
Test name
Test status
Simulation time 894347782 ps
CPU time 5.39 seconds
Started Jul 16 04:54:59 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 198452 kb
Host smart-5a22d76c-022d-4ad5-8cfc-02a9af7207ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287499005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3287499005
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1399798128
Short name T156
Test name
Test status
Simulation time 73028581 ps
CPU time 1.29 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 196100 kb
Host smart-3c854005-4a9f-4f08-b166-42a356dfbc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399798128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1399798128
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.489825080
Short name T374
Test name
Test status
Simulation time 194832561 ps
CPU time 1.31 seconds
Started Jul 16 04:54:56 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 198488 kb
Host smart-0c748024-8b21-44cb-acd9-bdee43d1ee09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489825080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.489825080
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.685635828
Short name T248
Test name
Test status
Simulation time 11944296762 ps
CPU time 83.53 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:56:29 PM PDT 24
Peak memory 198628 kb
Host smart-e070a0fd-d957-4e4e-992e-202819e9242e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685635828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.685635828
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3893919479
Short name T62
Test name
Test status
Simulation time 107322552903 ps
CPU time 813.29 seconds
Started Jul 16 04:55:10 PM PDT 24
Finished Jul 16 05:08:45 PM PDT 24
Peak memory 198736 kb
Host smart-08e73952-19f7-4660-87d0-832a904b1c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3893919479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3893919479
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2163978555
Short name T592
Test name
Test status
Simulation time 42508464 ps
CPU time 0.58 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 194656 kb
Host smart-ac8762b3-75d9-4477-bab9-178093f5bd36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163978555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2163978555
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2913376169
Short name T546
Test name
Test status
Simulation time 47427530 ps
CPU time 0.77 seconds
Started Jul 16 04:55:15 PM PDT 24
Finished Jul 16 04:55:16 PM PDT 24
Peak memory 195844 kb
Host smart-1c683c68-dedb-4745-8dd8-119847dc8d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913376169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2913376169
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.4282883270
Short name T489
Test name
Test status
Simulation time 1344744200 ps
CPU time 18.31 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:23 PM PDT 24
Peak memory 197428 kb
Host smart-b3cff5e4-9907-4747-829e-3ac44afd6ab2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282883270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.4282883270
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.574416202
Short name T441
Test name
Test status
Simulation time 134157151 ps
CPU time 0.75 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 196396 kb
Host smart-821c4675-afff-413c-8fca-a89626d82956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574416202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.574416202
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.631771397
Short name T667
Test name
Test status
Simulation time 968584208 ps
CPU time 1.01 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 196488 kb
Host smart-dc927dfe-5d1f-47b2-8bf1-57534ef666f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631771397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.631771397
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2291219561
Short name T304
Test name
Test status
Simulation time 208854974 ps
CPU time 2.2 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 198608 kb
Host smart-6f636bb2-2092-47b0-969d-1f0a18bfac45
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291219561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2291219561
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.513030062
Short name T341
Test name
Test status
Simulation time 240888631 ps
CPU time 1.44 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:55 PM PDT 24
Peak memory 197120 kb
Host smart-3cd725c4-3912-4398-a097-3ee0e265102d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513030062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.513030062
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1586204397
Short name T474
Test name
Test status
Simulation time 36583732 ps
CPU time 1.2 seconds
Started Jul 16 04:55:01 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 198480 kb
Host smart-852e0a36-1ca1-462f-a59c-06b4fec4d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586204397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1586204397
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2379550645
Short name T614
Test name
Test status
Simulation time 99382316 ps
CPU time 0.76 seconds
Started Jul 16 04:55:12 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 195792 kb
Host smart-0ed9d4b2-a5fe-4b6c-94f9-ecefbe047596
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379550645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2379550645
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.737405063
Short name T533
Test name
Test status
Simulation time 625296188 ps
CPU time 7.56 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:53 PM PDT 24
Peak memory 198440 kb
Host smart-90a218e6-3e97-461b-acd8-3a7038ee3e9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737405063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.737405063
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1711095073
Short name T125
Test name
Test status
Simulation time 385027340 ps
CPU time 1.22 seconds
Started Jul 16 04:54:54 PM PDT 24
Finished Jul 16 04:54:58 PM PDT 24
Peak memory 196880 kb
Host smart-f7ecc845-e79f-4343-adf4-59a3690b3c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711095073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1711095073
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.856081767
Short name T561
Test name
Test status
Simulation time 403892304 ps
CPU time 1.33 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 197228 kb
Host smart-721ad041-948f-40dd-a412-fed8bffd5081
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856081767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.856081767
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2327030495
Short name T603
Test name
Test status
Simulation time 6869178646 ps
CPU time 42.08 seconds
Started Jul 16 04:54:55 PM PDT 24
Finished Jul 16 04:55:40 PM PDT 24
Peak memory 198548 kb
Host smart-2d85b92b-9ac2-4aa3-a3f8-58441ff6c612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327030495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2327030495
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.408476794
Short name T875
Test name
Test status
Simulation time 96395435 ps
CPU time 0.99 seconds
Started Jul 16 05:28:42 PM PDT 24
Finished Jul 16 05:28:44 PM PDT 24
Peak memory 198396 kb
Host smart-6041985d-5ff9-4ce1-9261-a647fcc42a69
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=408476794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.408476794
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1995878652
Short name T885
Test name
Test status
Simulation time 65473966 ps
CPU time 1.06 seconds
Started Jul 16 05:32:35 PM PDT 24
Finished Jul 16 05:32:37 PM PDT 24
Peak memory 196964 kb
Host smart-52ac534f-692f-45c3-9c83-6a0a96ab5e95
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995878652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1995878652
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3511617539
Short name T928
Test name
Test status
Simulation time 280051897 ps
CPU time 1.18 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:29:01 PM PDT 24
Peak memory 197120 kb
Host smart-f7f90962-2568-49ab-810d-2fcb72860723
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3511617539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3511617539
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3472752185
Short name T935
Test name
Test status
Simulation time 84652110 ps
CPU time 1.23 seconds
Started Jul 16 05:28:43 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 196096 kb
Host smart-cc19e7ae-68b3-42e8-a0ca-c97089c09afd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472752185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3472752185
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.992511004
Short name T894
Test name
Test status
Simulation time 136025579 ps
CPU time 0.83 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 196424 kb
Host smart-626a0100-1aec-4e3c-8d49-b4ce34985447
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=992511004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.992511004
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4014617281
Short name T925
Test name
Test status
Simulation time 554946073 ps
CPU time 1.33 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:29:01 PM PDT 24
Peak memory 196932 kb
Host smart-f5ab3225-cadd-4c00-8d73-c58928825ebd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014617281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4014617281
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.836910126
Short name T921
Test name
Test status
Simulation time 75310673 ps
CPU time 1.18 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:37 PM PDT 24
Peak memory 196988 kb
Host smart-eea50668-7970-47c1-849b-758a396e12ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=836910126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.836910126
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1901985609
Short name T910
Test name
Test status
Simulation time 73197166 ps
CPU time 1.01 seconds
Started Jul 16 05:36:34 PM PDT 24
Finished Jul 16 05:36:36 PM PDT 24
Peak memory 197176 kb
Host smart-1496abc4-d518-4697-9a64-8bcbd81ef669
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901985609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1901985609
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3106720492
Short name T877
Test name
Test status
Simulation time 127880819 ps
CPU time 1.21 seconds
Started Jul 16 05:36:24 PM PDT 24
Finished Jul 16 05:36:26 PM PDT 24
Peak memory 198420 kb
Host smart-5c9875eb-2bf4-46d9-bc43-119e19c3d9d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3106720492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3106720492
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319656063
Short name T892
Test name
Test status
Simulation time 43929255 ps
CPU time 0.93 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:29:01 PM PDT 24
Peak memory 196940 kb
Host smart-6480fa66-8e4e-4da1-9fef-9f2184d467d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319656063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2319656063
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3217752844
Short name T884
Test name
Test status
Simulation time 180108129 ps
CPU time 1.32 seconds
Started Jul 16 05:28:58 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 197056 kb
Host smart-7f796bad-67ca-49bb-907f-ee2ed5b9785b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3217752844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3217752844
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2942181634
Short name T901
Test name
Test status
Simulation time 76729261 ps
CPU time 0.87 seconds
Started Jul 16 05:28:55 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 195676 kb
Host smart-18014fa0-ea54-46cc-9e3f-e038303258d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942181634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2942181634
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3119642741
Short name T929
Test name
Test status
Simulation time 71027422 ps
CPU time 1.29 seconds
Started Jul 16 05:28:57 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 197004 kb
Host smart-d1a64b50-509e-4ea0-a5b1-73e2aa74ee8e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3119642741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3119642741
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975300405
Short name T913
Test name
Test status
Simulation time 210208261 ps
CPU time 1.5 seconds
Started Jul 16 05:28:58 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 197008 kb
Host smart-ac516f3c-fd33-4415-a5da-f34539ed6207
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975300405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3975300405
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1614548767
Short name T900
Test name
Test status
Simulation time 97189369 ps
CPU time 1 seconds
Started Jul 16 05:36:52 PM PDT 24
Finished Jul 16 05:36:54 PM PDT 24
Peak memory 198408 kb
Host smart-28aef11f-b1fc-4a22-a94f-9ad7031bb2cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1614548767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1614548767
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.114282938
Short name T861
Test name
Test status
Simulation time 83380933 ps
CPU time 1.07 seconds
Started Jul 16 05:28:58 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 191976 kb
Host smart-869d1188-8a29-4811-a010-a86104ff7510
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114282938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.114282938
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2191284456
Short name T888
Test name
Test status
Simulation time 326285698 ps
CPU time 1.05 seconds
Started Jul 16 05:28:56 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 197128 kb
Host smart-79b95d5e-cb9d-43f5-bdf3-bb55b60609bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2191284456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2191284456
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1430012667
Short name T937
Test name
Test status
Simulation time 197846864 ps
CPU time 1.32 seconds
Started Jul 16 05:36:53 PM PDT 24
Finished Jul 16 05:36:55 PM PDT 24
Peak memory 196988 kb
Host smart-c2dd04de-72f8-4c5e-9865-ce18478a9c03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430012667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1430012667
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3989243984
Short name T907
Test name
Test status
Simulation time 146984394 ps
CPU time 1.14 seconds
Started Jul 16 05:28:57 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 197208 kb
Host smart-8a02b900-28d1-4cdd-a31b-0044e54a4fcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3989243984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3989243984
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3430980777
Short name T915
Test name
Test status
Simulation time 230064217 ps
CPU time 1.37 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:28:56 PM PDT 24
Peak memory 197280 kb
Host smart-01592183-77be-4221-9c1b-75c4563e898a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430980777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3430980777
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2306410076
Short name T927
Test name
Test status
Simulation time 440580541 ps
CPU time 1.02 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:28:58 PM PDT 24
Peak memory 197708 kb
Host smart-e1e9da49-6ddb-446e-b006-10d52c0db1a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2306410076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2306410076
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.434758601
Short name T924
Test name
Test status
Simulation time 57598331 ps
CPU time 1.15 seconds
Started Jul 16 05:36:51 PM PDT 24
Finished Jul 16 05:36:54 PM PDT 24
Peak memory 196260 kb
Host smart-109df4e6-1bb9-45f0-aba1-26f872454ede
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434758601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.434758601
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3337550450
Short name T873
Test name
Test status
Simulation time 141136281 ps
CPU time 1.28 seconds
Started Jul 16 05:36:53 PM PDT 24
Finished Jul 16 05:36:56 PM PDT 24
Peak memory 197268 kb
Host smart-cee9d290-b420-4229-b0ff-3a9f7c36e7b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3337550450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3337550450
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2258126271
Short name T844
Test name
Test status
Simulation time 48644677 ps
CPU time 0.82 seconds
Started Jul 16 05:28:57 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 196436 kb
Host smart-3b630c56-158b-42a0-99da-b3b3393f0243
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258126271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2258126271
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1344491278
Short name T850
Test name
Test status
Simulation time 37609632 ps
CPU time 0.99 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:28:59 PM PDT 24
Peak memory 197052 kb
Host smart-24dd3e36-2e00-464d-a804-9f8f87074c5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1344491278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1344491278
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1875031795
Short name T870
Test name
Test status
Simulation time 154681999 ps
CPU time 1.12 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 195948 kb
Host smart-520a452a-871d-4642-b83e-245942127701
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875031795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1875031795
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2193978773
Short name T887
Test name
Test status
Simulation time 54934008 ps
CPU time 1.16 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:29:02 PM PDT 24
Peak memory 198356 kb
Host smart-f70b0167-1ad7-478a-b838-cdfb687be13d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2193978773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2193978773
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.552181497
Short name T853
Test name
Test status
Simulation time 69210830 ps
CPU time 1.24 seconds
Started Jul 16 05:32:31 PM PDT 24
Finished Jul 16 05:32:33 PM PDT 24
Peak memory 197168 kb
Host smart-5f92b4ee-4704-4196-a8ee-21aa38cf0e26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552181497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.552181497
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2608776879
Short name T869
Test name
Test status
Simulation time 64153537 ps
CPU time 0.85 seconds
Started Jul 16 05:28:59 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 195724 kb
Host smart-9b7a0c49-4d9e-469f-961e-f05b61bf8598
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2608776879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2608776879
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2115995140
Short name T883
Test name
Test status
Simulation time 76991811 ps
CPU time 1.32 seconds
Started Jul 16 05:28:58 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 198428 kb
Host smart-d24d2a51-3d91-447e-b074-5973b3f3476b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115995140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2115995140
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1254645084
Short name T930
Test name
Test status
Simulation time 30153991 ps
CPU time 0.97 seconds
Started Jul 16 05:28:57 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 197884 kb
Host smart-fcd0a8e8-e96d-48ba-80aa-39ad43677bca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1254645084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1254645084
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2824693897
Short name T895
Test name
Test status
Simulation time 85556890 ps
CPU time 0.84 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:28:57 PM PDT 24
Peak memory 195880 kb
Host smart-e29903a1-2eef-42d4-8023-3ef32214a3af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824693897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2824693897
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1148337212
Short name T897
Test name
Test status
Simulation time 93629762 ps
CPU time 1.01 seconds
Started Jul 16 05:28:53 PM PDT 24
Finished Jul 16 05:28:55 PM PDT 24
Peak memory 198288 kb
Host smart-3b85dfd5-b27d-4b4f-bdc6-5ac78555a584
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1148337212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1148337212
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3843183138
Short name T932
Test name
Test status
Simulation time 124414460 ps
CPU time 1.13 seconds
Started Jul 16 05:36:40 PM PDT 24
Finished Jul 16 05:36:43 PM PDT 24
Peak memory 197028 kb
Host smart-32d636bc-05da-4eae-8760-e8321a07bad8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843183138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3843183138
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1549486503
Short name T882
Test name
Test status
Simulation time 58564168 ps
CPU time 1.05 seconds
Started Jul 16 05:36:52 PM PDT 24
Finished Jul 16 05:36:54 PM PDT 24
Peak memory 196236 kb
Host smart-4cc0b635-237a-4337-bda9-ccf277eadbad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1549486503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1549486503
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.898452693
Short name T917
Test name
Test status
Simulation time 58003068 ps
CPU time 1.27 seconds
Started Jul 16 05:35:51 PM PDT 24
Finished Jul 16 05:35:52 PM PDT 24
Peak memory 197020 kb
Host smart-79dfa422-5675-4d81-805f-e97edb9608a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898452693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.898452693
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3655539942
Short name T868
Test name
Test status
Simulation time 191166699 ps
CPU time 0.92 seconds
Started Jul 16 05:33:54 PM PDT 24
Finished Jul 16 05:33:55 PM PDT 24
Peak memory 197420 kb
Host smart-c7ef2428-f9ae-470b-9bcd-9b6256677ec0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3655539942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3655539942
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3506685037
Short name T903
Test name
Test status
Simulation time 149593667 ps
CPU time 0.85 seconds
Started Jul 16 05:32:29 PM PDT 24
Finished Jul 16 05:32:32 PM PDT 24
Peak memory 196000 kb
Host smart-1adcd531-266b-4c75-b2d8-819ba9b639d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506685037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3506685037
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2571238446
Short name T867
Test name
Test status
Simulation time 27614605 ps
CPU time 0.79 seconds
Started Jul 16 05:36:24 PM PDT 24
Finished Jul 16 05:36:25 PM PDT 24
Peak memory 196624 kb
Host smart-5c07f3f9-9975-4dee-bdc8-55cd7c86dfc6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2571238446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2571238446
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3554635384
Short name T891
Test name
Test status
Simulation time 50501534 ps
CPU time 1.01 seconds
Started Jul 16 05:35:51 PM PDT 24
Finished Jul 16 05:35:52 PM PDT 24
Peak memory 197072 kb
Host smart-0febc1cc-ca79-4804-b398-dd058819c5d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554635384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3554635384
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1106366485
Short name T934
Test name
Test status
Simulation time 42054033 ps
CPU time 0.84 seconds
Started Jul 16 05:28:56 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 195900 kb
Host smart-9a89d376-8dfa-4d2e-b2a9-e351ea3500d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1106366485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1106366485
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2655451891
Short name T912
Test name
Test status
Simulation time 236922090 ps
CPU time 1.17 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:29:01 PM PDT 24
Peak memory 197008 kb
Host smart-8391afbd-35f9-4350-a6be-c0f4b0bcdb6a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655451891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2655451891
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2677996422
Short name T914
Test name
Test status
Simulation time 185938602 ps
CPU time 1 seconds
Started Jul 16 05:28:55 PM PDT 24
Finished Jul 16 05:29:03 PM PDT 24
Peak memory 198416 kb
Host smart-d70261b4-3975-4445-adbc-5c97a363152f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2677996422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2677996422
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2828644813
Short name T905
Test name
Test status
Simulation time 53017733 ps
CPU time 1.03 seconds
Started Jul 16 05:31:18 PM PDT 24
Finished Jul 16 05:31:21 PM PDT 24
Peak memory 197000 kb
Host smart-595efd3f-eeca-44f7-874b-18716e48386f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828644813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2828644813
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2798468478
Short name T890
Test name
Test status
Simulation time 35881983 ps
CPU time 1.18 seconds
Started Jul 16 05:28:58 PM PDT 24
Finished Jul 16 05:29:04 PM PDT 24
Peak memory 196964 kb
Host smart-6e23cdf1-91d8-431d-a2fb-f0d45437eecc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2798468478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2798468478
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.163407630
Short name T864
Test name
Test status
Simulation time 668474198 ps
CPU time 1.06 seconds
Started Jul 16 05:29:07 PM PDT 24
Finished Jul 16 05:29:09 PM PDT 24
Peak memory 198460 kb
Host smart-2d4f0e0c-ea44-4e87-afd4-ebf43c37b724
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163407630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.163407630
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.833768588
Short name T886
Test name
Test status
Simulation time 316438356 ps
CPU time 0.97 seconds
Started Jul 16 05:31:20 PM PDT 24
Finished Jul 16 05:31:22 PM PDT 24
Peak memory 196928 kb
Host smart-d06ece16-68a3-43d8-9cb3-80a8434cb41e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=833768588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.833768588
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3615948884
Short name T876
Test name
Test status
Simulation time 507933541 ps
CPU time 1.32 seconds
Started Jul 16 05:28:54 PM PDT 24
Finished Jul 16 05:29:02 PM PDT 24
Peak memory 197124 kb
Host smart-0316bea8-dd76-4bc5-ab59-d51e51673c49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615948884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3615948884
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.686977207
Short name T858
Test name
Test status
Simulation time 99174874 ps
CPU time 1.08 seconds
Started Jul 16 05:29:11 PM PDT 24
Finished Jul 16 05:29:13 PM PDT 24
Peak memory 198000 kb
Host smart-a9594542-49d8-47c9-be73-efd53f1b6be7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=686977207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.686977207
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.123786655
Short name T922
Test name
Test status
Simulation time 472112816 ps
CPU time 1.21 seconds
Started Jul 16 05:29:13 PM PDT 24
Finished Jul 16 05:29:14 PM PDT 24
Peak memory 197460 kb
Host smart-6076bace-f2df-4066-8853-93562afade13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123786655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.123786655
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2958243901
Short name T871
Test name
Test status
Simulation time 288265173 ps
CPU time 1.4 seconds
Started Jul 16 05:36:08 PM PDT 24
Finished Jul 16 05:36:10 PM PDT 24
Peak memory 197016 kb
Host smart-246c21dc-f5b4-413f-be34-709962f5d480
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2958243901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2958243901
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3766633420
Short name T906
Test name
Test status
Simulation time 32828779 ps
CPU time 0.83 seconds
Started Jul 16 05:29:11 PM PDT 24
Finished Jul 16 05:29:13 PM PDT 24
Peak memory 196692 kb
Host smart-bb8f15cd-51b7-4e21-882a-bb68c7b4594e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766633420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3766633420
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3576097021
Short name T856
Test name
Test status
Simulation time 51193096 ps
CPU time 1.23 seconds
Started Jul 16 05:29:09 PM PDT 24
Finished Jul 16 05:29:11 PM PDT 24
Peak memory 197136 kb
Host smart-1ed9ee2b-5ac6-4bdd-8262-0e32f52018cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3576097021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3576097021
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1095107153
Short name T848
Test name
Test status
Simulation time 151059868 ps
CPU time 1.13 seconds
Started Jul 16 05:29:09 PM PDT 24
Finished Jul 16 05:29:11 PM PDT 24
Peak memory 196116 kb
Host smart-f4611a70-5afa-4e19-8aa7-97380a4ccb32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095107153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1095107153
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.456159466
Short name T896
Test name
Test status
Simulation time 101731490 ps
CPU time 1.36 seconds
Started Jul 16 05:29:09 PM PDT 24
Finished Jul 16 05:29:11 PM PDT 24
Peak memory 196988 kb
Host smart-6b99345b-ee85-42eb-8f3f-ffa81a0c6d00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=456159466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.456159466
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2444047179
Short name T859
Test name
Test status
Simulation time 242305643 ps
CPU time 1.14 seconds
Started Jul 16 05:29:07 PM PDT 24
Finished Jul 16 05:29:08 PM PDT 24
Peak memory 196336 kb
Host smart-7cffb50c-4b06-4c13-878d-6e5afb3f0dde
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444047179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2444047179
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2005077459
Short name T898
Test name
Test status
Simulation time 520963971 ps
CPU time 1.28 seconds
Started Jul 16 05:29:23 PM PDT 24
Finished Jul 16 05:29:25 PM PDT 24
Peak memory 196044 kb
Host smart-9684e498-a817-4fe0-b0d2-2e8c469e37ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2005077459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2005077459
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2324585093
Short name T846
Test name
Test status
Simulation time 40049470 ps
CPU time 1.1 seconds
Started Jul 16 05:29:09 PM PDT 24
Finished Jul 16 05:29:10 PM PDT 24
Peak memory 196992 kb
Host smart-d0090184-2f72-44bc-9c73-7c296a46c2fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324585093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2324585093
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2058748218
Short name T854
Test name
Test status
Simulation time 170630364 ps
CPU time 1.16 seconds
Started Jul 16 05:29:05 PM PDT 24
Finished Jul 16 05:29:06 PM PDT 24
Peak memory 196984 kb
Host smart-f3e4b8b4-49b1-4d2b-a3eb-3f9c1b639ec5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2058748218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2058748218
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1154221422
Short name T866
Test name
Test status
Simulation time 189896698 ps
CPU time 1.11 seconds
Started Jul 16 05:29:12 PM PDT 24
Finished Jul 16 05:29:14 PM PDT 24
Peak memory 197164 kb
Host smart-fea06f34-7f98-43ff-94a6-c9be7bdc644e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154221422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1154221422
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1011820718
Short name T839
Test name
Test status
Simulation time 46495672 ps
CPU time 1.21 seconds
Started Jul 16 05:29:07 PM PDT 24
Finished Jul 16 05:29:09 PM PDT 24
Peak memory 196152 kb
Host smart-a8e3016f-1f3a-49d9-a8c5-0b8c67fca16e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1011820718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1011820718
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4102578479
Short name T933
Test name
Test status
Simulation time 73691563 ps
CPU time 1.08 seconds
Started Jul 16 05:29:07 PM PDT 24
Finished Jul 16 05:29:09 PM PDT 24
Peak memory 196964 kb
Host smart-943a7dee-45b0-4dda-a94f-fae1b5272325
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102578479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4102578479
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3215889257
Short name T842
Test name
Test status
Simulation time 29018025 ps
CPU time 0.89 seconds
Started Jul 16 05:29:12 PM PDT 24
Finished Jul 16 05:29:13 PM PDT 24
Peak memory 195872 kb
Host smart-d1ed5091-203f-4566-8a62-01c77a9f26b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3215889257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3215889257
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2469382405
Short name T872
Test name
Test status
Simulation time 106162191 ps
CPU time 1.31 seconds
Started Jul 16 05:29:05 PM PDT 24
Finished Jul 16 05:29:07 PM PDT 24
Peak memory 197216 kb
Host smart-94a7a388-42fb-4cd8-b1d6-a57ae529b1c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469382405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2469382405
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2997437297
Short name T936
Test name
Test status
Simulation time 95874430 ps
CPU time 1.02 seconds
Started Jul 16 05:29:08 PM PDT 24
Finished Jul 16 05:29:10 PM PDT 24
Peak memory 196932 kb
Host smart-0d43e492-8440-4f3d-826e-989e0a441bab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2997437297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2997437297
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.913241608
Short name T860
Test name
Test status
Simulation time 124671927 ps
CPU time 1.02 seconds
Started Jul 16 05:29:08 PM PDT 24
Finished Jul 16 05:29:09 PM PDT 24
Peak memory 197024 kb
Host smart-099c2d4b-c35c-4bd5-ba7a-633c21b01087
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913241608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.913241608
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1507168715
Short name T893
Test name
Test status
Simulation time 47917635 ps
CPU time 1.29 seconds
Started Jul 16 05:34:11 PM PDT 24
Finished Jul 16 05:34:13 PM PDT 24
Peak memory 197136 kb
Host smart-5f66e228-3259-42fa-98fb-d18c31074787
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1507168715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1507168715
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2216498684
Short name T889
Test name
Test status
Simulation time 193062922 ps
CPU time 1.3 seconds
Started Jul 16 05:29:07 PM PDT 24
Finished Jul 16 05:29:08 PM PDT 24
Peak memory 198444 kb
Host smart-c17b03f9-c1d6-420e-807e-fa7c25a03b02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216498684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2216498684
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.854671864
Short name T863
Test name
Test status
Simulation time 254309986 ps
CPU time 0.98 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 197112 kb
Host smart-c348fccc-377b-449e-a1e8-f08541346bc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=854671864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.854671864
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.221947003
Short name T881
Test name
Test status
Simulation time 113112515 ps
CPU time 1.11 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 197100 kb
Host smart-a29876b4-4993-4549-a9e1-4eacf0ee188e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221947003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.221947003
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.618460940
Short name T852
Test name
Test status
Simulation time 294630785 ps
CPU time 1.29 seconds
Started Jul 16 05:34:11 PM PDT 24
Finished Jul 16 05:34:13 PM PDT 24
Peak memory 196084 kb
Host smart-2b6c57cf-b31a-497e-8f67-ae4cb3595d6f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=618460940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.618460940
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2850760324
Short name T918
Test name
Test status
Simulation time 45517574 ps
CPU time 1.28 seconds
Started Jul 16 05:34:03 PM PDT 24
Finished Jul 16 05:34:05 PM PDT 24
Peak memory 198396 kb
Host smart-0c8fe94a-8ca1-4ccf-903e-153701208d35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850760324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2850760324
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2659216197
Short name T931
Test name
Test status
Simulation time 144556666 ps
CPU time 0.92 seconds
Started Jul 16 05:34:13 PM PDT 24
Finished Jul 16 05:34:15 PM PDT 24
Peak memory 196888 kb
Host smart-e6dc889b-b675-4fb2-b347-8465c1eee5bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2659216197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2659216197
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3584521112
Short name T843
Test name
Test status
Simulation time 50947417 ps
CPU time 1.3 seconds
Started Jul 16 05:29:11 PM PDT 24
Finished Jul 16 05:29:12 PM PDT 24
Peak memory 198508 kb
Host smart-b32216c7-6d52-4b19-8d8d-eca445799012
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584521112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3584521112
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3197295350
Short name T840
Test name
Test status
Simulation time 72846475 ps
CPU time 1.08 seconds
Started Jul 16 05:29:12 PM PDT 24
Finished Jul 16 05:29:14 PM PDT 24
Peak memory 196268 kb
Host smart-e7ea47ea-1b73-4024-affc-4c33a7c68ebc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3197295350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3197295350
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3953013436
Short name T851
Test name
Test status
Simulation time 32120216 ps
CPU time 0.76 seconds
Started Jul 16 05:29:12 PM PDT 24
Finished Jul 16 05:29:13 PM PDT 24
Peak memory 194772 kb
Host smart-1c372fe7-ed80-4174-886f-8a18cb118510
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953013436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3953013436
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1691354664
Short name T902
Test name
Test status
Simulation time 949348853 ps
CPU time 1.22 seconds
Started Jul 16 05:29:12 PM PDT 24
Finished Jul 16 05:29:14 PM PDT 24
Peak memory 197020 kb
Host smart-9b6d23c6-dc32-4ebc-86c5-e9ddf5660e28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1691354664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1691354664
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3217671209
Short name T857
Test name
Test status
Simulation time 30375854 ps
CPU time 0.87 seconds
Started Jul 16 05:36:52 PM PDT 24
Finished Jul 16 05:36:54 PM PDT 24
Peak memory 195892 kb
Host smart-05c16d69-0c83-4c1e-a135-8488d8058111
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217671209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3217671209
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.128994583
Short name T862
Test name
Test status
Simulation time 35351764 ps
CPU time 0.91 seconds
Started Jul 16 05:32:35 PM PDT 24
Finished Jul 16 05:32:37 PM PDT 24
Peak memory 196944 kb
Host smart-52ae8e5d-38dd-4375-ab79-47738205581a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=128994583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.128994583
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2254198985
Short name T847
Test name
Test status
Simulation time 92574015 ps
CPU time 1.3 seconds
Started Jul 16 05:29:25 PM PDT 24
Finished Jul 16 05:29:27 PM PDT 24
Peak memory 197240 kb
Host smart-fd6d6622-363b-4e6c-a0fb-9e9902e06813
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254198985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2254198985
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.239720154
Short name T841
Test name
Test status
Simulation time 60349874 ps
CPU time 1.22 seconds
Started Jul 16 05:29:21 PM PDT 24
Finished Jul 16 05:29:23 PM PDT 24
Peak memory 197332 kb
Host smart-3b8b0708-d5be-49ac-bb06-d17499f145ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=239720154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.239720154
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3748111639
Short name T908
Test name
Test status
Simulation time 209111954 ps
CPU time 0.91 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:24 PM PDT 24
Peak memory 195824 kb
Host smart-3f2825ce-ba3c-496c-b65e-d026b4111ea9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748111639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3748111639
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3391766636
Short name T923
Test name
Test status
Simulation time 97292544 ps
CPU time 0.94 seconds
Started Jul 16 05:32:13 PM PDT 24
Finished Jul 16 05:32:14 PM PDT 24
Peak memory 197768 kb
Host smart-8054be21-f440-4353-8dfe-989efdc514f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3391766636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3391766636
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3029822186
Short name T880
Test name
Test status
Simulation time 194963892 ps
CPU time 1.35 seconds
Started Jul 16 05:32:41 PM PDT 24
Finished Jul 16 05:32:43 PM PDT 24
Peak memory 198432 kb
Host smart-749649e8-0ef9-4d91-b458-bf1e09bd0219
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029822186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3029822186
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4258809775
Short name T849
Test name
Test status
Simulation time 220209428 ps
CPU time 1.18 seconds
Started Jul 16 05:36:09 PM PDT 24
Finished Jul 16 05:36:10 PM PDT 24
Peak memory 196900 kb
Host smart-51751d88-25a9-450a-9049-690bb38daea0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4258809775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4258809775
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918278497
Short name T920
Test name
Test status
Simulation time 84662337 ps
CPU time 1.43 seconds
Started Jul 16 05:29:24 PM PDT 24
Finished Jul 16 05:29:26 PM PDT 24
Peak memory 197080 kb
Host smart-d67efa51-6a6e-445e-9052-becbc4cf4281
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918278497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3918278497
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.592394297
Short name T865
Test name
Test status
Simulation time 155642597 ps
CPU time 1.28 seconds
Started Jul 16 05:29:19 PM PDT 24
Finished Jul 16 05:29:20 PM PDT 24
Peak memory 198428 kb
Host smart-819aaaff-d1b6-46a5-8644-8889d79fee74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=592394297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.592394297
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604096411
Short name T855
Test name
Test status
Simulation time 93046914 ps
CPU time 1 seconds
Started Jul 16 05:29:22 PM PDT 24
Finished Jul 16 05:29:24 PM PDT 24
Peak memory 197272 kb
Host smart-c8957071-43da-4ee7-9534-9574bc3edf27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604096411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3604096411
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3882130212
Short name T874
Test name
Test status
Simulation time 32398087 ps
CPU time 0.89 seconds
Started Jul 16 05:29:18 PM PDT 24
Finished Jul 16 05:29:19 PM PDT 24
Peak memory 195748 kb
Host smart-7ef6f603-cb5d-4661-9080-ea28960aadd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3882130212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3882130212
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1061817501
Short name T879
Test name
Test status
Simulation time 224036296 ps
CPU time 1.32 seconds
Started Jul 16 05:29:20 PM PDT 24
Finished Jul 16 05:29:22 PM PDT 24
Peak memory 197056 kb
Host smart-77efbaa5-00af-4ab3-a43f-25ece7b26b06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061817501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1061817501
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.28344554
Short name T904
Test name
Test status
Simulation time 41880393 ps
CPU time 1.21 seconds
Started Jul 16 05:28:43 PM PDT 24
Finished Jul 16 05:28:45 PM PDT 24
Peak memory 196380 kb
Host smart-3e34b801-0653-4845-819f-8534256cb83e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=28344554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.28344554
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574210605
Short name T899
Test name
Test status
Simulation time 43920385 ps
CPU time 0.96 seconds
Started Jul 16 05:32:30 PM PDT 24
Finished Jul 16 05:32:32 PM PDT 24
Peak memory 197112 kb
Host smart-cf713ab0-e605-4fe4-8e50-dccf60aef20f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574210605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.574210605
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3984516271
Short name T938
Test name
Test status
Simulation time 184597284 ps
CPU time 0.96 seconds
Started Jul 16 05:28:53 PM PDT 24
Finished Jul 16 05:28:55 PM PDT 24
Peak memory 196212 kb
Host smart-0b146fde-7896-4aff-92ba-ee15ef22f605
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3984516271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3984516271
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2051241656
Short name T926
Test name
Test status
Simulation time 47813948 ps
CPU time 1.02 seconds
Started Jul 16 05:28:46 PM PDT 24
Finished Jul 16 05:28:48 PM PDT 24
Peak memory 196780 kb
Host smart-d1181ca0-90b4-4113-a11a-db5c836974f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051241656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2051241656
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.707626516
Short name T845
Test name
Test status
Simulation time 101954950 ps
CPU time 0.79 seconds
Started Jul 16 05:32:31 PM PDT 24
Finished Jul 16 05:32:33 PM PDT 24
Peak memory 196476 kb
Host smart-4262148c-0821-4830-aaab-dd92632b4959
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=707626516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.707626516
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.633902180
Short name T878
Test name
Test status
Simulation time 121588881 ps
CPU time 0.92 seconds
Started Jul 16 05:28:49 PM PDT 24
Finished Jul 16 05:28:52 PM PDT 24
Peak memory 196016 kb
Host smart-9dd8373e-9143-4662-a3d2-881920973393
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633902180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.633902180
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1327686009
Short name T919
Test name
Test status
Simulation time 139010037 ps
CPU time 1.25 seconds
Started Jul 16 05:32:24 PM PDT 24
Finished Jul 16 05:32:27 PM PDT 24
Peak memory 198316 kb
Host smart-2a9002a9-d5ff-4999-8675-4f9729543503
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1327686009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1327686009
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603709471
Short name T911
Test name
Test status
Simulation time 61398642 ps
CPU time 1.08 seconds
Started Jul 16 05:28:49 PM PDT 24
Finished Jul 16 05:28:52 PM PDT 24
Peak memory 197040 kb
Host smart-14bc9327-9516-47ec-8d4e-d4bf96047221
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603709471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1603709471
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4092901598
Short name T916
Test name
Test status
Simulation time 85140547 ps
CPU time 1.21 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:49 PM PDT 24
Peak memory 197296 kb
Host smart-9f33d7ed-c411-4ce5-ad7a-4903fcc9a112
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4092901598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.4092901598
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.117721361
Short name T909
Test name
Test status
Simulation time 47615745 ps
CPU time 1.32 seconds
Started Jul 16 05:28:47 PM PDT 24
Finished Jul 16 05:28:50 PM PDT 24
Peak memory 197088 kb
Host smart-dc801259-228a-4e55-9947-a3e3354871a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117721361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.117721361
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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