Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13672092	1			T29	174		T30	57		T31	300
all_values[1]	13672092	1			T29	174		T30	57		T31	300
all_values[2]	13672092	1			T29	174		T30	57		T31	300
all_values[3]	13672092	1			T29	174		T30	57		T31	300
all_values[4]	13672092	1			T29	174		T30	57		T31	300
all_values[5]	13672092	1			T29	174		T30	57		T31	300
all_values[6]	13672092	1			T29	174		T30	57		T31	300
all_values[7]	13672092	1			T29	174		T30	57		T31	300
all_values[8]	13672092	1			T29	174		T30	57		T31	300
all_values[9]	13672092	1			T29	174		T30	57		T31	300
all_values[10]	13672092	1			T29	174		T30	57		T31	300
all_values[11]	13672092	1			T29	174		T30	57		T31	300
all_values[12]	13672092	1			T29	174		T30	57		T31	300
all_values[13]	13672092	1			T29	174		T30	57		T31	300
all_values[14]	13672092	1			T29	174		T30	57		T31	300
all_values[15]	13672092	1			T29	174		T30	57		T31	300
all_values[16]	13672092	1			T29	174		T30	57		T31	300
all_values[17]	13672092	1			T29	174		T30	57		T31	300
all_values[18]	13672092	1			T29	174		T30	57		T31	300
all_values[19]	13672092	1			T29	174		T30	57		T31	300
all_values[20]	13672092	1			T29	174		T30	57		T31	300
all_values[21]	13672092	1			T29	174		T30	57		T31	300
all_values[22]	13672092	1			T29	174		T30	57		T31	300
all_values[23]	13672092	1			T29	174		T30	57		T31	300
all_values[24]	13672092	1			T29	174		T30	57		T31	300
all_values[25]	13672092	1			T29	174		T30	57		T31	300
all_values[26]	13672092	1			T29	174		T30	57		T31	300
all_values[27]	13672092	1			T29	174		T30	57		T31	300
all_values[28]	13672092	1			T29	174		T30	57		T31	300
all_values[29]	13672092	1			T29	174		T30	57		T31	300
all_values[30]	13672092	1			T29	174		T30	57		T31	300
all_values[31]	13672092	1			T29	174		T30	57		T31	300

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252045315

1

T29

5568

T30

1047

T31

9600

auto[1]

185461629

1

T30

777

T32

1269

T19

589

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101791817

1

T29

5568

T30

493

T31

9600

auto[1]

335715127

1

T30

1331

T32

931

T19

1312

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2614625	1			T29	174		T30	18		T31	300
all_values[0]	auto[0]	auto[1]	5256095	1			T30	15		T32	13		T19	15
all_values[0]	auto[1]	auto[0]	559225	1			T30	4		T32	19		T19	15
all_values[0]	auto[1]	auto[1]	5242147	1			T30	20		T32	27		T19	17
all_values[1]	auto[0]	auto[0]	2620905	1			T29	174		T30	13		T31	300
all_values[1]	auto[0]	auto[1]	5254906	1			T30	15		T32	10		T19	32
all_values[1]	auto[1]	auto[0]	572893	1			T30	17		T32	39		T19	9
all_values[1]	auto[1]	auto[1]	5223388	1			T30	12		T19	12		T21	134
all_values[2]	auto[0]	auto[0]	2620578	1			T29	174		T30	1		T31	300
all_values[2]	auto[0]	auto[1]	5265262	1			T30	15		T32	22		T19	35
all_values[2]	auto[1]	auto[0]	555997	1			T30	7		T32	20		T19	12
all_values[2]	auto[1]	auto[1]	5230255	1			T30	34		T32	15		T19	10
all_values[3]	auto[0]	auto[0]	2616701	1			T29	174		T30	3		T31	300
all_values[3]	auto[0]	auto[1]	5236236	1			T30	23		T32	20		T19	31
all_values[3]	auto[1]	auto[0]	572993	1			T30	4		T32	24		T19	8
all_values[3]	auto[1]	auto[1]	5246162	1			T30	27		T32	7		T19	4
all_values[4]	auto[0]	auto[0]	2614528	1			T29	174		T30	7		T31	300
all_values[4]	auto[0]	auto[1]	5274646	1			T30	33		T32	5		T19	30
all_values[4]	auto[1]	auto[0]	557030	1			T30	6		T32	31		T19	7
all_values[4]	auto[1]	auto[1]	5225888	1			T30	11		T32	12		T19	11
all_values[5]	auto[0]	auto[0]	2619808	1			T29	174		T30	13		T31	300
all_values[5]	auto[0]	auto[1]	5226468	1			T30	8		T32	28		T19	35
all_values[5]	auto[1]	auto[0]	561105	1			T30	18		T32	27		T19	5
all_values[5]	auto[1]	auto[1]	5264711	1			T30	18		T32	13		T19	12
all_values[6]	auto[0]	auto[0]	2617963	1			T29	174		T30	11		T31	300
all_values[6]	auto[0]	auto[1]	5251560	1			T30	15		T32	16		T19	25
all_values[6]	auto[1]	auto[0]	554138	1			T30	8		T32	26		T19	18
all_values[6]	auto[1]	auto[1]	5248431	1			T30	23		T32	22		T19	13
all_values[7]	auto[0]	auto[0]	2627977	1			T29	174		T30	2		T31	300
all_values[7]	auto[0]	auto[1]	5232119	1			T30	3		T32	9		T19	30
all_values[7]	auto[1]	auto[0]	558924	1			T30	12		T32	45		T19	6
all_values[7]	auto[1]	auto[1]	5253072	1			T30	40		T32	16		T19	8
all_values[8]	auto[0]	auto[0]	2614028	1			T29	174		T30	5		T31	300
all_values[8]	auto[0]	auto[1]	5229267	1			T30	46		T32	6		T19	27
all_values[8]	auto[1]	auto[0]	554083	1			T30	6		T32	19		T19	19
all_values[8]	auto[1]	auto[1]	5274714	1			T32	20		T19	12		T21	98
all_values[9]	auto[0]	auto[0]	2626286	1			T29	174		T30	11		T31	300
all_values[9]	auto[0]	auto[1]	5252999	1			T30	30		T32	8		T19	36
all_values[9]	auto[1]	auto[0]	551396	1			T30	7		T32	40		T19	9
all_values[9]	auto[1]	auto[1]	5241411	1			T30	9		T32	18		T19	3
all_values[10]	auto[0]	auto[0]	2617336	1			T29	174		T30	32		T31	300
all_values[10]	auto[0]	auto[1]	5228625	1			T30	14		T32	27		T19	34
all_values[10]	auto[1]	auto[0]	564644	1			T32	27		T19	12		T21	17
all_values[10]	auto[1]	auto[1]	5261487	1			T30	11		T32	5		T19	8
all_values[11]	auto[0]	auto[0]	2621647	1			T29	174		T30	11		T31	300
all_values[11]	auto[0]	auto[1]	5253125	1			T30	25		T32	8		T19	36
all_values[11]	auto[1]	auto[0]	558415	1			T30	10		T32	22		T19	5
all_values[11]	auto[1]	auto[1]	5238905	1			T30	11		T32	13		T19	14
all_values[12]	auto[0]	auto[0]	2618021	1			T29	174		T30	6		T31	300
all_values[12]	auto[0]	auto[1]	5246642	1			T30	21		T32	14		T19	27
all_values[12]	auto[1]	auto[0]	567180	1			T30	9		T32	31		T19	7
all_values[12]	auto[1]	auto[1]	5240249	1			T30	21		T32	18		T19	7
all_values[13]	auto[0]	auto[0]	2617703	1			T29	174		T30	7		T31	300
all_values[13]	auto[0]	auto[1]	5225297	1			T30	44		T32	21		T19	34
all_values[13]	auto[1]	auto[0]	564071	1			T32	19		T19	14		T21	14
all_values[13]	auto[1]	auto[1]	5265021	1			T30	6		T32	9		T19	6
all_values[14]	auto[0]	auto[0]	2625447	1			T29	174		T30	4		T31	300
all_values[14]	auto[0]	auto[1]	5299698	1			T30	30		T32	24		T19	33
all_values[14]	auto[1]	auto[0]	562615	1			T32	29		T19	10		T21	16
all_values[14]	auto[1]	auto[1]	5184332	1			T30	23		T32	5		T19	12
all_values[15]	auto[0]	auto[0]	2613102	1			T29	174		T30	7		T31	300
all_values[15]	auto[0]	auto[1]	5226810	1			T30	16		T32	15		T19	37
all_values[15]	auto[1]	auto[0]	563012	1			T30	19		T32	26		T19	2
all_values[15]	auto[1]	auto[1]	5269168	1			T30	15		T32	13		T19	1
all_values[16]	auto[0]	auto[0]	2617112	1			T29	174		T30	1		T31	300
all_values[16]	auto[0]	auto[1]	5274892	1			T30	16		T32	9		T19	38
all_values[16]	auto[1]	auto[0]	553193	1			T30	9		T32	33		T19	10
all_values[16]	auto[1]	auto[1]	5226895	1			T30	31		T32	24		T19	9
all_values[17]	auto[0]	auto[0]	2616015	1			T29	174		T30	10		T31	300
all_values[17]	auto[0]	auto[1]	5272235	1			T30	16		T32	16		T19	32
all_values[17]	auto[1]	auto[0]	571470	1			T30	4		T32	14		T19	12
all_values[17]	auto[1]	auto[1]	5212372	1			T30	27		T32	13		T19	6
all_values[18]	auto[0]	auto[0]	2627185	1			T29	174		T30	10		T31	300
all_values[18]	auto[0]	auto[1]	5253796	1			T30	24		T32	13		T19	28
all_values[18]	auto[1]	auto[0]	562505	1			T30	10		T32	44		T19	14
all_values[18]	auto[1]	auto[1]	5228606	1			T30	13		T32	12		T19	12
all_values[19]	auto[0]	auto[0]	2629811	1			T29	174		T30	1		T31	300
all_values[19]	auto[0]	auto[1]	5264277	1			T30	25		T32	14		T19	38
all_values[19]	auto[1]	auto[0]	563856	1			T30	6		T32	21		T19	13
all_values[19]	auto[1]	auto[1]	5214148	1			T30	25		T32	20		T19	8
all_values[20]	auto[0]	auto[0]	2620609	1			T29	174		T30	17		T31	300
all_values[20]	auto[0]	auto[1]	5271362	1			T30	25		T32	10		T19	26
all_values[20]	auto[1]	auto[0]	555158	1			T30	4		T32	37		T19	14
all_values[20]	auto[1]	auto[1]	5224963	1			T30	11		T32	16		T19	17
all_values[21]	auto[0]	auto[0]	2622766	1			T29	174		T30	3		T31	300
all_values[21]	auto[0]	auto[1]	5242421	1			T30	24		T32	13		T19	21
all_values[21]	auto[1]	auto[0]	565211	1			T30	13		T32	32		T19	5
all_values[21]	auto[1]	auto[1]	5241694	1			T30	17		T32	13		T19	4
all_values[22]	auto[0]	auto[0]	2619024	1			T29	174		T30	13		T31	300
all_values[22]	auto[0]	auto[1]	5273708	1			T30	25		T32	17		T19	36
all_values[22]	auto[1]	auto[0]	557290	1			T30	1		T32	14		T19	12
all_values[22]	auto[1]	auto[1]	5222070	1			T30	18		T32	10		T19	13
all_values[23]	auto[0]	auto[0]	2622732	1			T29	174		T30	15		T31	300
all_values[23]	auto[0]	auto[1]	5259662	1			T30	16		T32	16		T19	35
all_values[23]	auto[1]	auto[0]	566064	1			T30	7		T32	21		T19	7
all_values[23]	auto[1]	auto[1]	5223634	1			T30	19		T32	14		T19	10
all_values[24]	auto[0]	auto[0]	2627046	1			T29	174		T30	13		T31	300
all_values[24]	auto[0]	auto[1]	5254438	1			T30	23		T32	23		T19	22
all_values[24]	auto[1]	auto[0]	563484	1			T30	6		T32	25		T19	9
all_values[24]	auto[1]	auto[1]	5227124	1			T30	15		T32	11		T19	6
all_values[25]	auto[0]	auto[0]	2617540	1			T29	174		T30	1		T31	300
all_values[25]	auto[0]	auto[1]	5264257	1			T30	20		T32	20		T19	35
all_values[25]	auto[1]	auto[0]	556459	1			T30	4		T32	22		T19	5
all_values[25]	auto[1]	auto[1]	5233836	1			T30	32		T32	8		T19	12
all_values[26]	auto[0]	auto[0]	2617234	1			T29	174		T30	12		T31	300
all_values[26]	auto[0]	auto[1]	5253161	1			T30	14		T32	27		T19	37
all_values[26]	auto[1]	auto[0]	562724	1			T30	9		T32	20		T19	11
all_values[26]	auto[1]	auto[1]	5238973	1			T30	22		T32	7		T19	6
all_values[27]	auto[0]	auto[0]	2621188	1			T29	174		T30	12		T31	300
all_values[27]	auto[0]	auto[1]	5285185	1			T30	40		T32	21		T19	43
all_values[27]	auto[1]	auto[0]	556001	1			T32	18		T19	4		T21	28
all_values[27]	auto[1]	auto[1]	5209718	1			T30	5		T32	4		T19	7
all_values[28]	auto[0]	auto[0]	2615887	1			T29	174		T30	1		T31	300
all_values[28]	auto[0]	auto[1]	5273832	1			T30	44		T32	26		T19	36
all_values[28]	auto[1]	auto[0]	557536	1			T30	4		T32	9		T19	2
all_values[28]	auto[1]	auto[1]	5224837	1			T30	8		T32	14		T19	8
all_values[29]	auto[0]	auto[0]	2627705	1			T29	174		T30	7		T31	300
all_values[29]	auto[0]	auto[1]	5243596	1			T30	27		T32	20		T19	24
all_values[29]	auto[1]	auto[0]	564234	1			T30	3		T32	30		T19	13
all_values[29]	auto[1]	auto[1]	5236557	1			T30	20		T32	12		T19	7
all_values[30]	auto[0]	auto[0]	2618342	1			T29	174		T30	8		T31	300
all_values[30]	auto[0]	auto[1]	5302789	1			T30	49		T32	11		T19	42
all_values[30]	auto[1]	auto[0]	556997	1			T32	34		T19	10		T21	13
all_values[30]	auto[1]	auto[1]	5193964	1			T32	14		T21	136		T116	1147
all_values[31]	auto[0]	auto[0]	2613374	1			T29	174		T30	8		T31	300
all_values[31]	auto[0]	auto[1]	5255724	1			T30	23		T32	11		T19	42
all_values[31]	auto[1]	auto[0]	561689	1			T30	3		T32	33		T19	10
all_values[31]	auto[1]	auto[1]	5241305	1			T30	23		T32	13		T19	5