Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4082643	1			T29	1		T30	40		T31	1
all_pins[1]	4082643	1			T29	1		T30	40		T31	1
all_pins[2]	4082643	1			T29	1		T30	40		T31	1
all_pins[3]	4082643	1			T29	1		T30	40		T31	1
all_pins[4]	4082643	1			T29	1		T30	40		T31	1
all_pins[5]	4082643	1			T29	1		T30	40		T31	1
all_pins[6]	4082643	1			T29	1		T30	40		T31	1
all_pins[7]	4082643	1			T29	1		T30	40		T31	1
all_pins[8]	4082643	1			T29	1		T30	40		T31	1
all_pins[9]	4082643	1			T29	1		T30	40		T31	1
all_pins[10]	4082643	1			T29	1		T30	40		T31	1
all_pins[11]	4082643	1			T29	1		T30	40		T31	1
all_pins[12]	4082643	1			T29	1		T30	40		T31	1
all_pins[13]	4082643	1			T29	1		T30	40		T31	1
all_pins[14]	4082643	1			T29	1		T30	40		T31	1
all_pins[15]	4082643	1			T29	1		T30	40		T31	1
all_pins[16]	4082643	1			T29	1		T30	40		T31	1
all_pins[17]	4082643	1			T29	1		T30	40		T31	1
all_pins[18]	4082643	1			T29	1		T30	40		T31	1
all_pins[19]	4082643	1			T29	1		T30	40		T31	1
all_pins[20]	4082643	1			T29	1		T30	40		T31	1
all_pins[21]	4082643	1			T29	1		T30	40		T31	1
all_pins[22]	4082643	1			T29	1		T30	40		T31	1
all_pins[23]	4082643	1			T29	1		T30	40		T31	1
all_pins[24]	4082643	1			T29	1		T30	40		T31	1
all_pins[25]	4082643	1			T29	1		T30	40		T31	1
all_pins[26]	4082643	1			T29	1		T30	40		T31	1
all_pins[27]	4082643	1			T29	1		T30	40		T31	1
all_pins[28]	4082643	1			T29	1		T30	40		T31	1
all_pins[29]	4082643	1			T29	1		T30	40		T31	1
all_pins[30]	4082643	1			T29	1		T30	40		T31	1
all_pins[31]	4082643	1			T29	1		T30	40		T31	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	81171257	1			T29	32		T30	910		T31	32
values[0x1]	49473319	1			T30	370		T32	387		T33	367
transitions[0x0=>0x1]	29654163	1			T30	256		T32	285		T33	203
transitions[0x1=>0x0]	29654016	1			T30	255		T32	285		T33	202

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2539341	1			T29	1		T30	28		T31	1
all_pins[0]	values[0x1]	1543302	1			T30	12		T32	27		T33	11
all_pins[0]	transitions[0x0=>0x1]	954648	1			T30	12		T32	19		T33	7
all_pins[0]	transitions[0x1=>0x0]	957448	1			T30	12		T32	3		T33	4
all_pins[1]	values[0x0]	2542750	1			T29	1		T30	32		T31	1
all_pins[1]	values[0x1]	1539893	1			T30	8		T33	12		T19	11
all_pins[1]	transitions[0x0=>0x1]	921724	1			T30	5		T33	5		T19	2
all_pins[1]	transitions[0x1=>0x0]	925133	1			T30	9		T32	27		T33	4
all_pins[2]	values[0x0]	2531850	1			T29	1		T30	16		T31	1
all_pins[2]	values[0x1]	1550793	1			T30	24		T32	15		T33	7
all_pins[2]	transitions[0x0=>0x1]	929845	1			T30	18		T32	15		T33	3
all_pins[2]	transitions[0x1=>0x0]	918945	1			T30	2		T33	8		T19	8
all_pins[3]	values[0x0]	2536210	1			T29	1		T30	22		T31	1
all_pins[3]	values[0x1]	1546433	1			T30	18		T32	7		T33	5
all_pins[3]	transitions[0x0=>0x1]	924552	1			T30	6		T32	7		T33	5
all_pins[3]	transitions[0x1=>0x0]	928912	1			T30	12		T32	15		T33	7
all_pins[4]	values[0x0]	2529624	1			T29	1		T30	32		T31	1
all_pins[4]	values[0x1]	1553019	1			T30	8		T32	12		T33	10
all_pins[4]	transitions[0x0=>0x1]	928538	1			T30	3		T32	9		T33	7
all_pins[4]	transitions[0x1=>0x0]	921952	1			T30	13		T32	4		T33	2
all_pins[5]	values[0x0]	2535453	1			T29	1		T30	27		T31	1
all_pins[5]	values[0x1]	1547190	1			T30	13		T32	14		T33	10
all_pins[5]	transitions[0x0=>0x1]	923809	1			T30	8		T32	12		T33	8
all_pins[5]	transitions[0x1=>0x0]	929638	1			T30	3		T32	10		T33	8
all_pins[6]	values[0x0]	2535327	1			T29	1		T30	23		T31	1
all_pins[6]	values[0x1]	1547316	1			T30	17		T32	18		T33	11
all_pins[6]	transitions[0x0=>0x1]	924467	1			T30	10		T32	18		T33	8
all_pins[6]	transitions[0x1=>0x0]	924341	1			T30	6		T32	14		T33	7
all_pins[7]	values[0x0]	2540657	1			T29	1		T30	15		T31	1
all_pins[7]	values[0x1]	1541986	1			T30	25		T32	14		T33	12
all_pins[7]	transitions[0x0=>0x1]	922825	1			T30	12		T32	11		T33	5
all_pins[7]	transitions[0x1=>0x0]	928155	1			T30	4		T32	15		T33	4
all_pins[8]	values[0x0]	2531024	1			T29	1		T30	40		T31	1
all_pins[8]	values[0x1]	1551619	1			T32	19		T33	5		T19	9
all_pins[8]	transitions[0x0=>0x1]	930330	1			T32	12		T33	3		T19	7
all_pins[8]	transitions[0x1=>0x0]	920697	1			T30	25		T32	7		T33	10
all_pins[9]	values[0x0]	2531625	1			T29	1		T30	35		T31	1
all_pins[9]	values[0x1]	1551018	1			T30	5		T32	16		T33	10
all_pins[9]	transitions[0x0=>0x1]	923567	1			T30	5		T32	9		T33	8
all_pins[9]	transitions[0x1=>0x0]	924168	1			T32	12		T33	3		T19	9
all_pins[10]	values[0x0]	2537859	1			T29	1		T30	33		T31	1
all_pins[10]	values[0x1]	1544784	1			T30	7		T32	4		T33	9
all_pins[10]	transitions[0x0=>0x1]	920974	1			T30	3		T32	4		T33	5
all_pins[10]	transitions[0x1=>0x0]	927208	1			T30	1		T32	16		T33	6
all_pins[11]	values[0x0]	2535603	1			T29	1		T30	34		T31	1
all_pins[11]	values[0x1]	1547040	1			T30	6		T32	11		T33	11
all_pins[11]	transitions[0x0=>0x1]	928047	1			T30	3		T32	10		T33	8
all_pins[11]	transitions[0x1=>0x0]	925791	1			T30	4		T32	3		T33	6
all_pins[12]	values[0x0]	2536878	1			T29	1		T30	26		T31	1
all_pins[12]	values[0x1]	1545765	1			T30	14		T32	16		T33	9
all_pins[12]	transitions[0x0=>0x1]	923573	1			T30	11		T32	13		T33	8
all_pins[12]	transitions[0x1=>0x0]	924848	1			T30	3		T32	8		T33	10
all_pins[13]	values[0x0]	2532531	1			T29	1		T30	36		T31	1
all_pins[13]	values[0x1]	1550112	1			T30	4		T32	10		T33	14
all_pins[13]	transitions[0x0=>0x1]	926926	1			T30	4		T32	5		T33	11
all_pins[13]	transitions[0x1=>0x0]	922579	1			T30	14		T32	11		T33	6
all_pins[14]	values[0x0]	2542036	1			T29	1		T30	23		T31	1
all_pins[14]	values[0x1]	1540607	1			T30	17		T32	3		T33	8
all_pins[14]	transitions[0x0=>0x1]	922202	1			T30	17		T32	3		T33	1
all_pins[14]	transitions[0x1=>0x0]	931707	1			T30	4		T32	10		T33	7
all_pins[15]	values[0x0]	2530745	1			T29	1		T30	31		T31	1
all_pins[15]	values[0x1]	1551898	1			T30	9		T32	12		T33	6
all_pins[15]	transitions[0x0=>0x1]	933971	1			T32	12		T33	3		T21	14
all_pins[15]	transitions[0x1=>0x0]	922680	1			T30	8		T32	3		T33	5
all_pins[16]	values[0x0]	2537157	1			T29	1		T30	17		T31	1
all_pins[16]	values[0x1]	1545486	1			T30	23		T32	23		T33	14
all_pins[16]	transitions[0x0=>0x1]	923054	1			T30	16		T32	14		T33	10
all_pins[16]	transitions[0x1=>0x0]	929466	1			T30	2		T32	3		T33	2
all_pins[17]	values[0x0]	2533134	1			T29	1		T30	24		T31	1
all_pins[17]	values[0x1]	1549509	1			T30	16		T32	12		T33	11
all_pins[17]	transitions[0x0=>0x1]	929471	1			T30	9		T32	6		T33	5
all_pins[17]	transitions[0x1=>0x0]	925448	1			T30	16		T32	17		T33	8
all_pins[18]	values[0x0]	2536349	1			T29	1		T30	32		T31	1
all_pins[18]	values[0x1]	1546294	1			T30	8		T32	11		T33	13
all_pins[18]	transitions[0x0=>0x1]	925939	1			T30	7		T32	8		T33	6
all_pins[18]	transitions[0x1=>0x0]	929154	1			T30	15		T32	9		T33	4
all_pins[19]	values[0x0]	2537512	1			T29	1		T30	25		T31	1
all_pins[19]	values[0x1]	1545131	1			T30	15		T32	18		T33	5
all_pins[19]	transitions[0x0=>0x1]	927605	1			T30	14		T32	12		T33	2
all_pins[19]	transitions[0x1=>0x0]	928768	1			T30	7		T32	5		T33	10
all_pins[20]	values[0x0]	2538331	1			T29	1		T30	31		T31	1
all_pins[20]	values[0x1]	1544312	1			T30	9		T32	16		T33	20
all_pins[20]	transitions[0x0=>0x1]	926288	1			T30	1		T32	10		T33	18
all_pins[20]	transitions[0x1=>0x0]	927107	1			T30	7		T32	12		T33	3
all_pins[21]	values[0x0]	2533586	1			T29	1		T30	29		T31	1
all_pins[21]	values[0x1]	1549057	1			T30	11		T32	14		T33	13
all_pins[21]	transitions[0x0=>0x1]	926931	1			T30	7		T32	5		T33	2
all_pins[21]	transitions[0x1=>0x0]	922186	1			T30	5		T32	7		T33	9
all_pins[22]	values[0x0]	2538676	1			T29	1		T30	28		T31	1
all_pins[22]	values[0x1]	1543967	1			T30	12		T32	8		T33	18
all_pins[22]	transitions[0x0=>0x1]	922953	1			T30	5		T32	5		T33	8
all_pins[22]	transitions[0x1=>0x0]	928043	1			T30	4		T32	11		T33	3
all_pins[23]	values[0x0]	2537527	1			T29	1		T30	31		T31	1
all_pins[23]	values[0x1]	1545116	1			T30	9		T32	13		T33	14
all_pins[23]	transitions[0x0=>0x1]	924895	1			T30	9		T32	12		T33	3
all_pins[23]	transitions[0x1=>0x0]	923746	1			T30	12		T32	7		T33	7
all_pins[24]	values[0x0]	2539732	1			T29	1		T30	31		T31	1
all_pins[24]	values[0x1]	1542911	1			T30	9		T32	9		T33	16
all_pins[24]	transitions[0x0=>0x1]	925522	1			T30	7		T32	6		T33	11
all_pins[24]	transitions[0x1=>0x0]	927727	1			T30	7		T32	10		T33	9
all_pins[25]	values[0x0]	2538476	1			T29	1		T30	16		T31	1
all_pins[25]	values[0x1]	1544167	1			T30	24		T32	8		T33	16
all_pins[25]	transitions[0x0=>0x1]	925024	1			T30	22		T32	5		T33	7
all_pins[25]	transitions[0x1=>0x0]	923768	1			T30	7		T32	6		T33	7
all_pins[26]	values[0x0]	2539899	1			T29	1		T30	28		T31	1
all_pins[26]	values[0x1]	1542744	1			T30	12		T32	7		T33	16
all_pins[26]	transitions[0x0=>0x1]	924142	1			T30	9		T32	6		T33	6
all_pins[26]	transitions[0x1=>0x0]	925565	1			T30	21		T32	7		T33	6
all_pins[27]	values[0x0]	2541491	1			T29	1		T30	36		T31	1
all_pins[27]	values[0x1]	1541152	1			T30	4		T32	2		T33	16
all_pins[27]	transitions[0x0=>0x1]	924616	1			T30	2		T32	2		T33	5
all_pins[27]	transitions[0x1=>0x0]	926208	1			T30	10		T32	7		T33	5
all_pins[28]	values[0x0]	2535528	1			T29	1		T30	34		T31	1
all_pins[28]	values[0x1]	1547115	1			T30	6		T32	12		T33	6
all_pins[28]	transitions[0x0=>0x1]	928150	1			T30	6		T32	12		T33	1
all_pins[28]	transitions[0x1=>0x0]	922187	1			T30	4		T32	2		T33	11
all_pins[29]	values[0x0]	2538848	1			T29	1		T30	28		T31	1
all_pins[29]	values[0x1]	1543795	1			T30	12		T32	12		T33	13
all_pins[29]	transitions[0x0=>0x1]	923984	1			T30	12		T32	8		T33	13
all_pins[29]	transitions[0x1=>0x0]	927304	1			T30	6		T32	8		T33	6
all_pins[30]	values[0x0]	2539104	1			T29	1		T30	40		T31	1
all_pins[30]	values[0x1]	1543539	1			T32	13		T33	17		T21	41
all_pins[30]	transitions[0x0=>0x1]	928169	1			T32	8		T33	8		T21	21
all_pins[30]	transitions[0x1=>0x0]	928425	1			T30	12		T32	7		T33	4
all_pins[31]	values[0x0]	2536394	1			T29	1		T30	27		T31	1
all_pins[31]	values[0x1]	1546249	1			T30	13		T32	11		T33	9
all_pins[31]	transitions[0x0=>0x1]	927422	1			T30	13		T32	7		T33	3
all_pins[31]	transitions[0x1=>0x0]	924712	1			T32	9		T33	11		T21	19