Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13672092	1			T29	174		T30	57		T31	300
all_values[1]	13672092	1			T29	174		T30	57		T31	300
all_values[2]	13672092	1			T29	174		T30	57		T31	300
all_values[3]	13672092	1			T29	174		T30	57		T31	300
all_values[4]	13672092	1			T29	174		T30	57		T31	300
all_values[5]	13672092	1			T29	174		T30	57		T31	300
all_values[6]	13672092	1			T29	174		T30	57		T31	300
all_values[7]	13672092	1			T29	174		T30	57		T31	300
all_values[8]	13672092	1			T29	174		T30	57		T31	300
all_values[9]	13672092	1			T29	174		T30	57		T31	300
all_values[10]	13672092	1			T29	174		T30	57		T31	300
all_values[11]	13672092	1			T29	174		T30	57		T31	300
all_values[12]	13672092	1			T29	174		T30	57		T31	300
all_values[13]	13672092	1			T29	174		T30	57		T31	300
all_values[14]	13672092	1			T29	174		T30	57		T31	300
all_values[15]	13672092	1			T29	174		T30	57		T31	300
all_values[16]	13672092	1			T29	174		T30	57		T31	300
all_values[17]	13672092	1			T29	174		T30	57		T31	300
all_values[18]	13672092	1			T29	174		T30	57		T31	300
all_values[19]	13672092	1			T29	174		T30	57		T31	300
all_values[20]	13672092	1			T29	174		T30	57		T31	300
all_values[21]	13672092	1			T29	174		T30	57		T31	300
all_values[22]	13672092	1			T29	174		T30	57		T31	300
all_values[23]	13672092	1			T29	174		T30	57		T31	300
all_values[24]	13672092	1			T29	174		T30	57		T31	300
all_values[25]	13672092	1			T29	174		T30	57		T31	300
all_values[26]	13672092	1			T29	174		T30	57		T31	300
all_values[27]	13672092	1			T29	174		T30	57		T31	300
all_values[28]	13672092	1			T29	174		T30	57		T31	300
all_values[29]	13672092	1			T29	174		T30	57		T31	300
all_values[30]	13672092	1			T29	174		T30	57		T31	300
all_values[31]	13672092	1			T29	174		T30	57		T31	300

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252045315

1

T29

5568

T30

1047

T31

9600

auto[1]

185461629

1

T30

777

T32

1269

T19

589

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101791817

1

T29

5568

T30

493

T31

9600

auto[1]

335715127

1

T30

1331

T32

931

T19

1312

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

432591633

1

T29

5568

T30

1824

T31

9600

auto[1]

4915311

1

T32

161

T19

235

T21

411

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2614625	1			T29	174		T30	18		T31	300
all_values[0]	auto[0]	auto[0]	auto[1]	5178848	1			T30	15		T32	10		T19	12
all_values[0]	auto[0]	auto[1]	auto[0]	559225	1			T30	4		T32	19		T19	15
all_values[0]	auto[0]	auto[1]	auto[1]	5165813	1			T30	20		T32	26		T19	13
all_values[0]	auto[1]	auto[0]	auto[1]	77247	1			T32	3		T19	3		T21	7
all_values[0]	auto[1]	auto[1]	auto[1]	76334	1			T32	1		T19	4		T21	5
all_values[1]	auto[0]	auto[0]	auto[0]	2620905	1			T29	174		T30	13		T31	300
all_values[1]	auto[0]	auto[0]	auto[1]	5177472	1			T30	15		T32	8		T19	28
all_values[1]	auto[0]	auto[1]	auto[0]	572893	1			T30	17		T32	39		T19	9
all_values[1]	auto[0]	auto[1]	auto[1]	5146886	1			T30	12		T19	9		T21	131
all_values[1]	auto[1]	auto[0]	auto[1]	77434	1			T32	2		T19	4		T21	12
all_values[1]	auto[1]	auto[1]	auto[1]	76502	1			T19	3		T21	3		T1	14
all_values[2]	auto[0]	auto[0]	auto[0]	2620578	1			T29	174		T30	1		T31	300
all_values[2]	auto[0]	auto[0]	auto[1]	5188339	1			T30	15		T32	20		T19	28
all_values[2]	auto[0]	auto[1]	auto[0]	555997	1			T30	7		T32	20		T19	12
all_values[2]	auto[0]	auto[1]	auto[1]	5153618	1			T30	34		T32	12		T19	8
all_values[2]	auto[1]	auto[0]	auto[1]	76923	1			T32	2		T19	7		T21	6
all_values[2]	auto[1]	auto[1]	auto[1]	76637	1			T32	3		T19	2		T21	7
all_values[3]	auto[0]	auto[0]	auto[0]	2616701	1			T29	174		T30	3		T31	300
all_values[3]	auto[0]	auto[0]	auto[1]	5159571	1			T30	23		T32	16		T19	27
all_values[3]	auto[0]	auto[1]	auto[0]	572993	1			T30	4		T32	24		T19	8
all_values[3]	auto[0]	auto[1]	auto[1]	5169545	1			T30	27		T32	6		T19	4
all_values[3]	auto[1]	auto[0]	auto[1]	76665	1			T32	4		T19	4		T21	5
all_values[3]	auto[1]	auto[1]	auto[1]	76617	1			T32	1		T21	5		T1	16
all_values[4]	auto[0]	auto[0]	auto[0]	2614528	1			T29	174		T30	7		T31	300
all_values[4]	auto[0]	auto[0]	auto[1]	5197749	1			T30	33		T32	3		T19	22
all_values[4]	auto[0]	auto[1]	auto[0]	557030	1			T30	6		T32	31		T19	7
all_values[4]	auto[0]	auto[1]	auto[1]	5149349	1			T30	11		T32	10		T19	9
all_values[4]	auto[1]	auto[0]	auto[1]	76897	1			T32	2		T19	8		T21	5
all_values[4]	auto[1]	auto[1]	auto[1]	76539	1			T32	2		T19	2		T21	5
all_values[5]	auto[0]	auto[0]	auto[0]	2619808	1			T29	174		T30	13		T31	300
all_values[5]	auto[0]	auto[0]	auto[1]	5149390	1			T30	8		T32	23		T19	28
all_values[5]	auto[0]	auto[1]	auto[0]	561105	1			T30	18		T32	27		T19	5
all_values[5]	auto[0]	auto[1]	auto[1]	5188241	1			T30	18		T32	13		T19	11
all_values[5]	auto[1]	auto[0]	auto[1]	77078	1			T32	5		T19	7		T21	9
all_values[5]	auto[1]	auto[1]	auto[1]	76470	1			T19	1		T21	3		T1	10
all_values[6]	auto[0]	auto[0]	auto[0]	2617963	1			T29	174		T30	11		T31	300
all_values[6]	auto[0]	auto[0]	auto[1]	5174271	1			T30	15		T32	13		T19	21
all_values[6]	auto[0]	auto[1]	auto[0]	554138	1			T30	8		T32	26		T19	18
all_values[6]	auto[0]	auto[1]	auto[1]	5171815	1			T30	23		T32	17		T19	12
all_values[6]	auto[1]	auto[0]	auto[1]	77289	1			T32	3		T19	4		T21	6
all_values[6]	auto[1]	auto[1]	auto[1]	76616	1			T32	5		T19	1		T21	8
all_values[7]	auto[0]	auto[0]	auto[0]	2627977	1			T29	174		T30	2		T31	300
all_values[7]	auto[0]	auto[0]	auto[1]	5155333	1			T30	3		T32	7		T19	25
all_values[7]	auto[0]	auto[1]	auto[0]	558924	1			T30	12		T32	45		T19	6
all_values[7]	auto[0]	auto[1]	auto[1]	5176148	1			T30	40		T32	10		T19	6
all_values[7]	auto[1]	auto[0]	auto[1]	76786	1			T32	2		T19	5		T21	5
all_values[7]	auto[1]	auto[1]	auto[1]	76924	1			T32	6		T19	2		T21	9
all_values[8]	auto[0]	auto[0]	auto[0]	2614028	1			T29	174		T30	5		T31	300
all_values[8]	auto[0]	auto[0]	auto[1]	5151945	1			T30	46		T32	4		T19	23
all_values[8]	auto[0]	auto[1]	auto[0]	554083	1			T30	6		T32	19		T19	19
all_values[8]	auto[0]	auto[1]	auto[1]	5198053	1			T32	17		T19	12		T21	91
all_values[8]	auto[1]	auto[0]	auto[1]	77322	1			T32	2		T19	4		T21	10
all_values[8]	auto[1]	auto[1]	auto[1]	76661	1			T32	3		T21	7		T1	6
all_values[9]	auto[0]	auto[0]	auto[0]	2626286	1			T29	174		T30	11		T31	300
all_values[9]	auto[0]	auto[0]	auto[1]	5175783	1			T30	30		T32	7		T19	29
all_values[9]	auto[0]	auto[1]	auto[0]	551396	1			T30	7		T32	40		T19	9
all_values[9]	auto[0]	auto[1]	auto[1]	5165106	1			T30	9		T32	12		T21	208
all_values[9]	auto[1]	auto[0]	auto[1]	77216	1			T32	1		T19	7		T21	4
all_values[9]	auto[1]	auto[1]	auto[1]	76305	1			T32	6		T19	3		T21	7
all_values[10]	auto[0]	auto[0]	auto[0]	2617336	1			T29	174		T30	32		T31	300
all_values[10]	auto[0]	auto[0]	auto[1]	5151779	1			T30	14		T32	22		T19	30
all_values[10]	auto[0]	auto[1]	auto[0]	564644	1			T32	27		T19	12		T21	17
all_values[10]	auto[0]	auto[1]	auto[1]	5184823	1			T30	11		T32	5		T19	5
all_values[10]	auto[1]	auto[0]	auto[1]	76846	1			T32	5		T19	4		T21	8
all_values[10]	auto[1]	auto[1]	auto[1]	76664	1			T19	3		T21	6		T1	9
all_values[11]	auto[0]	auto[0]	auto[0]	2621647	1			T29	174		T30	11		T31	300
all_values[11]	auto[0]	auto[0]	auto[1]	5176446	1			T30	25		T32	6		T19	29
all_values[11]	auto[0]	auto[1]	auto[0]	558415	1			T30	10		T32	22		T19	5
all_values[11]	auto[0]	auto[1]	auto[1]	5162155	1			T30	11		T32	10		T19	10
all_values[11]	auto[1]	auto[0]	auto[1]	76679	1			T32	2		T19	7		T21	13
all_values[11]	auto[1]	auto[1]	auto[1]	76750	1			T32	3		T19	4		T21	3
all_values[12]	auto[0]	auto[0]	auto[0]	2618021	1			T29	174		T30	6		T31	300
all_values[12]	auto[0]	auto[0]	auto[1]	5170057	1			T30	21		T32	12		T19	22
all_values[12]	auto[0]	auto[1]	auto[0]	567180	1			T30	9		T32	31		T19	7
all_values[12]	auto[0]	auto[1]	auto[1]	5163698	1			T30	21		T32	13		T19	6
all_values[12]	auto[1]	auto[0]	auto[1]	76585	1			T32	2		T19	5		T21	3
all_values[12]	auto[1]	auto[1]	auto[1]	76551	1			T32	5		T19	1		T21	9
all_values[13]	auto[0]	auto[0]	auto[0]	2617703	1			T29	174		T30	7		T31	300
all_values[13]	auto[0]	auto[0]	auto[1]	5148821	1			T30	44		T32	19		T19	28
all_values[13]	auto[0]	auto[1]	auto[0]	564071	1			T32	19		T19	14		T21	14
all_values[13]	auto[0]	auto[1]	auto[1]	5188103	1			T30	6		T32	8		T19	4
all_values[13]	auto[1]	auto[0]	auto[1]	76476	1			T32	2		T19	6		T21	9
all_values[13]	auto[1]	auto[1]	auto[1]	76918	1			T32	1		T19	2		T21	5
all_values[14]	auto[0]	auto[0]	auto[0]	2625447	1			T29	174		T30	4		T31	300
all_values[14]	auto[0]	auto[0]	auto[1]	5222428	1			T30	30		T32	20		T19	27
all_values[14]	auto[0]	auto[1]	auto[0]	562615	1			T32	29		T19	10		T21	16
all_values[14]	auto[0]	auto[1]	auto[1]	5108044	1			T30	23		T32	2		T19	9
all_values[14]	auto[1]	auto[0]	auto[1]	77270	1			T32	4		T19	6		T21	2
all_values[14]	auto[1]	auto[1]	auto[1]	76288	1			T32	3		T19	3		T21	11
all_values[15]	auto[0]	auto[0]	auto[0]	2613102	1			T29	174		T30	7		T31	300
all_values[15]	auto[0]	auto[0]	auto[1]	5150174	1			T30	16		T32	13		T19	31
all_values[15]	auto[0]	auto[1]	auto[0]	563012	1			T30	19		T32	26		T19	2
all_values[15]	auto[0]	auto[1]	auto[1]	5192345	1			T30	15		T32	11		T21	64
all_values[15]	auto[1]	auto[0]	auto[1]	76636	1			T32	2		T19	6		T21	11
all_values[15]	auto[1]	auto[1]	auto[1]	76823	1			T32	2		T19	1		T21	3
all_values[16]	auto[0]	auto[0]	auto[0]	2617112	1			T29	174		T30	1		T31	300
all_values[16]	auto[0]	auto[0]	auto[1]	5198429	1			T30	16		T32	7		T19	32
all_values[16]	auto[0]	auto[1]	auto[0]	553193	1			T30	9		T32	33		T19	10
all_values[16]	auto[0]	auto[1]	auto[1]	5149810	1			T30	31		T32	20		T19	8
all_values[16]	auto[1]	auto[0]	auto[1]	76463	1			T32	2		T19	6		T21	9
all_values[16]	auto[1]	auto[1]	auto[1]	77085	1			T32	4		T19	1		T21	2
all_values[17]	auto[0]	auto[0]	auto[0]	2616015	1			T29	174		T30	10		T31	300
all_values[17]	auto[0]	auto[0]	auto[1]	5195792	1			T30	16		T32	13		T19	26
all_values[17]	auto[0]	auto[1]	auto[0]	571470	1			T30	4		T32	14		T19	12
all_values[17]	auto[0]	auto[1]	auto[1]	5135653	1			T30	27		T32	11		T19	5
all_values[17]	auto[1]	auto[0]	auto[1]	76443	1			T32	3		T19	6		T21	7
all_values[17]	auto[1]	auto[1]	auto[1]	76719	1			T32	2		T19	1		T21	9
all_values[18]	auto[0]	auto[0]	auto[0]	2627185	1			T29	174		T30	10		T31	300
all_values[18]	auto[0]	auto[0]	auto[1]	5177119	1			T30	24		T32	9		T19	24
all_values[18]	auto[0]	auto[1]	auto[0]	562505	1			T30	10		T32	44		T19	14
all_values[18]	auto[0]	auto[1]	auto[1]	5151638	1			T30	13		T32	10		T19	10
all_values[18]	auto[1]	auto[0]	auto[1]	76677	1			T32	4		T19	4		T21	9
all_values[18]	auto[1]	auto[1]	auto[1]	76968	1			T32	2		T19	2		T21	5
all_values[19]	auto[0]	auto[0]	auto[0]	2629811	1			T29	174		T30	1		T31	300
all_values[19]	auto[0]	auto[0]	auto[1]	5186534	1			T30	25		T32	10		T19	33
all_values[19]	auto[0]	auto[1]	auto[0]	563856	1			T30	6		T32	21		T19	13
all_values[19]	auto[0]	auto[1]	auto[1]	5138032	1			T30	25		T32	20		T19	4
all_values[19]	auto[1]	auto[0]	auto[1]	77743	1			T32	4		T19	5		T21	8
all_values[19]	auto[1]	auto[1]	auto[1]	76116	1			T19	4		T21	7		T1	8
all_values[20]	auto[0]	auto[0]	auto[0]	2620609	1			T29	174		T30	17		T31	300
all_values[20]	auto[0]	auto[0]	auto[1]	5194177	1			T30	25		T32	8		T19	22
all_values[20]	auto[0]	auto[1]	auto[0]	555158	1			T30	4		T32	37		T19	14
all_values[20]	auto[0]	auto[1]	auto[1]	5148494	1			T30	11		T32	14		T19	16
all_values[20]	auto[1]	auto[0]	auto[1]	77185	1			T32	2		T19	4		T21	9
all_values[20]	auto[1]	auto[1]	auto[1]	76469	1			T32	2		T19	1		T21	5
all_values[21]	auto[0]	auto[0]	auto[0]	2622766	1			T29	174		T30	3		T31	300
all_values[21]	auto[0]	auto[0]	auto[1]	5165487	1			T30	24		T32	10		T19	16
all_values[21]	auto[0]	auto[1]	auto[0]	565211	1			T30	13		T32	32		T19	5
all_values[21]	auto[0]	auto[1]	auto[1]	5165162	1			T30	17		T32	10		T19	3
all_values[21]	auto[1]	auto[0]	auto[1]	76934	1			T32	3		T19	5		T21	8
all_values[21]	auto[1]	auto[1]	auto[1]	76532	1			T32	3		T19	1		T21	6
all_values[22]	auto[0]	auto[0]	auto[0]	2619024	1			T29	174		T30	13		T31	300
all_values[22]	auto[0]	auto[0]	auto[1]	5196823	1			T30	25		T32	14		T19	30
all_values[22]	auto[0]	auto[1]	auto[0]	557290	1			T30	1		T32	14		T19	12
all_values[22]	auto[0]	auto[1]	auto[1]	5145497	1			T30	18		T32	10		T19	8
all_values[22]	auto[1]	auto[0]	auto[1]	76885	1			T32	3		T19	6		T21	5
all_values[22]	auto[1]	auto[1]	auto[1]	76573	1			T19	5		T21	7		T1	8
all_values[23]	auto[0]	auto[0]	auto[0]	2622732	1			T29	174		T30	15		T31	300
all_values[23]	auto[0]	auto[0]	auto[1]	5181913	1			T30	16		T32	14		T19	30
all_values[23]	auto[0]	auto[1]	auto[0]	566064	1			T30	7		T32	21		T19	7
all_values[23]	auto[0]	auto[1]	auto[1]	5147470	1			T30	19		T32	12		T19	8
all_values[23]	auto[1]	auto[0]	auto[1]	77749	1			T32	2		T19	5		T21	2
all_values[23]	auto[1]	auto[1]	auto[1]	76164	1			T32	2		T19	2		T21	8
all_values[24]	auto[0]	auto[0]	auto[0]	2627046	1			T29	174		T30	13		T31	300
all_values[24]	auto[0]	auto[0]	auto[1]	5177648	1			T30	23		T32	21		T19	18
all_values[24]	auto[0]	auto[1]	auto[0]	563484	1			T30	6		T32	25		T19	9
all_values[24]	auto[0]	auto[1]	auto[1]	5150062	1			T30	15		T32	9		T19	6
all_values[24]	auto[1]	auto[0]	auto[1]	76790	1			T32	2		T19	4		T21	5
all_values[24]	auto[1]	auto[1]	auto[1]	77062	1			T32	2		T21	5		T1	4
all_values[25]	auto[0]	auto[0]	auto[0]	2617540	1			T29	174		T30	1		T31	300
all_values[25]	auto[0]	auto[0]	auto[1]	5187382	1			T30	20		T32	16		T19	26
all_values[25]	auto[0]	auto[1]	auto[0]	556459	1			T30	4		T32	22		T19	5
all_values[25]	auto[0]	auto[1]	auto[1]	5157133	1			T30	32		T32	7		T19	10
all_values[25]	auto[1]	auto[0]	auto[1]	76875	1			T32	4		T19	9		T21	4
all_values[25]	auto[1]	auto[1]	auto[1]	76703	1			T32	1		T19	2		T21	8
all_values[26]	auto[0]	auto[0]	auto[0]	2617234	1			T29	174		T30	12		T31	300
all_values[26]	auto[0]	auto[0]	auto[1]	5176342	1			T30	14		T32	23		T19	32
all_values[26]	auto[0]	auto[1]	auto[0]	562724	1			T30	9		T32	20		T19	11
all_values[26]	auto[0]	auto[1]	auto[1]	5162861	1			T30	22		T32	5		T19	5
all_values[26]	auto[1]	auto[0]	auto[1]	76819	1			T32	4		T19	5		T21	6
all_values[26]	auto[1]	auto[1]	auto[1]	76112	1			T32	2		T19	1		T21	8
all_values[27]	auto[0]	auto[0]	auto[0]	2621188	1			T29	174		T30	12		T31	300
all_values[27]	auto[0]	auto[0]	auto[1]	5207644	1			T30	40		T32	19		T19	35
all_values[27]	auto[0]	auto[1]	auto[0]	556001	1			T32	18		T19	4		T21	28
all_values[27]	auto[0]	auto[1]	auto[1]	5133446	1			T30	5		T32	3		T19	4
all_values[27]	auto[1]	auto[0]	auto[1]	77541	1			T32	2		T19	8		T21	10
all_values[27]	auto[1]	auto[1]	auto[1]	76272	1			T32	1		T19	3		T21	1
all_values[28]	auto[0]	auto[0]	auto[0]	2615887	1			T29	174		T30	1		T31	300
all_values[28]	auto[0]	auto[0]	auto[1]	5196230	1			T30	44		T32	20		T19	27
all_values[28]	auto[0]	auto[1]	auto[0]	557536	1			T30	4		T32	9		T19	2
all_values[28]	auto[0]	auto[1]	auto[1]	5148347	1			T30	8		T32	13		T19	8
all_values[28]	auto[1]	auto[0]	auto[1]	77602	1			T32	6		T19	9		T21	7
all_values[28]	auto[1]	auto[1]	auto[1]	76490	1			T32	1		T21	3		T1	17
all_values[29]	auto[0]	auto[0]	auto[0]	2627705	1			T29	174		T30	7		T31	300
all_values[29]	auto[0]	auto[0]	auto[1]	5166085	1			T30	27		T32	17		T19	20
all_values[29]	auto[0]	auto[1]	auto[0]	564234	1			T30	3		T32	30		T19	13
all_values[29]	auto[0]	auto[1]	auto[1]	5160201	1			T30	20		T32	9		T19	5
all_values[29]	auto[1]	auto[0]	auto[1]	77511	1			T32	3		T19	4		T21	11
all_values[29]	auto[1]	auto[1]	auto[1]	76356	1			T32	3		T19	2		T21	5
all_values[30]	auto[0]	auto[0]	auto[0]	2618342	1			T29	174		T30	8		T31	300
all_values[30]	auto[0]	auto[0]	auto[1]	5225821	1			T30	49		T32	9		T19	37
all_values[30]	auto[0]	auto[1]	auto[0]	556997	1			T32	34		T19	10		T21	13
all_values[30]	auto[0]	auto[1]	auto[1]	5117312	1			T32	12		T21	132		T116	1147
all_values[30]	auto[1]	auto[0]	auto[1]	76968	1			T32	2		T19	5		T21	6
all_values[30]	auto[1]	auto[1]	auto[1]	76652	1			T32	2		T21	4		T1	11
all_values[31]	auto[0]	auto[0]	auto[0]	2613374	1			T29	174		T30	8		T31	300
all_values[31]	auto[0]	auto[0]	auto[1]	5178736	1			T30	23		T32	9		T19	37
all_values[31]	auto[0]	auto[1]	auto[0]	561689	1			T30	3		T32	33		T19	10
all_values[31]	auto[0]	auto[1]	auto[1]	5164388	1			T30	23		T32	11		T19	4
all_values[31]	auto[1]	auto[0]	auto[1]	76988	1			T32	2		T19	5		T21	4
all_values[31]	auto[1]	auto[1]	auto[1]	76917	1			T32	2		T19	1		T21	7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal