Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[1]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[2]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[3]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[4]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[5]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[6]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[7]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[8]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[9]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[10]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[11]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[12]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[13]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[14]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[15]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[16]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[17]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[18]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[19]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[20]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[21]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[22]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[23]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[24]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[25]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[26]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[27]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[28]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[29]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[30]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[31]	13513157	1			T29	301		T30	29		T31	560

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

259929214

1

T29

7794

T30

506

T31

13202

auto[1]

172491810

1

T29

1838

T30

422

T31

4718

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345254256

1

T29

8858

T30

928

T31

9625

auto[1]

87166768

1

T29

774

T31

8295

T32

215

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320038762

1

T29

4274

T30

928

T31

9440

auto[1]

112382262

1

T29

5358

T31

8480

T32

895

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5004016	1			T29	153		T30	17		T31	143
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3631171	1			T29	27		T30	12		T31	20
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1366782	1			T29	12		T31	146		T32	12
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1747311	1			T29	82		T31	128		T32	14
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	406840	1			T29	13		T32	7		T19	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1357037	1			T29	14		T31	123		T32	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5010692	1			T29	121		T30	11		T31	126
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3624051	1			T29	24		T30	18		T31	16
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1368511	1			T29	14		T31	130		T32	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1747409	1			T29	119		T31	138		T32	7
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	408199	1			T29	15		T32	2		T19	7
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1354295	1			T29	8		T31	150		T32	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5013066	1			T29	165		T30	15		T31	177
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3616239	1			T29	24		T30	14		T31	10
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1366695	1			T29	10		T31	110		T32	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1749116	1			T29	79		T31	132		T32	26
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	409390	1			T29	9		T32	11		T19	6
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1358651	1			T29	14		T31	131		T32	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5005628	1			T29	71		T30	14		T31	131
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3622835	1			T29	23		T30	15		T31	20
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1372219	1			T29	10		T31	145		T32	6
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1740383	1			T29	148		T31	144		T32	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	406672	1			T29	33		T32	7		T21	4
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1365420	1			T29	16		T31	120		T32	14
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5007690	1			T29	171		T30	21		T31	132
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3621506	1			T29	27		T30	8		T31	25
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1372368	1			T29	6		T31	144		T32	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1748231	1			T29	76		T31	135		T32	21
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	407474	1			T29	15		T32	5		T19	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1355888	1			T29	6		T31	124		T34	58
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5003675	1			T29	96		T30	12		T31	143
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3634163	1			T29	32		T30	17		T31	18
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1369964	1			T29	12		T31	143		T32	9
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1741309	1			T29	131		T31	126		T32	20
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	409561	1			T29	20		T32	17		T19	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1354485	1			T29	10		T31	130		T32	8
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5008646	1			T29	63		T30	13		T31	161
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3622203	1			T29	8		T30	16		T31	20
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1369599	1			T29	6		T31	144		T32	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1746829	1			T29	172		T31	123		T32	16
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	409163	1			T29	28		T32	9		T19	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1356717	1			T29	24		T31	112		T32	5
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5003547	1			T29	120		T30	16		T31	146
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3628470	1			T29	24		T30	13		T31	16
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1368354	1			T29	14		T31	134		T34	43
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1744507	1			T29	103		T31	134		T34	58
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	411141	1			T29	24		T32	13		T19	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1357138	1			T29	16		T31	130		T32	7
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4996052	1			T29	76		T30	19		T31	143
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3628024	1			T29	16		T30	10		T31	18
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1369537	1			T29	6		T31	128		T32	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1748618	1			T29	149		T31	135		T32	16
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	408688	1			T29	23		T32	11		T19	8
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1362238	1			T29	31		T31	136		T32	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4999852	1			T29	93		T30	17		T31	160
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3624665	1			T29	20		T30	12		T31	19
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1369756	1			T29	20		T31	150		T32	9
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1747092	1			T29	129		T31	120		T32	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	410390	1			T29	20		T32	5		T19	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1361402	1			T29	19		T31	111		T32	2
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5002887	1			T29	95		T30	17		T31	133
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3636747	1			T29	18		T30	12		T31	17
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1369982	1			T29	11		T31	118		T32	6
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1738947	1			T29	144		T31	170		T32	21
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	407628	1			T29	25		T32	13		T19	6
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1356966	1			T29	8		T31	122		T32	3
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4997794	1			T29	108		T30	16		T31	130
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3636642	1			T29	24		T30	13		T31	19
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1373465	1			T29	10		T31	168		T34	41
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1737772	1			T29	121		T31	82		T32	21
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	408349	1			T29	26		T32	5		T19	8
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1359135	1			T29	12		T31	161		T32	4
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5005012	1			T29	128		T30	15		T31	179
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3628620	1			T29	28		T30	14		T31	17
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1368585	1			T29	20		T31	108		T34	55
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1744008	1			T29	90		T31	112		T34	62
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	408021	1			T29	23		T32	8		T24	127
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1358911	1			T29	12		T31	144		T32	5
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5003880	1			T29	62		T30	10		T31	169
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3621505	1			T29	11		T30	19		T31	15
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1369635	1			T29	10		T31	144		T32	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1746015	1			T29	170		T31	140		T32	13
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	411922	1			T29	36		T32	10		T19	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1360200	1			T29	12		T31	92		T32	4
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5007727	1			T29	79		T30	20		T31	155
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3624243	1			T29	23		T30	9		T31	18
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1369664	1			T29	20		T31	148		T34	76
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1746299	1			T29	132		T31	135		T32	36
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	409715	1			T29	35		T32	4		T19	2
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1355509	1			T29	12		T31	104		T32	10
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5001561	1			T29	128		T30	18		T31	132
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3630178	1			T29	15		T30	11		T31	20
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1375403	1			T29	14		T31	120		T32	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1739230	1			T29	108		T31	140		T32	20
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	410041	1			T29	18		T32	13		T19	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1356744	1			T29	18		T31	148		T32	8
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5013966	1			T29	92		T30	21		T31	151
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3621125	1			T29	21		T30	8		T31	22
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1363363	1			T29	22		T31	104		T32	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1752627	1			T29	127		T31	170		T32	12
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	410176	1			T29	30		T32	6		T19	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1351900	1			T29	9		T31	113		T32	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5013010	1			T29	103		T30	14		T31	167
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3616090	1			T29	16		T30	15		T31	16
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1368183	1			T29	10		T31	133		T32	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1751482	1			T29	144		T31	140		T32	19
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	410371	1			T29	22		T32	6		T21	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1354021	1			T29	6		T31	104		T32	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5008029	1			T29	148		T30	12		T31	138
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3630533	1			T29	27		T30	17		T31	11
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1367939	1			T29	20		T31	116		T32	3
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1744984	1			T29	90		T31	146		T32	20
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	407446	1			T29	10		T32	5		T21	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1354226	1			T29	6		T31	149		T32	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5008824	1			T29	130		T30	18		T31	173
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3623119	1			T29	17		T30	11		T31	17
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1365131	1			T29	18		T31	118		T32	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1754547	1			T29	114		T31	138		T32	7
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	407436	1			T29	18		T32	13		T19	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1354100	1			T29	4		T31	114		T32	4
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5020553	1			T29	90		T30	14		T31	118
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3616412	1			T29	24		T30	15		T31	20
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1367513	1			T29	5		T31	98		T32	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1744838	1			T29	137		T31	158		T32	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	410143	1			T29	26		T32	2		T19	4
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1353698	1			T29	19		T31	166		T32	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5002343	1			T29	76		T30	17		T31	160
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3625470	1			T29	16		T30	12		T31	17
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1372266	1			T31	140		T32	5		T34	60
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1748784	1			T29	164		T31	138		T32	24
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	409202	1			T29	30		T32	5		T19	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1355092	1			T29	15		T31	105		T32	2
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5000219	1			T29	39		T30	21		T31	125
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3638642	1			T29	11		T30	8		T31	21
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1364197	1			T29	6		T31	146		T32	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1750673	1			T29	189		T31	166		T32	20
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	406918	1			T29	40		T32	6		T19	6
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1352508	1			T29	16		T31	102		T34	72
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5007156	1			T29	32		T30	14		T31	143
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3628009	1			T29	6		T30	15		T31	20
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1367707	1			T29	2		T31	150		T32	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1751388	1			T29	195		T31	129		T32	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	410273	1			T29	42		T32	9		T21	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1348624	1			T29	24		T31	118		T32	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5015634	1			T29	153		T30	12		T31	152
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3619873	1			T29	35		T30	17		T31	24
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1365537	1			T29	18		T31	132		T32	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1751376	1			T29	74		T31	124		T32	19
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	405448	1			T29	15		T32	10		T19	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1355289	1			T29	6		T31	128		T34	46
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5002798	1			T29	86		T30	10		T31	122
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3625282	1			T29	20		T30	19		T31	21
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1366543	1			T29	10		T31	118		T32	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1755955	1			T29	148		T31	140		T32	17
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	408479	1			T29	21		T32	10		T19	12
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1354100	1			T29	16		T31	159		T32	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5012781	1			T29	191		T30	23		T31	187
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3623319	1			T29	38		T30	6		T31	17
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1362209	1			T29	10		T31	120		T32	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1754965	1			T29	45		T31	104		T32	29
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	410456	1			T29	13		T32	4		T19	12
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1349427	1			T29	4		T31	132		T32	2
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4998587	1			T29	55		T30	23		T31	140
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3632748	1			T29	9		T30	6		T31	21
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1364257	1			T31	96		T32	3		T34	54
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1752097	1			T29	180		T31	166		T32	9
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	410220	1			T29	36		T32	8		T19	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1355248	1			T29	21		T31	137		T32	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5024465	1			T29	104		T30	10		T31	156
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3613775	1			T29	19		T30	19		T31	17
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1368571	1			T29	10		T31	124		T32	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1748675	1			T29	129		T31	146		T32	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	405605	1			T29	23		T32	9		T19	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1352066	1			T29	16		T31	117		T32	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5015863	1			T29	94		T30	14		T31	126
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3627907	1			T29	14		T30	15		T31	21
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1367881	1			T29	8		T31	142		T32	12
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1740883	1			T29	154		T31	124		T32	13
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	410323	1			T29	23		T32	16		T19	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1350300	1			T29	8		T31	147		T32	8
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5005323	1			T29	122		T30	13		T31	134
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3625827	1			T29	16		T30	16		T31	22
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1367756	1			T29	6		T31	120		T32	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1752599	1			T29	125		T31	132		T32	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	409445	1			T29	24		T32	7		T19	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1352207	1			T29	8		T31	152		T34	38
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4998260	1			T29	44		T30	19		T31	117
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3631291	1			T29	9		T30	10		T31	22
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1368970	1			T29	4		T31	137		T34	72
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1752187	1			T29	194		T31	144		T32	21
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	407765	1			T29	30		T32	14		T21	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1354684	1			T29	20		T31	140		T32	3

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal