Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[1]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[2]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[3]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[4]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[5]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[6]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[7]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[8]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[9]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[10]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[11]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[12]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[13]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[14]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[15]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[16]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[17]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[18]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[19]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[20]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[21]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[22]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[23]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[24]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[25]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[26]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[27]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[28]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[29]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[30]	13513157	1			T29	301		T30	29		T31	560
bins_for_gpio_bits[31]	13513157	1			T29	301		T30	29		T31	560

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

259929214

1

T29

7794

T30

506

T31

13202

auto[1]

172491810

1

T29

1838

T30

422

T31

4718

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

259921652

1

T29

7792

T30

506

T31

13191

auto[1]

172499372

1

T29

1840

T30

422

T31

4729

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7874338	1			T29	241		T30	17		T31	382
bins_for_gpio_bits[0]	auto[0]	auto[1]	243522	1			T29	6		T31	34		T34	16
bins_for_gpio_bits[0]	auto[1]	auto[0]	243771	1			T29	6		T31	35		T34	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	5151526	1			T29	48		T30	12		T31	109
bins_for_gpio_bits[1]	auto[0]	auto[0]	7883386	1			T29	251		T30	11		T31	361
bins_for_gpio_bits[1]	auto[0]	auto[1]	242997	1			T29	3		T31	33		T34	16
bins_for_gpio_bits[1]	auto[1]	auto[0]	243226	1			T29	3		T31	33		T34	16
bins_for_gpio_bits[1]	auto[1]	auto[1]	5143548	1			T29	44		T30	18		T31	133
bins_for_gpio_bits[2]	auto[0]	auto[0]	7885304	1			T29	251		T30	15		T31	388
bins_for_gpio_bits[2]	auto[0]	auto[1]	243344	1			T29	3		T31	30		T34	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	243573	1			T29	3		T31	31		T34	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	5140936	1			T29	44		T30	14		T31	111
bins_for_gpio_bits[3]	auto[0]	auto[0]	7874023	1			T29	223		T30	14		T31	389
bins_for_gpio_bits[3]	auto[0]	auto[1]	243983	1			T29	6		T31	31		T32	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	244207	1			T29	6		T31	31		T34	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	5150944	1			T29	66		T30	15		T31	109
bins_for_gpio_bits[4]	auto[0]	auto[0]	7884449	1			T29	250		T30	21		T31	374
bins_for_gpio_bits[4]	auto[0]	auto[1]	243631	1			T29	3		T31	37		T34	18
bins_for_gpio_bits[4]	auto[1]	auto[0]	243840	1			T29	3		T31	37		T34	18
bins_for_gpio_bits[4]	auto[1]	auto[1]	5141237	1			T29	45		T30	8		T31	112
bins_for_gpio_bits[5]	auto[0]	auto[0]	7871377	1			T29	234		T30	12		T31	378
bins_for_gpio_bits[5]	auto[0]	auto[1]	243345	1			T29	5		T31	34		T34	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	243571	1			T29	5		T31	34		T34	13
bins_for_gpio_bits[5]	auto[1]	auto[1]	5154864	1			T29	57		T30	17		T31	114
bins_for_gpio_bits[6]	auto[0]	auto[0]	7881381	1			T29	235		T30	13		T31	401
bins_for_gpio_bits[6]	auto[0]	auto[1]	243503	1			T29	6		T31	27		T34	13
bins_for_gpio_bits[6]	auto[1]	auto[0]	243693	1			T29	6		T31	27		T34	13
bins_for_gpio_bits[6]	auto[1]	auto[1]	5144580	1			T29	54		T30	16		T31	105
bins_for_gpio_bits[7]	auto[0]	auto[0]	7872773	1			T29	232		T30	16		T31	381
bins_for_gpio_bits[7]	auto[0]	auto[1]	243393	1			T29	5		T31	33		T34	10
bins_for_gpio_bits[7]	auto[1]	auto[0]	243635	1			T29	5		T31	33		T34	10
bins_for_gpio_bits[7]	auto[1]	auto[1]	5153356	1			T29	59		T30	13		T31	113
bins_for_gpio_bits[8]	auto[0]	auto[0]	7869596	1			T29	222		T30	19		T31	377
bins_for_gpio_bits[8]	auto[0]	auto[1]	244424	1			T29	9		T31	29		T34	17
bins_for_gpio_bits[8]	auto[1]	auto[0]	244611	1			T29	9		T31	29		T34	17
bins_for_gpio_bits[8]	auto[1]	auto[1]	5154526	1			T29	61		T30	10		T31	125
bins_for_gpio_bits[9]	auto[0]	auto[0]	7873021	1			T29	235		T30	17		T31	400
bins_for_gpio_bits[9]	auto[0]	auto[1]	243462	1			T29	7		T31	29		T34	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	243679	1			T29	7		T31	30		T34	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	5152995	1			T29	52		T30	12		T31	101
bins_for_gpio_bits[10]	auto[0]	auto[0]	7868318	1			T29	248		T30	17		T31	383
bins_for_gpio_bits[10]	auto[0]	auto[1]	243255	1			T29	2		T31	38		T34	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	243498	1			T29	2		T31	38		T34	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	5158086	1			T29	49		T30	12		T31	101
bins_for_gpio_bits[11]	auto[0]	auto[0]	7865410	1			T29	234		T30	16		T31	347
bins_for_gpio_bits[11]	auto[0]	auto[1]	243384	1			T29	5		T31	32		T34	15
bins_for_gpio_bits[11]	auto[1]	auto[0]	243621	1			T29	5		T31	33		T34	15
bins_for_gpio_bits[11]	auto[1]	auto[1]	5160742	1			T29	57		T30	13		T31	148
bins_for_gpio_bits[12]	auto[0]	auto[0]	7874410	1			T29	233		T30	15		T31	368
bins_for_gpio_bits[12]	auto[0]	auto[1]	242943	1			T29	5		T31	31		T34	16
bins_for_gpio_bits[12]	auto[1]	auto[0]	243195	1			T29	5		T31	31		T34	16
bins_for_gpio_bits[12]	auto[1]	auto[1]	5152609	1			T29	58		T30	14		T31	130
bins_for_gpio_bits[13]	auto[0]	auto[0]	7875750	1			T29	237		T30	10		T31	423
bins_for_gpio_bits[13]	auto[0]	auto[1]	243521	1			T29	5		T31	30		T34	19
bins_for_gpio_bits[13]	auto[1]	auto[0]	243780	1			T29	5		T31	30		T34	19
bins_for_gpio_bits[13]	auto[1]	auto[1]	5150106	1			T29	54		T30	19		T31	77
bins_for_gpio_bits[14]	auto[0]	auto[0]	7879842	1			T29	227		T30	20		T31	406
bins_for_gpio_bits[14]	auto[0]	auto[1]	243571	1			T29	4		T31	32		T34	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	243848	1			T29	4		T31	32		T34	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	5145896	1			T29	66		T30	9		T31	90
bins_for_gpio_bits[15]	auto[0]	auto[0]	7872573	1			T29	245		T30	18		T31	358
bins_for_gpio_bits[15]	auto[0]	auto[1]	243397	1			T29	5		T31	34		T34	15
bins_for_gpio_bits[15]	auto[1]	auto[0]	243621	1			T29	5		T31	34		T34	15
bins_for_gpio_bits[15]	auto[1]	auto[1]	5153566	1			T29	46		T30	11		T31	134
bins_for_gpio_bits[16]	auto[0]	auto[0]	7886278	1			T29	236		T30	21		T31	395
bins_for_gpio_bits[16]	auto[0]	auto[1]	243449	1			T29	4		T31	29		T34	17
bins_for_gpio_bits[16]	auto[1]	auto[0]	243678	1			T29	5		T31	30		T34	17
bins_for_gpio_bits[16]	auto[1]	auto[1]	5139752	1			T29	56		T30	8		T31	106
bins_for_gpio_bits[17]	auto[0]	auto[0]	7888266	1			T29	254		T30	14		T31	414
bins_for_gpio_bits[17]	auto[0]	auto[1]	244180	1			T29	3		T31	26		T34	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	244409	1			T29	3		T31	26		T34	12
bins_for_gpio_bits[17]	auto[1]	auto[1]	5136302	1			T29	41		T30	15		T31	94
bins_for_gpio_bits[18]	auto[0]	auto[0]	7877316	1			T29	257		T30	12		T31	364
bins_for_gpio_bits[18]	auto[0]	auto[1]	243412	1			T29	1		T31	35		T34	13
bins_for_gpio_bits[18]	auto[1]	auto[0]	243636	1			T29	1		T31	36		T34	13
bins_for_gpio_bits[18]	auto[1]	auto[1]	5148793	1			T29	42		T30	17		T31	125
bins_for_gpio_bits[19]	auto[0]	auto[0]	7884700	1			T29	260		T30	18		T31	399
bins_for_gpio_bits[19]	auto[0]	auto[1]	243529	1			T29	2		T31	30		T32	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	243802	1			T29	2		T31	30		T34	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	5141126	1			T29	37		T30	11		T31	101
bins_for_gpio_bits[20]	auto[0]	auto[0]	7889135	1			T29	227		T30	14		T31	337
bins_for_gpio_bits[20]	auto[0]	auto[1]	243513	1			T29	4		T31	37		T34	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	243769	1			T29	5		T31	37		T34	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	5136740	1			T29	65		T30	15		T31	149
bins_for_gpio_bits[21]	auto[0]	auto[0]	7878970	1			T29	233		T30	17		T31	405
bins_for_gpio_bits[21]	auto[0]	auto[1]	244193	1			T29	7		T31	32		T34	12
bins_for_gpio_bits[21]	auto[1]	auto[0]	244423	1			T29	7		T31	33		T34	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	5145571	1			T29	54		T30	12		T31	90
bins_for_gpio_bits[22]	auto[0]	auto[0]	7871013	1			T29	230		T30	21		T31	407
bins_for_gpio_bits[22]	auto[0]	auto[1]	243906	1			T29	4		T31	30		T34	17
bins_for_gpio_bits[22]	auto[1]	auto[0]	244076	1			T29	4		T31	30		T34	17
bins_for_gpio_bits[22]	auto[1]	auto[1]	5154162	1			T29	63		T30	8		T31	93
bins_for_gpio_bits[23]	auto[0]	auto[0]	7882112	1			T29	221		T30	14		T31	393
bins_for_gpio_bits[23]	auto[0]	auto[1]	243899	1			T29	8		T31	29		T34	15
bins_for_gpio_bits[23]	auto[1]	auto[0]	244139	1			T29	8		T31	29		T34	15
bins_for_gpio_bits[23]	auto[1]	auto[1]	5143007	1			T29	64		T30	15		T31	109
bins_for_gpio_bits[24]	auto[0]	auto[0]	7888251	1			T29	243		T30	12		T31	376
bins_for_gpio_bits[24]	auto[0]	auto[1]	244052	1			T29	2		T31	32		T34	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	244296	1			T29	2		T31	32		T34	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	5136558	1			T29	54		T30	17		T31	120
bins_for_gpio_bits[25]	auto[0]	auto[0]	7880410	1			T29	239		T30	10		T31	343
bins_for_gpio_bits[25]	auto[0]	auto[1]	244632	1			T29	5		T31	36		T34	16
bins_for_gpio_bits[25]	auto[1]	auto[0]	244886	1			T29	5		T31	37		T34	16
bins_for_gpio_bits[25]	auto[1]	auto[1]	5143229	1			T29	52		T30	19		T31	144
bins_for_gpio_bits[26]	auto[0]	auto[0]	7886498	1			T29	244		T30	23		T31	382
bins_for_gpio_bits[26]	auto[0]	auto[1]	243215	1			T29	2		T31	29		T34	13
bins_for_gpio_bits[26]	auto[1]	auto[0]	243457	1			T29	2		T31	29		T34	14
bins_for_gpio_bits[26]	auto[1]	auto[1]	5139987	1			T29	53		T30	6		T31	120
bins_for_gpio_bits[27]	auto[0]	auto[0]	7870982	1			T29	227		T30	23		T31	367
bins_for_gpio_bits[27]	auto[0]	auto[1]	243685	1			T29	8		T31	34		T34	11
bins_for_gpio_bits[27]	auto[1]	auto[0]	243959	1			T29	8		T31	35		T34	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	5154531	1			T29	58		T30	6		T31	124
bins_for_gpio_bits[28]	auto[0]	auto[0]	7897811	1			T29	239		T30	10		T31	391
bins_for_gpio_bits[28]	auto[0]	auto[1]	243663	1			T29	4		T31	34		T34	12
bins_for_gpio_bits[28]	auto[1]	auto[0]	243900	1			T29	4		T31	35		T34	12
bins_for_gpio_bits[28]	auto[1]	auto[1]	5127783	1			T29	54		T30	19		T31	100
bins_for_gpio_bits[29]	auto[0]	auto[0]	7881339	1			T29	253		T30	14		T31	359
bins_for_gpio_bits[29]	auto[0]	auto[1]	243008	1			T29	3		T31	32		T32	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	243288	1			T29	3		T31	33		T34	14
bins_for_gpio_bits[29]	auto[1]	auto[1]	5145522	1			T29	42		T30	15		T31	136
bins_for_gpio_bits[30]	auto[0]	auto[0]	7881895	1			T29	250		T30	13		T31	353
bins_for_gpio_bits[30]	auto[0]	auto[1]	243541	1			T29	3		T31	33		T34	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	243783	1			T29	3		T31	33		T34	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	5143938	1			T29	45		T30	16		T31	141
bins_for_gpio_bits[31]	auto[0]	auto[0]	7875319	1			T29	236		T30	19		T31	361
bins_for_gpio_bits[31]	auto[0]	auto[1]	243854	1			T29	6		T31	37		T34	15
bins_for_gpio_bits[31]	auto[1]	auto[0]	244098	1			T29	6		T31	37		T34	16
bins_for_gpio_bits[31]	auto[1]	auto[1]	5149886	1			T29	53		T30	10		T31	125