Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870720 |
1 |
|
|
T29 |
174 |
|
T30 |
33 |
|
T31 |
300 |
| auto[1] |
5801372 |
1 |
|
|
T30 |
24 |
|
T32 |
46 |
|
T19 |
32 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12938045 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
734047 |
1 |
|
|
T30 |
2 |
|
T32 |
2 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884577 |
1 |
|
|
T29 |
174 |
|
T30 |
30 |
|
T31 |
300 |
| auto[1] |
5787515 |
1 |
|
|
T30 |
27 |
|
T32 |
42 |
|
T19 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2532435 |
1 |
|
|
T30 |
8 |
|
T32 |
27 |
|
T19 |
21 |
| auto[1] |
auto[0] |
auto[1] |
367046 |
1 |
|
|
T30 |
1 |
|
T19 |
1 |
|
T21 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2521033 |
1 |
|
|
T30 |
17 |
|
T32 |
13 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
367001 |
1 |
|
|
T30 |
1 |
|
T32 |
2 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7875811 |
1 |
|
|
T29 |
174 |
|
T30 |
28 |
|
T31 |
300 |
| auto[1] |
5796281 |
1 |
|
|
T30 |
29 |
|
T32 |
39 |
|
T19 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12941050 |
1 |
|
|
T29 |
174 |
|
T30 |
56 |
|
T31 |
300 |
| auto[1] |
731042 |
1 |
|
|
T30 |
1 |
|
T32 |
2 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904180 |
1 |
|
|
T29 |
174 |
|
T30 |
37 |
|
T31 |
300 |
| auto[1] |
5767912 |
1 |
|
|
T30 |
20 |
|
T32 |
57 |
|
T19 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2538176 |
1 |
|
|
T30 |
10 |
|
T32 |
40 |
|
T19 |
28 |
| auto[1] |
auto[0] |
auto[1] |
367503 |
1 |
|
|
T30 |
1 |
|
T32 |
2 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2498694 |
1 |
|
|
T30 |
9 |
|
T32 |
15 |
|
T21 |
83 |
| auto[1] |
auto[1] |
auto[1] |
363539 |
1 |
|
|
T21 |
3 |
|
T116 |
116 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7845961 |
1 |
|
|
T29 |
174 |
|
T30 |
46 |
|
T31 |
300 |
| auto[1] |
5826131 |
1 |
|
|
T30 |
11 |
|
T32 |
32 |
|
T19 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12938662 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
733430 |
1 |
|
|
T30 |
2 |
|
T32 |
1 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878968 |
1 |
|
|
T29 |
174 |
|
T30 |
31 |
|
T31 |
300 |
| auto[1] |
5793124 |
1 |
|
|
T30 |
26 |
|
T32 |
36 |
|
T19 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2514365 |
1 |
|
|
T30 |
14 |
|
T32 |
17 |
|
T19 |
21 |
| auto[1] |
auto[0] |
auto[1] |
364623 |
1 |
|
|
T30 |
1 |
|
T19 |
1 |
|
T21 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2545329 |
1 |
|
|
T30 |
10 |
|
T32 |
18 |
|
T19 |
6 |
| auto[1] |
auto[1] |
auto[1] |
368807 |
1 |
|
|
T30 |
1 |
|
T32 |
1 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7874772 |
1 |
|
|
T29 |
174 |
|
T30 |
36 |
|
T31 |
300 |
| auto[1] |
5797320 |
1 |
|
|
T30 |
21 |
|
T32 |
35 |
|
T19 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12933913 |
1 |
|
|
T29 |
174 |
|
T30 |
53 |
|
T31 |
300 |
| auto[1] |
738179 |
1 |
|
|
T30 |
4 |
|
T32 |
1 |
|
T21 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7859017 |
1 |
|
|
T29 |
174 |
|
T30 |
18 |
|
T31 |
300 |
| auto[1] |
5813075 |
1 |
|
|
T30 |
39 |
|
T32 |
49 |
|
T19 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2544810 |
1 |
|
|
T30 |
22 |
|
T32 |
30 |
|
T19 |
3 |
| auto[1] |
auto[0] |
auto[1] |
370356 |
1 |
|
|
T30 |
3 |
|
T21 |
4 |
|
T116 |
115 |
| auto[1] |
auto[1] |
auto[0] |
2530086 |
1 |
|
|
T30 |
13 |
|
T32 |
18 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
367823 |
1 |
|
|
T30 |
1 |
|
T32 |
1 |
|
T21 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7864663 |
1 |
|
|
T29 |
174 |
|
T30 |
27 |
|
T31 |
300 |
| auto[1] |
5807429 |
1 |
|
|
T30 |
30 |
|
T32 |
49 |
|
T19 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12936321 |
1 |
|
|
T29 |
174 |
|
T30 |
53 |
|
T31 |
300 |
| auto[1] |
735771 |
1 |
|
|
T30 |
4 |
|
T32 |
1 |
|
T21 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7873640 |
1 |
|
|
T29 |
174 |
|
T30 |
22 |
|
T31 |
300 |
| auto[1] |
5798452 |
1 |
|
|
T30 |
35 |
|
T32 |
47 |
|
T19 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2530687 |
1 |
|
|
T30 |
15 |
|
T32 |
31 |
|
T19 |
13 |
| auto[1] |
auto[0] |
auto[1] |
367784 |
1 |
|
|
T30 |
2 |
|
T21 |
3 |
|
T116 |
162 |
| auto[1] |
auto[1] |
auto[0] |
2531994 |
1 |
|
|
T30 |
16 |
|
T32 |
15 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
367987 |
1 |
|
|
T30 |
2 |
|
T32 |
1 |
|
T21 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7843000 |
1 |
|
|
T29 |
174 |
|
T30 |
51 |
|
T31 |
300 |
| auto[1] |
5829092 |
1 |
|
|
T30 |
6 |
|
T32 |
28 |
|
T19 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12939190 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
732902 |
1 |
|
|
T32 |
1 |
|
T19 |
1 |
|
T21 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878182 |
1 |
|
|
T29 |
174 |
|
T30 |
51 |
|
T31 |
300 |
| auto[1] |
5793910 |
1 |
|
|
T30 |
6 |
|
T32 |
31 |
|
T19 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2511603 |
1 |
|
|
T30 |
6 |
|
T32 |
21 |
|
T19 |
20 |
| auto[1] |
auto[0] |
auto[1] |
364049 |
1 |
|
|
T32 |
1 |
|
T19 |
1 |
|
T21 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2549405 |
1 |
|
|
T32 |
9 |
|
T21 |
49 |
|
T116 |
304 |
| auto[1] |
auto[1] |
auto[1] |
368853 |
1 |
|
|
T21 |
1 |
|
T116 |
77 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7925145 |
1 |
|
|
T29 |
174 |
|
T30 |
34 |
|
T31 |
300 |
| auto[1] |
5746947 |
1 |
|
|
T30 |
23 |
|
T32 |
34 |
|
T19 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12937800 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
734292 |
1 |
|
|
T32 |
1 |
|
T19 |
1 |
|
T21 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870967 |
1 |
|
|
T29 |
174 |
|
T30 |
51 |
|
T31 |
300 |
| auto[1] |
5801125 |
1 |
|
|
T30 |
6 |
|
T32 |
22 |
|
T19 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2557486 |
1 |
|
|
T30 |
5 |
|
T32 |
8 |
|
T19 |
15 |
| auto[1] |
auto[0] |
auto[1] |
370680 |
1 |
|
|
T32 |
1 |
|
T19 |
1 |
|
T21 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2509347 |
1 |
|
|
T30 |
1 |
|
T32 |
13 |
|
T21 |
71 |
| auto[1] |
auto[1] |
auto[1] |
363612 |
1 |
|
|
T21 |
2 |
|
T116 |
150 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7839912 |
1 |
|
|
T29 |
174 |
|
T30 |
23 |
|
T31 |
300 |
| auto[1] |
5832180 |
1 |
|
|
T30 |
34 |
|
T32 |
39 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12932616 |
1 |
|
|
T29 |
174 |
|
T30 |
56 |
|
T31 |
300 |
| auto[1] |
739476 |
1 |
|
|
T30 |
1 |
|
T32 |
3 |
|
T21 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7848436 |
1 |
|
|
T29 |
174 |
|
T30 |
24 |
|
T31 |
300 |
| auto[1] |
5823656 |
1 |
|
|
T30 |
33 |
|
T32 |
36 |
|
T19 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2522918 |
1 |
|
|
T30 |
6 |
|
T32 |
25 |
|
T19 |
7 |
| auto[1] |
auto[0] |
auto[1] |
366905 |
1 |
|
|
T32 |
2 |
|
T21 |
1 |
|
T116 |
106 |
| auto[1] |
auto[1] |
auto[0] |
2561262 |
1 |
|
|
T30 |
26 |
|
T32 |
8 |
|
T21 |
45 |
| auto[1] |
auto[1] |
auto[1] |
372571 |
1 |
|
|
T30 |
1 |
|
T32 |
1 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892004 |
1 |
|
|
T29 |
174 |
|
T30 |
17 |
|
T31 |
300 |
| auto[1] |
5780088 |
1 |
|
|
T30 |
40 |
|
T32 |
57 |
|
T19 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12932442 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
739650 |
1 |
|
|
T30 |
2 |
|
T32 |
2 |
|
T21 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7847250 |
1 |
|
|
T29 |
174 |
|
T30 |
16 |
|
T31 |
300 |
| auto[1] |
5824842 |
1 |
|
|
T30 |
41 |
|
T32 |
24 |
|
T19 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2555958 |
1 |
|
|
T30 |
16 |
|
T32 |
8 |
|
T19 |
10 |
| auto[1] |
auto[0] |
auto[1] |
373109 |
1 |
|
|
T32 |
1 |
|
T21 |
5 |
|
T116 |
124 |
| auto[1] |
auto[1] |
auto[0] |
2529234 |
1 |
|
|
T30 |
23 |
|
T32 |
14 |
|
T19 |
10 |
| auto[1] |
auto[1] |
auto[1] |
366541 |
1 |
|
|
T30 |
2 |
|
T32 |
1 |
|
T21 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7888250 |
1 |
|
|
T29 |
174 |
|
T30 |
26 |
|
T31 |
300 |
| auto[1] |
5783842 |
1 |
|
|
T30 |
31 |
|
T32 |
27 |
|
T19 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12938600 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
733492 |
1 |
|
|
T32 |
4 |
|
T19 |
1 |
|
T21 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889642 |
1 |
|
|
T29 |
174 |
|
T30 |
37 |
|
T31 |
300 |
| auto[1] |
5782450 |
1 |
|
|
T30 |
20 |
|
T32 |
46 |
|
T19 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2528625 |
1 |
|
|
T30 |
6 |
|
T32 |
33 |
|
T19 |
18 |
| auto[1] |
auto[0] |
auto[1] |
367591 |
1 |
|
|
T32 |
4 |
|
T19 |
1 |
|
T21 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2520333 |
1 |
|
|
T30 |
14 |
|
T32 |
9 |
|
T21 |
53 |
| auto[1] |
auto[1] |
auto[1] |
365901 |
1 |
|
|
T21 |
1 |
|
T116 |
93 |
|
T2 |
2302 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880981 |
1 |
|
|
T29 |
174 |
|
T30 |
34 |
|
T31 |
300 |
| auto[1] |
5791111 |
1 |
|
|
T30 |
23 |
|
T32 |
56 |
|
T19 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12935262 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
736830 |
1 |
|
|
T30 |
2 |
|
T32 |
2 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7849758 |
1 |
|
|
T29 |
174 |
|
T30 |
28 |
|
T31 |
300 |
| auto[1] |
5822334 |
1 |
|
|
T30 |
29 |
|
T32 |
49 |
|
T19 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2539399 |
1 |
|
|
T30 |
13 |
|
T32 |
14 |
|
T19 |
18 |
| auto[1] |
auto[0] |
auto[1] |
368612 |
1 |
|
|
T30 |
1 |
|
T19 |
1 |
|
T21 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2546105 |
1 |
|
|
T30 |
14 |
|
T32 |
33 |
|
T19 |
9 |
| auto[1] |
auto[1] |
auto[1] |
368218 |
1 |
|
|
T30 |
1 |
|
T32 |
2 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894088 |
1 |
|
|
T29 |
174 |
|
T30 |
26 |
|
T31 |
300 |
| auto[1] |
5778004 |
1 |
|
|
T30 |
31 |
|
T32 |
41 |
|
T19 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12936582 |
1 |
|
|
T29 |
174 |
|
T30 |
56 |
|
T31 |
300 |
| auto[1] |
735510 |
1 |
|
|
T30 |
1 |
|
T21 |
11 |
|
T116 |
194 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7862445 |
1 |
|
|
T29 |
174 |
|
T30 |
38 |
|
T31 |
300 |
| auto[1] |
5809647 |
1 |
|
|
T30 |
19 |
|
T32 |
47 |
|
T19 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2554102 |
1 |
|
|
T30 |
14 |
|
T32 |
36 |
|
T19 |
20 |
| auto[1] |
auto[0] |
auto[1] |
369876 |
1 |
|
|
T21 |
6 |
|
T116 |
87 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2520035 |
1 |
|
|
T30 |
4 |
|
T32 |
11 |
|
T21 |
92 |
| auto[1] |
auto[1] |
auto[1] |
365634 |
1 |
|
|
T30 |
1 |
|
T21 |
5 |
|
T116 |
107 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885840 |
1 |
|
|
T29 |
174 |
|
T30 |
16 |
|
T31 |
300 |
| auto[1] |
5786252 |
1 |
|
|
T30 |
41 |
|
T32 |
35 |
|
T19 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12931814 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
740278 |
1 |
|
|
T30 |
2 |
|
T32 |
3 |
|
T21 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7836636 |
1 |
|
|
T29 |
174 |
|
T30 |
32 |
|
T31 |
300 |
| auto[1] |
5835456 |
1 |
|
|
T30 |
25 |
|
T32 |
47 |
|
T19 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2551861 |
1 |
|
|
T32 |
24 |
|
T19 |
3 |
|
T21 |
131 |
| auto[1] |
auto[0] |
auto[1] |
370642 |
1 |
|
|
T32 |
1 |
|
T21 |
5 |
|
T116 |
145 |
| auto[1] |
auto[1] |
auto[0] |
2543317 |
1 |
|
|
T30 |
23 |
|
T32 |
20 |
|
T19 |
6 |
| auto[1] |
auto[1] |
auto[1] |
369636 |
1 |
|
|
T30 |
2 |
|
T32 |
2 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891971 |
1 |
|
|
T29 |
174 |
|
T30 |
42 |
|
T31 |
300 |
| auto[1] |
5780121 |
1 |
|
|
T30 |
15 |
|
T32 |
53 |
|
T19 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12939315 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
732777 |
1 |
|
|
T30 |
2 |
|
T32 |
1 |
|
T21 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7888781 |
1 |
|
|
T29 |
174 |
|
T30 |
41 |
|
T31 |
300 |
| auto[1] |
5783311 |
1 |
|
|
T30 |
16 |
|
T32 |
50 |
|
T19 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2532554 |
1 |
|
|
T30 |
9 |
|
T32 |
27 |
|
T19 |
3 |
| auto[1] |
auto[0] |
auto[1] |
367700 |
1 |
|
|
T30 |
1 |
|
T21 |
7 |
|
T116 |
75 |
| auto[1] |
auto[1] |
auto[0] |
2517980 |
1 |
|
|
T30 |
5 |
|
T32 |
22 |
|
T19 |
12 |
| auto[1] |
auto[1] |
auto[1] |
365077 |
1 |
|
|
T30 |
1 |
|
T32 |
1 |
|
T21 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7865187 |
1 |
|
|
T29 |
174 |
|
T30 |
27 |
|
T31 |
300 |
| auto[1] |
5806905 |
1 |
|
|
T30 |
30 |
|
T32 |
45 |
|
T19 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12933988 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
738104 |
1 |
|
|
T32 |
1 |
|
T21 |
13 |
|
T116 |
220 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7853413 |
1 |
|
|
T29 |
174 |
|
T30 |
30 |
|
T31 |
300 |
| auto[1] |
5818679 |
1 |
|
|
T30 |
27 |
|
T32 |
31 |
|
T19 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2533893 |
1 |
|
|
T30 |
9 |
|
T32 |
22 |
|
T19 |
6 |
| auto[1] |
auto[0] |
auto[1] |
367753 |
1 |
|
|
T32 |
1 |
|
T21 |
9 |
|
T116 |
100 |
| auto[1] |
auto[1] |
auto[0] |
2546682 |
1 |
|
|
T30 |
18 |
|
T32 |
8 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
370351 |
1 |
|
|
T21 |
4 |
|
T116 |
120 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892732 |
1 |
|
|
T29 |
174 |
|
T30 |
38 |
|
T31 |
300 |
| auto[1] |
5779360 |
1 |
|
|
T30 |
19 |
|
T32 |
24 |
|
T19 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12931853 |
1 |
|
|
T29 |
174 |
|
T30 |
54 |
|
T31 |
300 |
| auto[1] |
740239 |
1 |
|
|
T30 |
3 |
|
T21 |
3 |
|
T116 |
212 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7844570 |
1 |
|
|
T29 |
174 |
|
T30 |
8 |
|
T31 |
300 |
| auto[1] |
5827522 |
1 |
|
|
T30 |
49 |
|
T32 |
36 |
|
T19 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2554369 |
1 |
|
|
T30 |
29 |
|
T32 |
31 |
|
T19 |
7 |
| auto[1] |
auto[0] |
auto[1] |
372690 |
1 |
|
|
T30 |
2 |
|
T21 |
1 |
|
T116 |
94 |
| auto[1] |
auto[1] |
auto[0] |
2532914 |
1 |
|
|
T30 |
17 |
|
T32 |
5 |
|
T21 |
71 |
| auto[1] |
auto[1] |
auto[1] |
367549 |
1 |
|
|
T30 |
1 |
|
T21 |
2 |
|
T116 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882394 |
1 |
|
|
T29 |
174 |
|
T30 |
31 |
|
T31 |
300 |
| auto[1] |
5789698 |
1 |
|
|
T30 |
26 |
|
T32 |
35 |
|
T19 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12931791 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
740301 |
1 |
|
|
T30 |
2 |
|
T21 |
10 |
|
T116 |
195 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7829675 |
1 |
|
|
T29 |
174 |
|
T30 |
22 |
|
T31 |
300 |
| auto[1] |
5842417 |
1 |
|
|
T30 |
35 |
|
T32 |
26 |
|
T19 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2556506 |
1 |
|
|
T30 |
18 |
|
T32 |
23 |
|
T19 |
6 |
| auto[1] |
auto[0] |
auto[1] |
370912 |
1 |
|
|
T21 |
4 |
|
T116 |
67 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2545610 |
1 |
|
|
T30 |
15 |
|
T32 |
3 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
369389 |
1 |
|
|
T30 |
2 |
|
T21 |
6 |
|
T116 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881484 |
1 |
|
|
T29 |
174 |
|
T30 |
36 |
|
T31 |
300 |
| auto[1] |
5790608 |
1 |
|
|
T30 |
21 |
|
T32 |
36 |
|
T19 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12939689 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
732403 |
1 |
|
|
T30 |
2 |
|
T32 |
1 |
|
T21 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885955 |
1 |
|
|
T29 |
174 |
|
T30 |
15 |
|
T31 |
300 |
| auto[1] |
5786137 |
1 |
|
|
T30 |
42 |
|
T32 |
43 |
|
T19 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2538800 |
1 |
|
|
T30 |
20 |
|
T32 |
34 |
|
T19 |
13 |
| auto[1] |
auto[0] |
auto[1] |
368903 |
1 |
|
|
T30 |
1 |
|
T21 |
2 |
|
T116 |
131 |
| auto[1] |
auto[1] |
auto[0] |
2514934 |
1 |
|
|
T30 |
20 |
|
T32 |
8 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
363500 |
1 |
|
|
T30 |
1 |
|
T32 |
1 |
|
T116 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881797 |
1 |
|
|
T29 |
174 |
|
T30 |
21 |
|
T31 |
300 |
| auto[1] |
5790295 |
1 |
|
|
T30 |
36 |
|
T32 |
30 |
|
T19 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12934112 |
1 |
|
|
T29 |
174 |
|
T30 |
56 |
|
T31 |
300 |
| auto[1] |
737980 |
1 |
|
|
T30 |
1 |
|
T32 |
1 |
|
T21 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7856598 |
1 |
|
|
T29 |
174 |
|
T30 |
30 |
|
T31 |
300 |
| auto[1] |
5815494 |
1 |
|
|
T30 |
27 |
|
T32 |
38 |
|
T19 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2537034 |
1 |
|
|
T30 |
3 |
|
T32 |
30 |
|
T19 |
18 |
| auto[1] |
auto[0] |
auto[1] |
369450 |
1 |
|
|
T32 |
1 |
|
T21 |
3 |
|
T116 |
141 |
| auto[1] |
auto[1] |
auto[0] |
2540480 |
1 |
|
|
T30 |
23 |
|
T32 |
7 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[1] |
368530 |
1 |
|
|
T30 |
1 |
|
T21 |
2 |
|
T116 |
148 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870395 |
1 |
|
|
T29 |
174 |
|
T30 |
26 |
|
T31 |
300 |
| auto[1] |
5801697 |
1 |
|
|
T30 |
31 |
|
T32 |
27 |
|
T19 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12937204 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
734888 |
1 |
|
|
T19 |
1 |
|
T21 |
12 |
|
T116 |
214 |