Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869523 |
1 |
|
|
T29 |
174 |
|
T30 |
26 |
|
T31 |
300 |
| auto[1] |
5802569 |
1 |
|
|
T30 |
31 |
|
T32 |
48 |
|
T19 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12943228 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
728864 |
1 |
|
|
T32 |
1 |
|
T19 |
1 |
|
T21 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902398 |
1 |
|
|
T29 |
174 |
|
T30 |
44 |
|
T31 |
300 |
| auto[1] |
5769694 |
1 |
|
|
T30 |
13 |
|
T32 |
36 |
|
T19 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2511978 |
1 |
|
|
T32 |
14 |
|
T19 |
11 |
|
T21 |
71 |
| auto[1] |
auto[0] |
auto[1] |
363533 |
1 |
|
|
T32 |
1 |
|
T19 |
1 |
|
T21 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2528852 |
1 |
|
|
T30 |
13 |
|
T32 |
21 |
|
T19 |
6 |
| auto[1] |
auto[1] |
auto[1] |
365331 |
1 |
|
|
T21 |
5 |
|
T116 |
79 |
|
T1 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |