Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7845961 |
1 |
|
|
T29 |
174 |
|
T30 |
46 |
|
T31 |
300 |
| auto[1] |
5826131 |
1 |
|
|
T30 |
11 |
|
T32 |
32 |
|
T19 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11307935 |
1 |
|
|
T29 |
174 |
|
T30 |
52 |
|
T31 |
300 |
| auto[1] |
2364157 |
1 |
|
|
T30 |
5 |
|
T32 |
10 |
|
T19 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7888241 |
1 |
|
|
T29 |
174 |
|
T30 |
52 |
|
T31 |
300 |
| auto[1] |
5783851 |
1 |
|
|
T30 |
5 |
|
T32 |
14 |
|
T19 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1703275 |
1 |
|
|
T32 |
4 |
|
T19 |
15 |
|
T21 |
65 |
| auto[1] |
auto[0] |
auto[1] |
1181278 |
1 |
|
|
T32 |
7 |
|
T19 |
3 |
|
T21 |
20 |
| auto[1] |
auto[1] |
auto[0] |
1716419 |
1 |
|
|
T21 |
12 |
|
T116 |
244 |
|
T1 |
103 |
| auto[1] |
auto[1] |
auto[1] |
1182879 |
1 |
|
|
T30 |
5 |
|
T32 |
3 |
|
T21 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |