Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7843000 |
1 |
|
|
T29 |
174 |
|
T30 |
51 |
|
T31 |
300 |
| auto[1] |
5829092 |
1 |
|
|
T30 |
6 |
|
T32 |
28 |
|
T19 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11294458 |
1 |
|
|
T29 |
174 |
|
T30 |
33 |
|
T31 |
300 |
| auto[1] |
2377634 |
1 |
|
|
T30 |
24 |
|
T32 |
2 |
|
T19 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7857875 |
1 |
|
|
T29 |
174 |
|
T30 |
19 |
|
T31 |
300 |
| auto[1] |
5814217 |
1 |
|
|
T30 |
38 |
|
T32 |
10 |
|
T19 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1711295 |
1 |
|
|
T30 |
14 |
|
T32 |
8 |
|
T19 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1183561 |
1 |
|
|
T30 |
24 |
|
T32 |
2 |
|
T19 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1725288 |
1 |
|
|
T21 |
45 |
|
T116 |
224 |
|
T1 |
67 |
| auto[1] |
auto[1] |
auto[1] |
1194073 |
1 |
|
|
T19 |
5 |
|
T21 |
32 |
|
T116 |
196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |