Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891971 |
1 |
|
|
T29 |
174 |
|
T30 |
42 |
|
T31 |
300 |
| auto[1] |
5780121 |
1 |
|
|
T30 |
15 |
|
T32 |
53 |
|
T19 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11297667 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
2374425 |
1 |
|
|
T32 |
4 |
|
T19 |
27 |
|
T21 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7855512 |
1 |
|
|
T29 |
174 |
|
T30 |
52 |
|
T31 |
300 |
| auto[1] |
5816580 |
1 |
|
|
T30 |
5 |
|
T32 |
23 |
|
T19 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1735258 |
1 |
|
|
T32 |
9 |
|
T19 |
10 |
|
T21 |
61 |
| auto[1] |
auto[0] |
auto[1] |
1193431 |
1 |
|
|
T32 |
2 |
|
T19 |
15 |
|
T21 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1706897 |
1 |
|
|
T30 |
5 |
|
T32 |
10 |
|
T21 |
90 |
| auto[1] |
auto[1] |
auto[1] |
1180994 |
1 |
|
|
T32 |
2 |
|
T19 |
12 |
|
T21 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |