Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7865187 |
1 |
|
|
T29 |
174 |
|
T30 |
27 |
|
T31 |
300 |
| auto[1] |
5806905 |
1 |
|
|
T30 |
30 |
|
T32 |
45 |
|
T19 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11305512 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
2366580 |
1 |
|
|
T21 |
51 |
|
T116 |
665 |
|
T1 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889496 |
1 |
|
|
T29 |
174 |
|
T30 |
47 |
|
T31 |
300 |
| auto[1] |
5782596 |
1 |
|
|
T30 |
10 |
|
T32 |
10 |
|
T19 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1702732 |
1 |
|
|
T30 |
5 |
|
T32 |
4 |
|
T19 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1183707 |
1 |
|
|
T21 |
33 |
|
T116 |
336 |
|
T1 |
49 |
| auto[1] |
auto[1] |
auto[0] |
1713284 |
1 |
|
|
T30 |
5 |
|
T32 |
6 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1182873 |
1 |
|
|
T21 |
18 |
|
T116 |
329 |
|
T1 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |