Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892732 |
1 |
|
|
T29 |
174 |
|
T30 |
38 |
|
T31 |
300 |
| auto[1] |
5779360 |
1 |
|
|
T30 |
19 |
|
T32 |
24 |
|
T19 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11297843 |
1 |
|
|
T29 |
174 |
|
T30 |
52 |
|
T31 |
300 |
| auto[1] |
2374249 |
1 |
|
|
T30 |
5 |
|
T32 |
3 |
|
T19 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7865893 |
1 |
|
|
T29 |
174 |
|
T30 |
52 |
|
T31 |
300 |
| auto[1] |
5806199 |
1 |
|
|
T30 |
5 |
|
T32 |
14 |
|
T19 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1723939 |
1 |
|
|
T32 |
11 |
|
T19 |
11 |
|
T21 |
30 |
| auto[1] |
auto[0] |
auto[1] |
1190156 |
1 |
|
|
T30 |
5 |
|
T19 |
13 |
|
T21 |
26 |
| auto[1] |
auto[1] |
auto[0] |
1708011 |
1 |
|
|
T19 |
2 |
|
T21 |
45 |
|
T116 |
335 |
| auto[1] |
auto[1] |
auto[1] |
1184093 |
1 |
|
|
T32 |
3 |
|
T21 |
23 |
|
T116 |
324 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |