Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7871301 |
1 |
|
|
T29 |
174 |
|
T30 |
34 |
|
T31 |
300 |
| auto[1] |
5800791 |
1 |
|
|
T30 |
23 |
|
T32 |
42 |
|
T19 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12935860 |
1 |
|
|
T29 |
174 |
|
T30 |
54 |
|
T31 |
300 |
| auto[1] |
736232 |
1 |
|
|
T30 |
3 |
|
T32 |
2 |
|
T21 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7851763 |
1 |
|
|
T29 |
174 |
|
T30 |
12 |
|
T31 |
300 |
| auto[1] |
5820329 |
1 |
|
|
T30 |
45 |
|
T32 |
53 |
|
T19 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2540116 |
1 |
|
|
T30 |
21 |
|
T32 |
34 |
|
T19 |
13 |
| auto[1] |
auto[0] |
auto[1] |
367681 |
1 |
|
|
T30 |
2 |
|
T32 |
2 |
|
T21 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2543981 |
1 |
|
|
T30 |
21 |
|
T32 |
17 |
|
T19 |
6 |
| auto[1] |
auto[1] |
auto[1] |
368551 |
1 |
|
|
T30 |
1 |
|
T21 |
5 |
|
T116 |
137 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |